VLSI DESIGN (VII-SEM.) Unit - | : Practical Consideration and Technology in VLSI Design : Introduction, Size and Complexity of Integrated Circuits, The Microelectronics Field, IC Production Process, Processing Steps, Packaging and Testing, MOS Processes, NMOS Process, CMOS Process, Bipolar Technology, Hybrid Technology, Design Rules and Process Parameters. Unit - Il: Device Modeling : DC Models, Small Signal Models, MOS Models, MOSFET Models in High Frequency and small Signal, Short Channel Devices, Sub threshold Operations, Modeling Noise Sources in MOSFET’s, Diode Models, Bipolar Models, Passive Component Models. Unit - Ill : Circuit Simulation : Introduction, Circuit Simulation Using Spice, MOSFET Model, Level 1 Large Signal Mode: Level 2 Large Signal Model, High Frequency Model, Noise Model of MOSFET, Large signal Diode Current, High Frequency BJT model, BUT Noise Model, Temperature Dependence of BJT. Unit - IV : Structured Digital Circuits and Systems : Random Logic and Structured Logic Forms, Register Storage Circuits, Quasi Static Register Celis, A Static Register Cell, Micro Coded Controllers, Microprocessor Design, Systolic Arrays, Bit-Serial Processing Elements, Algotronix. Unit - V : CMOS Processing Technology : Basic CMOS Technology, A Basic n-well CMOS Process, Twin Tub Processes, CMOS Process Enhancement, Interconnects and Circuit Elements, Layout Design Rules, Latch up, Physical Origin, Latch up Triggering, Latch up Prevention, Internal Latch up Prevention Techniques. Price : Rs. 105.00 (Rs. One Hundred Five Only) Edition : 2020 —VLSI DESIGN © (VII-SeEM.) iderati Jogyin VLSI Design tic ideration & Technol patel onery of norte CCU, The ction, veenearoncsF Ic roguction Prove 5 Processes, Nemna yy, Hybrid Technol Parameters. rg steps, Packaging and Testing. SP eepaes, GMOS Process, Bipolar ‘ogy, Design Rules and Process and small Signal, Short Channel Models in High Feo Operations, Modeling Noise Sources in Devices, Sub Threshold Operal MOSFET's. Diode Models, unr. irosucton, MOSFET Model, Level Large Signal Mode Node. igh Frequency Mode, Noise Model of MOSFET, Large joe Cure igh Frequency BJT mod Dependence of BIT 6) UNIT-1v Random Logic and Structured Logic Forms, Register Storage Microcoded Controllers, Microprocessor Design, Systolic Arrays, Bit-Serial Processing Elements, Algotronix... : UNIT -V: CMOS Processing Technology Basic CMOS Technology, ABasic n- tub Pr0COSS€S on rnnnmanrnn CMOS Process Enhancement Elements... PRACTICAL CONSIDERATION & TECHNOLOGY IN VLSI DESIGN INTRODUCTION, SIZE AND COMPLEXITY OF INTEGRATED CIRCUITS, THE MICROELECTRONICS FIELD Q.1. Write in brief historical overview of VISE technoloxy. Or Fe inconsequentisT-aTT his approach has been phenomenal. Noyce and k what has become the VLSI design field. Ineaty day as a semiconductor. Present semiconductor becaus Some other mater niche large number of transistors, over one million in some designs. Tradi Which involved iteration at the breadboard level proved impract integrated circuits. This is because of poor designer powerful graphics-intense workstations. Integrated circuit ical equipments and materials intaining close tolerances and small geometries VLSI design Ans. (i) Integrated Circuit ~ The combination of intereonaceted cteuit ‘lements inseparably associated on or wi us substrate is known as integrated circuit. i) Mo place upon or wi lements formed wi the substrate, | | |4 vEsi Desir I~ iii) Hy types 1s Mi Test Cell or Test Lead ~ | ‘a few times on eacl cal prope ietermines crystal orientation. This seed crystal le erystal growth, Quartz erucible is used to rounded by a graphite radiator, Radio perature is maintained at a keep the melt, induction heats the era foedemes above the meting fe dees a nee ing ltd afer the sedi dipped ta the melt. The molten polyerystal son melts the tip of the seed, and as i is withdrawn refreezing occurs. seed as the melt freezes. This method is With the help of seed rotation rate and seed wi 10 waters are usual culling edge diamond blades. Generally, wafers are between 0.25 mm and 1.0 tm thick, depending on their diameter. At least one face is polished to a flat, Q4. Define the test plug or process control bar. Ans. A specilic chip which is repeated only a few 0 ¥. Process parameters o sd by this chip. The validity of the process is veri processing, Ifthe determination of key parameters atthe test plug level ar acceptable, the wafer 1s discarded 0.5. Write down the approaches of IC design. Ans, Two approaches of IC design are given below ~ ( Botom-up Approach ~ The designer begins at the transistor OF. and designs subcireuits o complexity, which are then es on each water is technology after Practical Consideration & Technology in VLSI Design 5 ener repeatedly decomposes the Into groups and subgroups of simpler tasks. The eme ‘on, th standard \e required ms and ofien can be used ant increase in designer producti Give a brief discussion about the size and complexity of integrated (RGPS:, Dec. 2015) or € and complexity of integrated circuits (RGPS, June 2016) Discuss abou the siz Or Give a classification of integrated circuits by device count. (RGPN:, Dec. 2016) Or Write and explain the classification of integrated circuits by deve (RGPY, devices or potent number of agtive devices. Table 1.1 shows circuit by device count. i¢ classification of integrated Table 141 Name of Circuit | Active Device Count Functions ssl 110 10? Gates, op-amps, many linear MSI = 10? to 103 ters, ete, Lsl = 10° to 108 Microprocessors, A/D, ete VLSI - 105 to 10° Memones, computers, Processors, Rased on feature size, clas feature size or pit otherwords, pitel feature size was 7 nmcro to 10 micro in early 1970 and 5 micro were popular in lite 1970 and early 1980. In the end 1980s the minimum feature size had shrunk to. mum feature size. The mu under 2 1, with some groups producing | ys and i circus. A shetch of FET js shown in fig. 1.1 for references purposes.ryil-Sem) Practical Consideration & Technology m VLSI Design 7 5 mst Design With attractive ‘ith altractive temperature charac {s hard (0 get with the standarg cesses are capable. This strate processes, Micro Active Substrate . Nps tipo moster bur r—+— Max patos estos | ri ra, ess. Mi in the maximum practical chip size. jes field. HOS are the types of MOS, Process. pechannel and ic devices of MOS MO ie short note on microelectt ean, The term NOS ts yu sonable perfor On sastatigings i AMOS proses -tercectrnie fed plays avidin WLS (RGRN, Dec, 2015) the help of a suitable exaple. ms known asC ’ fers the designer si extra Fe 4 an PMOS or NMOS process. For F ion on microelectronics field. Give its classification — sed Appian clue ct taroseto (RGR 3. asic lowe fa Or ctions and & host of 1es of major proceses (R.GRY., May 2019) shes in the and processes have found nict Tield of microelectronics is very broad jon is shown in fig, 1.2. Explain the microelectronics field. Give the 9p used in IC fabrication. types of approach market place. The « Pecent trends in VLSI Design. How VLSI design will be economical ? Give the major costs associated with wafer processing and fabrication, (RGPN,, Dec. 2016) A identifi In the production of VLSI citcui iable. The continual shrinking of the mi is the most visible. Therefore, the rate at Inpocess types reduces is slowing, this trend Active substrates te more de this slowing is partially attrib gradually rising costs related wi inert substrates. M processes which : very fine equipment of resolution processing ze inert substrates are very important. Make good resistonRhonges from company to 4 Technology in VES! Design 9 company and from project to project. Due to differing project requirements Cost tes of the 5 - Per Wafer [Per bie and device count on di is important for establi 2 complexity sign. For ICs, this Information about design costs within a company is proprietary. The jon costs of IC are ler {0 projected. Major sociated with wafer des toward raised productivity of designer and an evg is toward ern te desi process. Inseeral cu -“echniques which were standard a ten year ago woul design projects, | ss bbe completely unworkable. i ‘A filth trend represents the contint iven in table 1.2. Typi x7 t re eneohcallyTsted:# sven inal 12-Tyil vega alo oe ‘nostand innovative desi Tablets peter Processing Cove wereasing shift in the design eff W Proce : jes has taken place Water fbricaton = 5" Process : c mn shifling mor lank wafer a costs rem ature producto e yalateprecessing J =Stan IZ 1 Eastern countries fafer probe (per water) | 275150 produced far Eastern countries. a ; x probe (per water) | 27 S14 i wh sith trend represents increasing coupling of @ spe ne roc Water sawing (per water) ee ¥5=540 processing equipment The process is becoming increasingly dependent Diestach and Res = c pieces of equipmet : onding (per wafer) = sc epecific performance pieces of equipment. in x5=83 o ‘ther trends comprise the employ of more powerful CAD tools. Packaging SiS keomy PE38 | of the systems designer. inal test per package) | xi Csppicon) | See below) } 1 from both scientific and engineerin Facer Lise sien? developmental and research efforts may, Plastic DIP focused toward regions i ments may be recoupled in the mark DIP Spin sae na relatively short time. Hence, it is important that the designer lastic DIP 16 pin 0048 the IC production economics. The developmental costs Plastic DIP 0.091 with the IC p Pl oininate on a product which is anticipated to have a relatively small” Ceramic side brazed 070 | inate on a product witha | mated sales volume over the life product life. x f “The developmental costs are projected once the engineering effort needed a product into produe ion is known. svelopmental costs cal product into produc ion is known, The developmen uy Ceramic CERDIP become quite lage for seeming simple designs. The burden is quite large dat} to several expenses such as computer time charges, t ian support, docs | ‘mentation preparation, applications engineering, equipment amortization, pil production, test procedure development and mask generation, The burden factot Ceramic pin grid array Ceramic pin grid array Ceramic pin grid aray Ceramic pin grid arrayvas esign (ViESem) ° wrap te tock dagran of convenonal IC diy ‘Draw and ¢: (R.GPN June 2016, May 2019) sus he book gram of conventional C design prose 1B shows the Be ing pont. Amajor efforts necessa : cations on complicated design models of devices or tr more accurate models may be used to vei he mesign, Good device and cell (subciruit) mod ely. predicts experimental performance a tion, a model is sufficiently e ;mulation using mucl ‘The actual layout occurs, once the design is deemed acceptable. commonly entered prior to the completion of preliminary design phase. A good floorplan can be achieved early in the desigo after a good estimate of the overall architecture and cells size can tbe achieved. The floorplan contains all cells placement and major busing (output pad inary information as well as input designations ‘Afier layout and ulti ‘mulation is undertaken on ions are essential because cffects related with the layout analog corcuits and digi circuits, the parasites normally caus additional unwanted delays or potent astrous race conditions whereas Production j Fig, 1.3 Conventional IC Desist Process effects of the parasities cannot be Practical Consideration & commonly necessitate changes ines eh yout _ Pr sate a pany re microprocessor requires ananea fence chip can be fabricated on a 5 inch wasey » "N*M Sol. Neglecting the area loss e (on the periphery ofthe wafer, the number of ‘op-amps and microproce are *oprocessors can be determined No = 2QSin? noe = 1963.495 = 1963 a ns. and . Nyp= = 126 i m process windows determi hye te pe Ilan dese, Ni emi eh a et @ Caos i S D=10 Wii) C= 15 Gin) Cp= 20. Sok (i) C,=05 (RGRN:, Dec. 2016) The design specification window is given by Lp, et oe ON 2 ee fH Tg hae tas = Fee ~sc0 ‘Therefore, the probability th the probability that al the design specification window is ee Proo» = (0.8664) =5.229« 10 0 P= have a parameter within (iG = The design specitication window is given by 1 le [ea osm Techn Technology in Visi Design 14an, -gh 9 = (0.999993)! = 0.993 and 99.3% yield. WC, = 2.0 . on - ee = 0,999999998 Pe peso Pago = (0999999998)! = 0.999998 = 1.0 and 2 100% yield This representing essent NG STEPS, \CTION PROCESS, PROCESSING STEPS, — Ic PRODUS PACKAGING AND TESTING ral (0.10. Write the major steps involved in producing ICs point of view. o rite down all the steps of IC production process. (R-GPV, Dec. 2015 ICs from qualitative poin Major steps involved in prod view are given below — Crystal preparation (ii) Masking i) Photolithographic process (iv) Deposition Diffusion Etching Conductors and resistors (ix) Epitaxy. Q.11, What do you mean by erystal preparation ? Or Write down all the steps of erystal preparation of bipolar substrate, : (RGRY, June 2018) [A single crystal of silicon which is lightly doped with either p off s is known as substrate of bipolar and MOS ICs. These crystals ular cylinders of crystalline silicon that are grOW® ‘upto 2 mand that lies in diameter from | to several inches. The thickness: Practical Co nserat 7 g slices are 250 1 to 4a ”& Technology in VLSI Design 13 H. The size o rs has been growing rapidly 4 larger number mn of chin Sms nes bat anew ne Q.12. What is meant by maskin, Aus. Integrated cit pene? oxpositives, During the phox from striking a photosen covered with a thin emulsion masks ae k To produce the real electron beam suse in thd method as this method but it needs more time and expensing 0.13. Discuss the photolthographie process, Or Explain the photolithographic process with masking used (GRY, June 2016) mask, ion implantation might not occur or the dielectric ot mete be Jeft intact. In areas where the mask is absent, the imy or dielectric or metal could be etched away. The Process called photolithography, from the Greck pi thos (stone) | | and graph (picture), which literally means ‘carving pictures in stone wing light’. The primary method for defining areas where we want matcal tobe | present or absent on a wafer is by the use of photo j With the photoresist and subjected to selective illum Photomask. After the i such as polycrystalline silicon, Physical masks on the chip.ey 44. vesi Design (vil-Sem™) ee vu mean by deposition ? sses films of different is known as evapor ire and pressure 0! temperatu - is formed. 1 is obtained in two ways ~ Je gas, which also frees the ‘Chemical vapour deposit {By pyrolytic decomposition of asin! desired molecules for reattachment i) Bycausinga reaction of tvo gases near te substral, a reaction gots that creates ‘that subsequently adhere to the substrat surface. Q.15. What is meant by etching ? “hn. Selectively dismissing unnecessary material from the surface ofthe subsite is known as etching. Masks and photoresist are used to selective patter the surface of the substrate. Wet and dry types of etches use generation. ‘also known as chemical etches. Dry etching, also le to the with emphasis 0 (R.GPY., Dec. 2017) Ans. Diffusionis the process of introducing controlled amounts of dopant Using diffusion, conductivity of silicon is being altered type and require that diffusion to be cari and by placing the dopant atoms on the surface of the semiconductor. So we haveahugh\ ion of the dopant atthe surface and it gradually decreases WF to that used i nert gas th growth rat MOSFETs. These polysilicon mater st i PT net hte eslin is mostly used for gates of mated app extremely significant. Source Metal | Feseeeme cere ye saben Se Ss Fig. 1.4 An NMOS Transistor Sho ure oxygen. Temperatures are in the region of 120°C;16 VLSI Design (Vil-Semm,) ject is shown in fig, 1.4 for an n-chal id oxide) projects above and below the ing terms ~ (ii) Lithography (iv) Epitaxy. 0.19. Explain the follo (i) Oxidation jit) Lon-implantation a ae (R.GRN, Dec. 2013). Refer to the ans. of Q.18. is the process of transferring pattems layer of radial : of the semiconductor substrate. The ave to be fabricated, bonding pads ete.| Ans, () Oxidation Gi) Lithography — Lithography Jometric shapes on a mask to a called resist covering the whole surface pattems define the regions of th This includes the implantation r 1g layers where the device is. After ns of the (0 the under are also transferred is done to remove unmasked po transferring the pattern layers. (iii) Jon-implantation ~ Ion-implantation is the process of | substrate, The dopant introdvetion of high energy charged particles into the atoms are vaporized, accelerated and targeted at the substrate, The atoms“ tmter the erystal lattice, collide with the substrate atoms, lose energy and h the dopant atoms penetrate depend on their speed. Typically the ion energies lie between 30 and 300 KeV and iow 6 jons/em?. lon-implantation is mainly used when. small areas are to be doped at lower temperatures. ‘A beam of ions, having desired charge to mass ratio are accelerated by ‘a voltage and permitted to impinge on the silicon wafer. The surface of the wafer is selectively coated with a beam resist such that the beam energy is ps ice only in the selected regions. The ighly directional and little lateral penetration occurs only at the is and which is very low: The dopant dose can be controlled by dg cans upon and taxis means ordered. Thus growth of thin ordered crystalline layer on a crystalline substrate is called epitaxy. During epitaxy the substra ¢ seed crystal and the crystal can be grown below used to enhance the performance of bipolar transistor and other CMOS ICs also. 10, What do you mean by i" a Packasng and rite short note On VLSI testing testin package W! -at away fro Ine die. Processed wafers ate sliced ino dice (chips) and packaged. Fig. 15 shows a Ls FF x1. mmehip in a40 pin duat-nline package ie bonded package uses thin packages offer different tradcof’s between cvs power handling, and reliability Flip-chip tech Uireoly onto the die, eliminating thebond wieeindoee over the entire chip area rather than just tte port Even tiny defects in a wafer or dust particles oar, Chips are tested before being sold. Testers capable of handle chips cost millions of dollars, so many chip uve bution reduce the tester time required itm self test features to an i 21. Explain IC production processandwhatarthe methodsofteting bo (R.GPN., June 2 Ans, Refer to the ans. of Q.10 t0 Q.20, ace 0.22, What is the weed of tesabiliy in a VLSI design ? Define ds for pi (RGBK, Dec. 2014) __Ans. Testability ~ Developed chips are eventually inserted ino printed circuit boards or multichip modules for system uses. The correct functionality of the system hinges upon the correct fu ofthe chip used. Thus, the fabricated chips must be completely testable o ensue thet all the chips passing the specified chip test may be inserted into the system without causing failures, either in packaged or in bare die form Such a aim requires ~ : = (Generation of good test vectors. Availability of reliable test fixture at speed Design of testable chip. __ Design for Testability ~ As the number of transistors integrated ito 2 single chip raises, the task of chip testing to ensure correct functionality becornes increasingly more complex. Thus, many chips must be tested within a short18 VLSI Design (Vil-Sem) ery to consumers ina production environment. Design for 1 to overcome such difficult issues, hare testable are the two concep, ed known as controllability and observabiliy, the ability to set (10 1) and reset (to 0) every node internal ty the circuit, Observabil to observe either directly or indiregy, the state of any node in the circuit “Three main techniques are used for design for testa Practical Consideration & Technology in VLSI Design 19 shown in fig. 1.7, is a non-conducting condition with Vp = Vs = Vps = 0. Ifthe nected to a postive volage with respect ta the sour, the el field is established between the gate and the substrate, which induces region in the substrate under the gate insulation and a conduction path or rmed between source and drain. Souree CHP Drain Ny Mey y. These are given (i) Ad-hoc testable design techniques EES Po ) Scan based techniques i aa role i) Self-test and built-in techniques. tte MOS PROCESSES, NMOS PROCESS, CMOS PROCES: BIPOLAR TECHNOLOGY, HYBRID TECHNOLOGY, DESIC RULES AND PROCESS PARAMETERS 7 (a) NMOS Enhancement Mode Transistor Source Gate Drain LAN TT sonductor devices wh CMOS process. Particularly, the jun 1 is used primarily in digital circuits asa protection device in I/O structures and the latter can be constructed to improve the speed of CMOS in BICMOS processes. However, of concer he parasitic bipolar transistors constructed as a basic NMOS/PMOS structures in CMOS, which (6) NMOS Depletion Mode Transistor Fig. 17 In depletion mode device, the channel is present under the condition Vx, = 0 by implanting suitable impurities in the region between source and drain during manufacture and prior to depositing the insulation and the gate. In this, source and drain are connected by a conducting channel, but the channel may be closed by applying a suitable negative voltage to the gate. : 0.24, Sketch the schematic symbol for n-channel and bechamel depletion MOSFET and enhancement MOSFET. What is the significant difference between the construction of an enhancement type MOSFET and depletion type MOSFET ? a tns. Commonly used +t a “F 4 4 + erence between enhanee- AMOS NMOS POS. ment type MOSFET and Fatincement Depletion Enhancement pe MOSFET as Fig. 1.6. MOS Transistor Circuit ly cut-ol zero gate bias are called enhancement mode devices, whereasp-Channel Eahancemeat p-Channel Depletion Fig. 1.8 Conduction Characteristics for Enhancement and Depletion “Mode MOS Transistors (Assuming Fixed Vis.) (0.28, Briefly seuss the physical structure af PMOS transsto, | Ans. Physical structure of PMOS transistor is shown in fig. 1.9. A even of maype and p-type regions of NMOS yields a p-channel MOS transistor.” Gace nesubstrate Drain O=N ay (Usually Vpp) 1.9 Physical Structure of PMOS Transistor When a negative gate voltage is applied (with respect to source), it draws w the gate, resulting in the channel changing fromn- conduction path between the source and the drain is instance, conduction results due to the movement of we channel. A negative dre ge sweeps holes from the source through the channel to the drain, _ YG. Explain the physical structure and operation of an NMOS hancement transistor, Or __ Explain the operation of n-channel enhancement MOSFET with different values of gate voltage. (R.GPV., Dec. 2013) — Or Explain about the NMOS process in details. Or Write short note on NMOS process. (R.GRY, June 2018) (R.GRY,, Dec. 2015, 2016) Practical Consideration & Technology n VLSI Design 24 Or Explain the operating principle of n-channel MOSFET with the help of suitable regional diagrams. (RGPN, May 2019) shows the physical structure of an NMOS enhancement ts ofa moderately doped p-type silicon substrate into which two doped n* regions, the source and drain, are diffused. narrow region of p-type substrate exists between these two regions, which is g layer of n electrode over this oxide layer, which is referred to as gate. Gate Onsite Le Source prowbatrate Sonstate (useally og) Fig, 1.10 Physical Structure of an NMOS Enhancement Transistor ‘The D.C. current from the gate to channel is essentially zero, because the oxide layer is an insulator. There is no physical distincton between the drain and source regions due to the inherent symmetry of the structure. The application of high gate fields is possible because SiO, has relatively low loss and high dielectric strength In operation, a positive gate voltage is given between the source and the drain (Vg,). When gate bias 1s zero (ie., Ves= 0). current does not flow from source to drain since they are effectively insulated from each other by the two reversed biased pn-junctions illustrated in fig. 1.10. But, whena voltage, which is positive with respect to the source and the substrate, is applied to the gate then it generates an clectrc field E across the substrate which attracts electrons toward the gate and repels holes. In case when gate voltage is sufficiently large, the region under the gate alters from p-type to n-type and gives a conduction path between the source and the drain, Under such a condition, the surface of the underlying p-type silicon is called inverted. Fig. 1.11 shows the intial distribution of mobile positive holes n a p-type silicon substrate of an MOS structure for a voltage, Vi» much less than 2 es voltage, Vj, that is the threshold voltage, This mode is referred to asCE ISSSSSSSSS Beegseee9 QOHOOHOLO (@) Depletion ce voltage, Ves is equal to is given bet drain is the responsi i associated with the drain-to-source vollage Practical Consideration & Technology in VLSI Design 23 channel starts to change the shape of the chan ‘The full gate voltage is effective in inv the channel tween the gate and drain voltages is eff ive. Drain I Nonsaturated Mode) saturated or unsaturated re} gate and drait and Vien Va, is greater hed-olf, = Vga < ager reaches the drait In such a ease, conduction is brou; fon under the effect of the posi24 VLSI Design (Vil-Sem,) Practical Consideration & Technology in VLSI Design 25 3s, the hole mobility is approximately 500 ce, the (othe drain depletion region and are subsequently result, the vollage across the pinched-of the 1 current tance of an equi e operating conditions. a-channel pel obtain the same resistance. Hence, n-channel MOS cn the same complexity as compared to p-channel devices. case wl ‘affect the level of drai gre more advantageous than p-channel circuits. However, the more extensive process control required for n-channel fabrication makes them expensive and ly with p-channel devices at this time. ¢ to compete economic: In the ease of an MOS be categorized as (i) Cutoff Region — tn this region, the current flow is essentially 0.29, Describe the two Npesof MOS transistors used in CMOS technology: Ans. In the CMOS technology. two types of transistors are used — an n- type transistor (1-MOS) and a p-type transistor (p-MOS). Fabrication of these ors is done in electrons (nega! in holes. When fabri ure includes distinct layers called diffusion, polysilicon and separated by insulating layer, zero, which the drain current is depe (ii) Saturated Region= of the drain h voltages are applied to the drain, an abnor gate has no control over the dra nche breakdown, conduction. current. Conductor Insulator 0.27. Discuss the operation of n-channel MOSFET in depletion and inversion region. (RGR, June 2016) ‘Ans, Reler to the ans. of Q.26, 0.28. Write advantage of NMOS over PMOS devices. sement FET is very popular in MOS systems spared to the n-channel device, In are positively Subttrate Sehematic Leon Ans, The p-channel enl and substrate, In an n= Gate ive with respect to the 4 ‘charged contaminants collect along the interface te Source ange from this layer | Subnrate tends to make the transistor s, the positive contaminant ions are o the aluminium-SiO interface) Schematic eon .13 Architecture of MOS Transistors and their Schematic Iconsures for the two types of MOS transistors, ion of p-type silicon (called the substrata) 1. This structure is formed by using ted areas in the po’ ‘common w ections, designated the source and s ed regions, Gate is a control input, which affeety thé stncal current between the source and the drain. Actually. the drathaygd source ‘een as two switched terminals, which are interchangeable. 20. Draw and explain ideal I-V characteristics of MOS transistor. Or Draw the transfer characteristics of MOSFET and derive the expression Ans. Fi ‘The depletion a ms, corresponding to V., nes jufacturer sometimes indicates is reduced to some speci- gate-source cut-off voltage Vp, negligible value ata recommended V4, tage Vp of a JFET, \ pinch-off ¥ pobre tt a ey Nesolt Fig, LI Transfer Characteristic of an n-channel MOSFET that can be Used Either in the Enhancement Mode or in the Depletion Mode ion of the Expression for Drain Current — Let us consider a lage Vx, which 1s applied between gate and source with V., > V, to induce channel In adion, we assume that a voltage Va, is applied between drain And source. Fist we consider operation inthe triode region, for which the channel must be ‘ous and hence Vpg must be greater than V, of Practical Consideration & Technology in VLSI Design 27 ave the tapered In such a case, the channel Kor of Value i 7 ° o Fig. 1.15 Derivation of the I4,~V,, Characteristic of the NMOS Transistor We know that in the MOSFET, the gate and the channel region form a paral jor for which the oxide layer acts as a dielectric. If the capacitance per unit gate area is represented by Cg, and the thickness of the oxide layer is toy then we obtain, Com HE ‘ where, ox = Permittivity of tl fog = 3.9 fy = 3.9 * 8.854 « 10°12 = 3.45 « 10-11 Fm, Oxide thickness t,, is obtained by the process technology used to fabricate the MOSFET. Now, refer to fig. 1.15 and consider the infinitesimal strip of the gate at distance x from the source. Capacitance of this strip is C.,Wdx. ‘To determine the charge stored on this infinitesimal strip ofthe gate capacitance, ‘we multiply the capacitance by the effective voltage between the gate and the channel at point x, where the effective voltage is the voltage which is responsible for inducing the channel at point x and is hence [V,,~ V(x) — Vj] where V(x) is the voltage in the channel at point x. It follows that the electron charge dq in the infinitesimal part of the channel at point x is obtained as 4g = ~ Coy (Wd) [Vox = VOX) - Vid i) where the leading negative sign indicates that dq is a negative charge.1 s- WW Vis 5 Vas This is the ex30. VLSI Design (Vil-Sem) sal Consideration & Technology in VLSI Design 31 to open windows Im through the photoresist mask Etching of the alumi st. Fig. 1.17 (e) shows the etching ff the remaining photon ‘Thermal treatment for firing of aluminium into silicon, of an npn bipolar emitter current, psi the structure and Vi character can be constructed by building a0 np 1.18 (a). Likewise, a pnp transistor cat between the inals of a bipolar transistor are known as collector, base and emit the behaviour of the transistor can be modeled by Coder Second photomasking ope iffusions. ‘Second diffusion to provide isolating p layers and isolated s | he dffsan boro "| ing operation to open windows in the oxide | @ w Fig. 1.18 Structure and Model of an npn Bipolar Transistor By using the Ebers-Moll model, the collector current can be given as ~ grow n* layers, using the diffusan is sometimes of the two stage type too, {siv) Total deposition of aluminium film onto the wafer a shown in| : : 4Practcal Consizeraten & Tectnclogy in VLSIDeSa0 33 the invener shown in sor R,, Base s connected is expressed as ~ Vg. = Input voltage = Base emitter voltage (~| expressed a 1. = Bly ‘Thus. the collector voltage is given as — Gain A is expressed as WVeu _ BRe Var ORS “Ann-well CMOS process inherently has « pnp transistor wbich is generated von the substrate (collector). well (bate). and source drain diffusions This pnp transistor is not that use: al except for application as a e. Since the transistor is form:d by the vertical stacking of junctions. this transistors averical pap, To construct more useful npn transistors, extra processing steps must a JOS processes. These Oro steps result in whatis termed BiCMOS process (for bipolar and CMOS). 0 the case of p-and n-channel tors in CMOS, npn lar tran transistors have much higher gain and V better frequency as compared to pnp Fig. 1.20 Inverter Using NPN transistors. Hence, BICMOS processes Transistor adding a high-performance npa transistor. concentrate (55. What do you mean by hybrid technology ? Describe the thick film and thin film circuits. (R.GPV., Dec. 2013) Or Write short note on hybrid technolo Ans, The combination of two or mo: wo or more integrated cus Ce few discrete components in soni C4863, th a single package To form what is called a hybrid integrated circuit. Monolithic structures are cheaper than hybrid (R.GBY., May 2019, Nox: 2019) Fig. 1.18 shows the V/ characteristics of a ical npn t : basic design equations for use with di saa ney tans34 VLSI Design (Vil-Sem.) Practical Consideration & Technology in VLSI Design 35 the features of thick film HICs. IC has following features ~ ensure sufficiently n and hybrid ICs are divided i.e. cannot produce technology of manufactu fone mechanically, that ick film technology is simpler, so the thick fi ible and are cheaper, 5. Write down the features of The various features ‘The capaci integrated circuits. ‘The deposition of film over one micrometre in thickness, requires since the rate of deposition of thin film is very less. Also, the Ims over I or 2 um thick is easily peeled off. A ow rate of film growth permits easy control of film thickness, yrances on the values of resistors and capacitors. lows — ry layer of paste should be ’igh precision values are formed insulating re differences beoveen the bipolar technology and (R.GRY, Dec. 2015, June 2017) Or ed to make this eleme ye same time as the tra and hence grown to same depth as base. Class of bipolar mate doping of a semiconductor substrate with donar and acceptor imput the body of the substrate. ‘An IC with some discrete elements or a jon of two or more IC types is known as hybrid IC. In hybrid ICs various layers deposited on an insulating substrate of size of few square centimet 037. What do you understand by layout design rules ? Explai function, Ans Layout rules are also known as design considered as a prescription for preparing th of integrated circuits) The rules provide an es circuit designer and process engineer du Objective associated with layout rules in small area as poss out compromising reliability ofthe circuit les. These rules can be asks used inthe fabrication 1! communication link between \e manufacturing phase. The main(vison) Practical Consideration & Technology in VLSI Design 37 © he next process dow. iy uses the actual micron-design rules and codes desien in hese dimensions, or uses symbolic layout systems to target the exactly. ‘Table 1.4 CMOS Layout Rules 2p Rule Layer a. Rute] (0.5y) | w Rule ‘Minimum size Tox | Sn 2h Minimum spacing a ‘wells at same potential) oo | 3p he wings are placed 10 ease Tone another, (wells at same po Take place betwWeen two ‘Minimum spacing aay Belweet twa Tadependent (wells at different potentials) | 8% | 4 2h logy of a process. mer Minimum size 3h isa] iw by the mask-making a Miniroum spacing 3h tse | om S aDiTis ine Newell overlap of p* sa | 25 | tn Newell overlap of n* 3h 130 | tie Newell space to n* se | 25 | Su inimam feature sizes Newell space to p* 3h tn | 3H en process, The lambda-based nd Conway are based ona single parame! n of Ey rm te 2 ip ‘| Spacing to Active nm o3n | Ose Gate Extension 2 im u ‘plus/n-plus (p*, n* for short) mn Ip Wie brief the ta i ‘a trivial nD Su ue refs the layout design rules followed in fabrication of IS devices, (R.GPY., June 2017) CS Expl , ic Dm osu | 2m lain the various CMOS design rules. (RGN, June 2015) D.4] Spacing of p" ‘sel rules are described based on the MOSIS CMOS n*ip* gate 3A ts _[_15n € rules for a hypothetical (but-.. Practical Consideration & Technology in VLSI Design 39 3g. USI Design (Vil-Sem,) each mask needed in a process one requires to know whether itis £,_Contact 2 a Ja!" or “dark field”, whether light will pass through the mask to expose D shographic pattern or whether light will be blocked by the mask. 2 Teepe Furthermore, biases are added or subtracted from the drawn dimensions of 2n One the mask allow for varying types of processing. Contacts might be shrunk 1h MSIE as etching tends to make them larger during processing, The rules in table 1.4 n strated in fig. 1.23 (and in Plate 2, ist 3h 1S £2 | Minimum spacing 3a 15a G Via GI | Minimum size Bre in G2 | Minimum spacing 3h Isp G3 | Minimum Metaltoverlap 2 05 G4 | Minimum Metal2 overlap 1 osn_| = [Metal “5 111 [Minimum size 3h 15h 112 | Minimum spacing a en 1 Via TT [Minimum size 2h rm 2 | Minimum spacing 3h 15p J. Metal 3 €.Copy 1 Res JL] Minimum size 8h 4u an J.2 | Minirowm spacing oh 2su | 25p J.3 | Minimum Metal 2 overlap 2a In In | bee J.8 | Minimum Metal3 overlap m in I wen Minimum opening Toon | 10a mele Layer D.ptint Rates ntand ptimay be um spacing ison | 150m fae (ee eee ed in terms of ~ overlaps. rules stated above, there are various spacing rules f «chip which frequently depend on the vendor (e.g., spacit © boundary is 20-50). Tent Epo? Teer40 VLSI Design the need of design rules ? Di CMOS IC des ifferent wpes of desis Dec. 2017, Nov. 2015 rules, (RG Ans. Refer to the ans. of Q.37 and Q.38, Q.40. Describe the various rules and process parameters of VLSI. (R.GPY., Dec. 201: Ans, Refer to the ans. of Q.37 and Q.38. some reasons for the design rules (design rule backgroun usually a deeper implant comp: iplants, therefore it is necessary for rension to provide sufficient clearance between the n-well ed djacent n* diffusions. 7 ‘The inside clearance is determined by the transition of the field oxi across the well boundary. Some processes that use STI may permit inside clearance, but problems such as the *birds-beak’ effect usually Practical Consideration & Technology in VLSI Design 41 (6) Fig. 1.24 Effects of Insufficient Gate Extension and Source-drain ExtensionPractical Consideration & Technology in VLSI Design 43 ther the substrate of the n= modem processes, ly require uniform contact sizes to achieve well-defined etching Mee ‘pp Merged contacts may be inset source of the corresponding n-transistor where wide transistors are wed. Here the n? well contact is separated from the p* source/dcain whereas an nedevice has an n° reg not covered by n are p* and hence are p-devices or Therefore a transistor is n-ch p-channel device. (ii) Comact Rules ~ There are several generally av (p-diffusion) o th cemplo} diffusion ings that are p* diffusions in the Guard Rings ~ Guard iffusions in the n-well are used to col p-subste id to Vop» While p* guard rings must be tied to V,s. A p* diffusion with n* ‘guard ring is shown in fig. 1.26 (a), while an n° diffusion with p* guard ring is shown in fig. 1.26 (b). Different well-enclosure rules may apply for guard-ring structures, The n in fig. 1.26 (a) is also that for a pap transistor if one was polysilicon and the active transistor region. Som allowed to only one type of active area. 4 ns, each isolated well the navell must be region is the area of the emitter. The base is the n-well and is connected via the nt ring. The collector is substrate. must have access (0 two separ SSS = @ O) Fig. 1.26 Guard () Metal Rules — Metal spacings may vary with th eased, This is due to ital wires. There may also be maximut there may be rules that are applied to long closely spaced para Mask Fig. 1.25 Structure of a Merged ar Abu Substrate Comact44 WLS! Oasign (virSem) ould he clmumced dari: coma opeoings imine: thene perches cuit ae every ow due tz unig tre thar womlt render 3 coeae openangs wert alowed tar» be pon 4. and d, > 12A, The layout itself also edges of the metal and ment) it can be argued by design rule 5.6 that 2A, From design rules 5.4 and 5.7, the poly and metal ce there is um spacing between the left-hand edge ofthe poly in the tub can be coincident with the _| the guard ring may be broken). It thus follows that, dy> 5% a3 ich from above becomes d= 392 = 29.25 p. Practical Consideration & Technology in VLSI Design §3 -k film resistor layout strategy is shor ibstrate age of Sabtrate ‘Sol. Since R = 325 kQ and since the goal is to minimize area, the highest be used for the resistors. We obtain fe n = 325 KOUR,, = 32.5 squares of resistive material. Since there tre five equal width resistances in series, each of width W, the length of each (4,) must equal 32.5W/5 = 6.5 W. follows that the length and height of the substrate are L= 2d + 24, + 2d, + 5W H= 24, + 24, + 4, ‘The following minimum sizes are obtained for each ofthe parameters d = dy, and W- +4, Rule T 12 22 1s 4.0 23) 13a 136 24 2 Parameter It should be noted that even though these are minimum spacings, the layout itself may impose more stringent requirements to av void layout violatior| 54 VLSI Design (Vil-Sem.) Specifically, dy > dy + 2dyy = 42 dy > dy + dy, = 22 d) > 5h. We thus obtain — L= (2)(2X) + (2)(42) + 2(2A) + (5)(52) +(4)(4n) = smh H= (2)(2A) +(2)(2A) + (65)(54) = 40.52 With A = 250 y, the minimum substrate size is = 1.425 em x 1.0125 em