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Design and Simulation of 4-Bit Johnson Ccounter Using Verilog.

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Amarjyoti samal
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103 views

Design and Simulation of 4-Bit Johnson Ccounter Using Verilog.

Uploaded by

Amarjyoti samal
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Laboratory Report

On
Design and simulation of 4-bit
johnson counter using verilog HDL
(D&LiC Lab)

Submitted By:
Ojaswi Agrawal (22053440)
Himashu Kumar (22053429)
Abhijeet Sinha (22053479)
Akash Aman (22053483)
Amarjyoti Samal (22053484)

B.Tech Programme in Computer Science Engineering


School of Electronics Engineering
Kalinga Institute of Industrial Technology,Deemed to be University
Bhubaneswar,India
OBJECTIVE:

Design and Simulation of 4 bit Ring counter and 4 bit Johnson counter using Verilog
HDL.
Hardware implementation of 4 bit Ring counter and 4 bit Johnson counter.

THEORY:

Johnson Counter:
A Johnson counter is a type of shift register that is similar to a ring counter, but with
an additional invert stage. It is sometimes also called a "twisted ring counter" counter".
The operation of a Johnson counter is similar to that of a ring counter, with each flip
flop output changing state on each clock pulse. However, in a Johnson counter, the
output of the last flip-flop is inverted and fed back into the first flip-flop. This causes
the counter to cycle through a sequence of states that includes both ascending and
descending binary values.

Figure 7.13: Logic diagram of Johnson Counter

Assume, initial status of the D flip-flops from leftmost to rightmost is Q1 Q2 Q3 Q4 =


“0000” .This status repeats for every Eight (8) clock pulse which is shown in below
Table 7.7.
A “mod-2n” ring counter will require “n” number of flip-flops connected together to
circulate a single data bit providing “2n” different output states.Each state repeats after
every “2n” clock pulse.
The design and simulation of a 4-bit Johnson counter using Verilog constitutes a significant aspect of
digital circuit theory and implementation. A Johnson counter, also known as a twisted-ring counter, is a
type of shift register with a feedback mechanism, creating a circular pattern in its output. In a 4-bit Johnson
counter, there are eight states, and it cycles through all of them, providing a unique sequence of binary
values.

The theoretical foundation for this project involves understanding the principles of sequential logic circuits,
particularly shift registers and feedback loops. Verilog, a hardware description language (HDL), serves as a
crucial tool for modeling and simulating digital systems. The language allows for the abstraction of
complex digital circuits into modular and hierarchical structures, making it suitable for describing the
behavior of the 4-bit Johnson counter at various levels of abstraction.

In the context of the 4-bit Johnson counter, the design involves specifying the flip-flops, the feedback
connections, and the sequential logic necessary to achieve the counter's cyclic behavior. Verilog modules
can be defined for each component, fostering modularity and reusability. Simulation tools such as
ModelSim or VCS can be employed to validate the correctness and functionality of the designed counter
before actual implementation.

Additionally, the thesis can delve into the optimization of the design, considering factors like speed, power
consumption, and area utilization. This may involve tweaking parameters such as clock frequency or
exploring different architectures to achieve a balance between performance and resource utilization.
Understanding the trade-offs and implications of these design choices contributes to the depth of the thesis.
Furthermore, the thesis could explore applications of the 4-bit Johnson counter in practical scenarios, such
as signal generation, frequency division, or pattern recognition.
REQUIREMENTS:

LOGIC DIAGRAM:

DESIGN CODE:
module johnson_counter( out,reset,clk);

input clk,reset;

output [3:0] out;

reg [3:0] q;

always @(posedge clk)

begin

if(reset)

q=4'd0;

else
begin

q[3]<=q[2];

q[2]<=q[1];

q[1]<=q[0];

q[0]<=(~q[3]);

end

end

assign out=q;

endmodule
TESTBENCH CODE:
module test_jcounter();
reg clk,reset;
wire [3:0] out;

johnson_counter dut (.out(out), .reset(reset), .clk(clk));

always
#5 clk =~clk;

initial begin
reset=1'b1; clk=1'b0;
#20 reset= 1'b0;
end

initial
begin
$monitor( $time, " clk=%b, out= %b, reset=%b", clk,out,reset);
#105 $stop;
end
endmodule
OBSERVATIONS/RESULTS

A) RTL Schematic
B) Output Waveform

DISCUSSION OF RESULTS:

As we performed the experiment using hardware implementation and software


simulation,we found that the results obtained from the truth table by hardware
implementation matches and is also duly verified with the schematic waveform
obtained from software simulation using Vivado 2016.1.

CONCLUSION:
Thus,Design and simulation of 4-bit johnson ccounter using verilog HDL was
implementated using hardware and software simulation using vivado 2016.1 and
the truth table was verified along with it.
STUDENT SIGNATURES:

1)

2)

3)

4)

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