04-09-2023

Computer Organization and Architecture

Basic Operational Concepts

Veena Thenkanidiyoor
National Institute of Technology Goa

Recap
• Hierarchical nature of a computer
• Structure of a computer
• Function of a computer
• Internal of a single processor system
• Contemporary computers with multiple processors
• History of computers
• Computer organization- computer architecture
• Computer types
• Layered view of a computer system
• Computer as a multilevel machine
• Microarchitecture level
• Course content
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Functional Units
• Input Unit
• Memory Unit
• Arithmetic and Logic Unit (ALU)
• Output Unit
• Control Unit

I/O Processor

Input Output Memory ALU Control

3
Data path or bus

Information Processed by Computer

• Instructions:
– Instructions are commands that
• Govern the transfer of information with in computer as well as between the computer
and its I/O devices
• Specify the arithmetic and logic operations to be performed
– A set of instructions that perform a task is called program
– Usually a program is stored in memory
– Processor fetches the instructions that make up the program from memory, one
after another, perform desired operation
• Data:
– They are numbers or encoded characters that are used as operands by the
instructions
• Information handled by a computer is encoded in a suitable format (string of
binary digits called bits – 0/1)
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Basic Operational Concepts

• High-level program segment
scanf(“%d, %d”, a,b);
c=a+b;
printf(“&d”, c);

• Assembly level program segment

IN PORTA, LOCA - Read operand from input port and store into a memory
location, LOCA
IN PORTA, LOCB
LOAD LOCA, R0 - Load the content from LOCA to processor register R0
ADDM LOCB, R0 - Add the operand at memory location LOCB to the
operand in processor register R0 and places the
result in R0
STORE R0, LOCC - Store the result in R0 to memory location LOCC
OUT PORTB

Basic Operational Concepts

• High-level program segment Memory
scanf(“%d, %d”, a,b); LOC 0
c=a+b;
printf(“&d”, c); LOC 101 IN PORTA, LOCA
LOC 102 IN PORTA, LOCB
LOC 103 LOAD LOCA, R0
• Assembly level program segment
LOC 104 ADDM LOCB, R0
IN PORTA, LOCA - Read operand from input port and store into a memory LOC 105 STORE R0, LOCC
location, LOCA
LOC 106 OUT PORTB
IN PORTA, LOCB
LOAD LOCA, R0 - Load the content from LOCA to processor register R0
ADDM LOCB, R0 - Add the operand at memory location LOCB to the LOCA
operand in processor register R0 and places the
LOCB
result in R0
LOCC
STORE R0, LOCC - Store the result in R0 to memory location LOCC
OUT PORTB
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Execution of an Instruction
• Execution of an instruction requires to perform several steps
– Instruction is fetched from memory into processor
– If the instruction include operands, then the operands are fetched
– If an instruction is for arithmetic operation, perform that operation on the
fetched operands and store the results in destination location

• Transfers between memory and processor are started by sending the

address of the memory location to be accessed to memory unit and
issuing the appropriate control signals

Operational Details

Memory

MAR MDR
Control
PC R0 Unit
R1
IR

ALU

Rn-1

Processor n general purpose

registers 8
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Registers in Processor
• General purpose registers
– Hold the operands or address of the operand
– Typically 16 to 32
• IR (Instruction Register)
– Holds the instruction currently being executed
• PC (Program Counter)
– Holds the memory address of the next instruction to be fetched and execured
• MAR (Memory Address Register)
– Holds the address of the memory location to be accessed
• MDR (Memory Data Register)
– Holds the data to be written into or read out of the addressed location

Execution of an Instruction, IN
PC LOC 101
Memory
IR IN PORTA, LOCA LOC 0
MAR LOC 101

MDR IN PORTA, LOCA

LOC 101 IN PORTA, LOCA • Fetch
R0 LOC 102 IN PORTA, LOCB
R1 LOC 103 LOAD LOCA, R0
n general LOC 104 ADDM LOCB, R0
purpose
LOC 105 STORE R0, LOCC
registers
LOC 106 OUT PORTB
Rn-1

Control Read LOCA

Unit
LOCB
Processor LOCC

ALU
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Execution of an Instruction, IN
PC LOC 101
Memory
IR IN PORTA, LOCA LOC 0
MAR LOCA

MDR 5 • Decode
LOC 101 IN PORTA, LOCA
R0 LOC 102 IN PORTA, LOCB
R1 • Execution
LOC 103 LOAD LOCA, R0
n general LOC 104 ADDM LOCB, R0
purpose
LOC 105 STORE R0, LOCC
registers
LOC 106 OUT PORTB
Rn-1

Control Write LOCA

Unit
LOCB
Processor LOCC

ALU
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Execution of an Instruction, IN
PC LOC 102
Memory
IR IN PORTA, LOCA LOC 0
MAR LOCA

MDR 5 • Decode
LOC 101 IN PORTA, LOCA
R0 LOC 102 IN PORTA, LOCB
R1 • Execution
LOC 103 LOAD LOCA, R0
n general LOC 104 ADDM LOCB, R0
purpose
LOC 105 STORE R0, LOCC
registers
LOC 106 OUT PORTB
Rn-1

Control Write LOCA 05

Unit
LOCB
Processor LOCC

ALU
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Execution of an Instruction, IN
PC LOC 103
Memory
IR IN PORTA, LOCB LOC 0
MAR LOCB

MDR 4 • Decode
LOC 101 IN PORTA, LOCA
R0 LOC 102 IN PORTA, LOCB
R1 • Execution
LOC 103 LOAD LOCA, R0
n general LOC 104 ADDM LOCB, R0
purpose
LOC 105 STORE R0, LOCC
registers
LOC 106 OUT PORTB
Rn-1

Control Write LOCA 05

Unit
LOCB 04
Processor LOCC

ALU
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Execution of an Instruction, LOAD

PC LOC 103
Memory
IR LOAD LOCA, R0 LOC 0
MAR LOC 103

MDR LOAD LOCA, R0 • Fetch

LOC 101 IN PORTA, LOCA
R0 LOC 102 IN PORTA, LOCB
R1 • Decode
LOC 103 LOAD LOCA, R0
n general LOC 104 ADDM LOCB, R0
purpose • Execution
LOC 105 STORE R0, LOCC
registers
LOC 106 OUT PORTB
Rn-1

Control Read LOCA 05

Unit
LOCB 04
Processor LOCC

ALU
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Execution of an Instruction, LOAD

PC LOC 104
Memory
IR LOAD LOCA, R0 LOC 0
MAR LOCA

MDR 05 • Fetch
LOC 101 IN PORTA, LOCA
R0 LOC 102 IN PORTA, LOCB
R1 • Decode
LOC 103 LOAD LOCA, R0
n general LOC 104 ADDM LOCB, R0
purpose • Execution
LOC 105 STORE R0, LOCC
registers
LOC 106 OUT PORTB
Rn-1

Control Read LOCA 05

Unit
LOCB 04
Processor LOCC

ALU
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Execution of an Instruction, LOAD

PC LOC 104
Memory
IR LOAD LOCA, R0 LOC 0
MAR LOCA

MDR 05 • Fetch
LOC 101 IN PORTA, LOCA
R0 05 LOC 102 IN PORTA, LOCB
R1 • Decode
LOC 103 LOAD LOCA, R0
n general LOC 104 ADDM LOCB, R0
purpose • Execution
LOC 105 STORE R0, LOCC
registers
LOC 106 OUT PORTB
Rn-1

Control MDR_OUT
R0_IN LOCA 05
Unit
LOCB 04
Processor LOCC

ALU
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Fetching and execution of an Instruction, ADDM

PC LOC 105
104
Memory
IR ADDM LOCB, R0 LOC 0
MAR LOC 104

MDR ADDM LOCB, R0

LOC 101 IN PORTA, LOCA
R0 05 LOC 102 IN PORTA, LOCB
R1 LOC 103 LOAD LOCA, R0
n general LOC 104 ADDM LOCB, R0
purpose
LOC 105 STORE R0, LOCC
registers
LOC 106 OUT PORTB
Rn-1

Control Read LOCA 05

Unit
LOCB 04
Processor LOCC

ALU
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Fetching and execution of an Instruction, ADDM

PC LOC 105
Memory
IR ADDM LOCB, R0 LOC 0
MAR LOCB

MDR 04
LOC 101 IN PORTA, LOCA
R0 05
09 LOC 102 IN PORTA, LOCB
R1 LOC 103 LOAD LOCA, R0
n general LOC 104 ADDM LOCB, R0
purpose
LOC 105 STORE R0, LOCC
registers
LOC 106 OUT PORTB
Rn-1

Control Read
Add LOCA 05
Unit
LOCB 04
Processor LOCC

ALU 05 +04 = 09
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To Summarize

• Functional units

• Basic operational concepts

– Execution of an instruction
– Important processor registers

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Functional Units
• Suitable connection between the functional units
• Functional units handle one full word of information
– All the bits in a word are transferred in parallel over
many wires, lines
– One bit per line
• Bus: group of lines that serve as a connecting path
I/O Processor

Input Output Memory ALU Control

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Data path or bus
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Bus Structures

• Single bus-All units are connected to this bus

• Only one transfer at a time
• Only two units can use at a time

I/O Processor

Input Output Memory ALU Control

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Data path or bus

Bus Structures
• Devices connected to a bus vary widely in speed of operation
– Keyboards and printers are relatively slow
 Electromechanical devices
– Memory and processor are faster
 Operate at electronics speed

 Communicate with each other over a bus

- May get constrained by the slow devices

 Buffer registers
- Every device to hold the information during transfers
- Transfer of a character from processor to a printer
- Transferred over a bus to the printer buffer
- Printer can print without further intervention of the bus and the processor
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System Software
• For executing an application program, some system software must
already be in memory and executing
• Program that reads numbers stored in a file on disk, sorts the
number in ascending order and displays the sorted list on the screen
- Write a program in high level language using some text editor
- Save the program onto disk in a file
- Translate the program written in high level language into machine language
program
- Linking a user written program with the standard library which the program is
using
- Running the program
- Receiving and interpreting the commands issued for translation, execution etc
- Managing the disk storage to support the file reading operation
- Coordinating the I/O units
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System Software
• Responsible for the coordination of all activities in a computing
system
• Program that reads numbers stored in a file on disk, sorts the
number in ascending order and displays the sorted list on the screen
- Text editor
- Command prompt – Operating system
- Compiler
- Linker and loader
- Operating system
- …..
• Operating system
– Large program, collection of routines
– Control the sharing and interaction of various computer units
– Assigning resources to individual application programs 24
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Performance of a Processor
• How quickly programs can be executed

• Good performance
- Hardware
- Machine instruction set
- Compiler

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Performance of a Processor
• Elapsed time
- Total time required to execute a program
- Measure of entire computer system
- Affected by the speed of the processor, disk and peripherals like
printers
• Processor time
- Performance of the processor
- Periods during which the processor is active
- Depends on the hardware involved in the execution of individual
machine instruction
 Processor and memory

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Processor Clock
• Timing signal that controls the processor circuit
• Periodic signal
- Regular time intervals- clock cycles
• Execution of an instruction
- Divide into a sequence of basic steps
- Each basic step can be completed in one clock cycle
• Length of one clock cycle: P
- Clock rate 𝑅 = ⁄ cycles per second
- Hertz (Hz), Mega (M) Hz-Million, Giga (G) Hz-Billion
 500 million cycles per second-500 MHz
o 2 nanoseconds (ns)
 1250 million cycles per second—1.25 GHz
o 0.8 ns
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Basic Performance Equation

• T: The processor time required to execute a program that has been
prepared in high level language
• N: Actual number of machine language instructions required to
execute a program written in high level language

High level language Machine language

scanf(“%d, %d”, a,b); IN PORTA, LOCA
c=a+b; IN PORTA, LOCB
printf(“&d”, c); LOAD LOCA, R0
ADDM LOCB, R0
STORE R0, LOCC
OUT PORTB
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Basic Performance Equation

• N: Actual number of machine language instructions required to
execute a program written in high level language
Machine language
High level language
SUB R0, R0, R0; R0 has value of loop index i
LEA R1, A; Load the effective address of A in R1
FOR ( i = 0; i < N; i++)
LEA R2, B
A[i] = B[i] + C[i];
LEA R3, C
LOAD R4, N
Loop_Begin: CMP R0, R4
JEQ Loop_End
LOAD R5, [R2][R0]
LOAD R6, [R3][R0]
ADD R7, R5, R6
STORE [R1][R0], R7
INC R0
JMP Loop_Begin
Loop_End: 29

Basic Performance Equation

• T: The processor time required to execute a program that has been
prepared in high level language
• N: Actual number of machine language instructions required to
execute a program written in high level language
- Loop-instructions get executed multiple times
- Condition execution-some instructions may not get executed
• S: Average number of basic steps needed to execute one machine
instruction
- Each basic step is completed in one clock cycle
• 𝑅: Clock rate
• Program execution time
𝑁x𝑆
𝑇=
𝑅 30
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High Performance
𝑁x𝑆
𝑇=
𝑅
• Reduce the value of T
- Reduce N and S
- Increase R
• Reduction in N – complexity of instruction increases
- S increases
• Increasing R-using higher frequency clock
– Time to complete a basic execution step reduces
• N,S, and R are not independent parameters
– Changing one may affect the other
• Attempt to improve performance only by overall reduction of T
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Further Performance Improvement?

• Instructions are executed one after another
• S is the total number of basic steps (clock cycles) required to execute
an instruction
Instruction 1 IF ID OF EX WB

Instruction 2 IF ID OF EX WB

Instruction 3 IF ID OF EX WB

Instruction N-1 IF ID OF EX WB

Instruction N IF ID OF EX WB 32
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Overlapping the Execution of Successive Instructions

Clock cycle

1 2 3 4 5 6 7 8 9 10 11 12 13 14
I1 IF ID OF EX WB

I2 IF ID OF EX WB

I3 IF ID OF EX WB

I4 IF ID OF EX WB
Instruction
I5 IF ID OF EX WB

I6 IF ID OF EX WB

I7 IF ID OF EX WB

I8 IF ID OF EX WB

I9 IF ID OF EX WB

I10 IF ID OF EX WB

• One instruction completed in every clock cycle from 5th clock cycle
onwards
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• For the purpose of computing T, the effective value of S is 1

Instruction Pipelining
Clock cycle

1 2 3 4 5 6 7 8 9 10 11 12 13 14
I1 IF ID OF EX WB

I2 IF ID OF EX WB

I3 IF ID OF EX WB

I4 IF ID OF EX WB
Instruction
I5 IF ID OF EX WB

I6 IF ID OF EX WB

I7 IF ID OF EX WB

I8 IF ID OF EX WB

I9 IF ID OF EX WB

I10 IF ID OF EX WB

• One instruction completed in every clock cycle from 5th clock cycle
onwards
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• For the purpose of computing T, the effective value of S is 1
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Superscalar Execution
• Multiple instruction pipelines
– Multiple functional units

• Execution of several instructions per clock cycle

• Effective value of S can be reduced to less than one

• Many of today’s high performance processors are designed

in this manner

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Performance of a Processor
• Good performance
- Compiler
- Machine instruction set
- Hardware

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Increasing Clock Rate R

• Improving the integrated-circuit (IC) technology makes logic

circuits faster
– Time needed to complete a basic step reduces
– Clock period P reduces and clock rate R increases

• Reducing the amount of processing done in one basic step

– Reduce the clock period P
– Number of basic steps needed may increase S

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Instruction Set: Simple Vs Complex Instructions

• Simple instructions
– Require a small number of basic steps
– A large number of instructions may be needed to perform a given
programming task
– Large value of N and small value of S

• Complex instructions
– Require a large number of steps
– Individual instructions perform complex operations
– Fewer instructions will be needed
– Lower value of N and a larger value of S

• Design of an instruction set of a computer? 38

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Instruction Set: Simple Vs Complex Instructions

• Support for pipelining

– Easier in processors with simple instruction set

• Complex Instruction Set Computer (CISC)

• Reduced Instruction Set Computer (RISC)

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Compiler
• Translates a high-level language program into a sequence of
machine instructions

• To reduce N, suitable machine instruction set a compiler that

makes use of it

• An optimizing compiler takes advantage of various features of

the target processor to reduce NxS

• A compiler is not a separate entity from the processor with which it

is used
– Should be closely linked to the processor architecture
– Compiler and processor are designed together
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Performance of a Processor
• Affected by
– Hardware
– Machine language instructions-instruction set
– Compiler

• For best performance, it is necessary to design the compiler, the

machine instruction set, and he hardware in a coordinated way

• Performance of a processor is the execution time, T, for the

program of interest

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Performance Measurement
• Performance equation
– Conceptual simplicity
– Not easy to measure
• Measuring computer performance using benchmark programs
– Benchmark: Standardised program
• Performance measure: Time it takes to execute a given benchmark
• Use a selection of real application programs to evaluate performance
– System Performance Evaluation Corporation (SPEC) selects and
publishes representative application programs for different application
domains
 Range from game playing, compiler and database applications to numerically
intensive programs in astrophysics and quantum chemistry

• The same program is also run one computer selected as a reference

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Performance Measurement
• SPEC rating for a benchmark is given by

𝑅𝑢𝑛𝑛𝑖𝑛𝑔 𝑡𝑖𝑚𝑒 𝑜𝑛 𝑡ℎ𝑒 𝑟𝑒𝑓𝑒𝑟𝑒𝑛𝑐𝑒 𝑐𝑜𝑚𝑝𝑢𝑡𝑒𝑟

𝑆𝑃𝐸𝐶 𝑟𝑎𝑡𝑖𝑛𝑔 =
𝑅𝑢𝑛𝑛𝑖𝑛𝑔 𝑡𝑖𝑚𝑒 𝑢𝑛𝑑𝑒𝑟 𝑐𝑜𝑚𝑝𝑢𝑡𝑒𝑟 𝑢𝑛𝑑𝑒𝑟 𝑡𝑒𝑠𝑡

• The overall SPEC rating for the computer is given by

𝑆𝑃𝐸𝐶 𝑟𝑎𝑡𝑖𝑛𝑔 = 𝑆𝑃𝐸𝐶

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To Summarize
• Bus structure

• System software

• Performance of a processor
– Basic performance equation
– Factors affecting the performance

• Improving the performance

– Pipelining
– Superscalar processing

• Performance measurement
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Thank You

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