210245: Digital Electronics and

Logic Design

Unit VI

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 Introduction to Computer
Architecture
 Introduction to Ideal Microprocessor

 Data Bus

 Address Bus

 Control Bus

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 Introduction to Ideal Microprocessor

 Basics of Microprocessor
 Fairchild Semiconductor(1957)
 Founder of
Intel(Robert,Gordan,Andrew)
 3 man start up 1968 to industrial gaint
by 1981.

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1970s Processors

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1980s Processors

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Block Diagram of µp :

I/O Data Bus

Device
Control Control
Bus Bus
Memory
I/O Ports CPU RAM &
ROM

O/P Address Bus

Device

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• The microprocessor or CPU reads each
instruction from the memory, decodes it and
executes it.
• It processes the data as required in the
instructions. The processing is in the form of
arithmetic and logical operations.
• The data is retrieved from memory or taken
from an input device and the result of
processing is stored in the memory or
delivered to an appropriate output device, all
as per the instructions.

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 Buses

●There are a number of possible

interconnection systems
●Single and multiple BUS structures
are most common
●e.g. Control/Address/Data bus (PC)
●e.g. Unibus (DEC-PDP)

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 What is a Bus?
● A communication pathway connecting two or
more devices
● Usually broadcast
● Often grouped
● A number of channels in one bus
● e.g. 32 bit data bus is 32 separate single bit
channels
● Power lines may not be shown

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 Data Bus:
• Data lines that provide a path for moving
data among system modules
• May consist of 32, 64, 128, or more
separate lines
• The number of lines determines how
many bits of data can be transferred at a
time.

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 Address Bus
 If the processor wishes to read a
word of data from memory it puts
the address of the desired word on
the address lines.
• Used to address I/O ports.

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 Control Bus
• Used to control the access and the use of the
data and address lines.

• Data and Address lines are shared by all

components there must be a means of
controlling their use.

• Control signals transmit both command and

timing information among system modules
• Timing signals indicate the validity of data and
address information
• Command signals specify operations to be
performed
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Microprocessor based
Systems – Basic Operation :

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Hardware and Software
Approaches

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 Major components:
• CPU
• Instruction interpreter
• Module of general-purpose arithmetic and logic
functions
• I/O Components
• Input module
• Contains basic components for accepting data
and instructions and converting them into an
internal form of signals usable by the system
• Output module
• Means of reporting results
• Memory
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 Processor Components
• ALU- Arithmetic Logic Unit
• Registers
• Control Unit

ALU
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Control Unit

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 Cont…
● The Control Unit and the Arithmetic and Logic
Unit constitute the Central Processing Unit
● Data and instructions need to get into the
system and results out
● Input/output
● Temporary storage of code and results is
needed
● Main memory

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 Microprocessor based Systems
 Instruction Cycle
● Two steps:
● Fetch
● Execute

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Fetch Cycle
● Program Counter (PC) holds address of next
instruction to fetch
● Processor fetches instruction from memory
location pointed to by PC
● Increment PC
● Unless told otherwise
● Instruction loaded into Instruction Register
(IR)
● Processor interprets instruction and performs
required actions

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Execute Cycle
● Processor-memory
● data transfer between CPU and main memory
● Processor I/O
● Data transfer between CPU and I/O module
● Data processing
● Some arithmetic or logical operation on data
● Control
● Alteration of sequence of operations
● e.g. jump
● Combination of above

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Block Diagram of Microprocessor

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 Internal architecture of 8086
 8086 has two blocks BIU and EU. (Independent)
 The BIU handles all transactions of data and
addresses on the buses for EU.
 The BIU performs all bus operations such as
instruction fetching, reading and writing
operands for memory and calculating the
addresses of the memory operands. The
instruction bytes are transferred to the
instruction queue.
 It is also called as external world interface of
processor
 EU executes instructions from the instruction
system byte queue.

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 Both units operate asynchronously
to give the 8086 an overlapping
instruction fetch and execution
mechanism which is called as
Pipelining. This results in efÏcient
use of the system bus and system
performance.
 BIU contains Instruction queue,
Segment registers, Instruction
pointer, Address adder.
 EU contains Control circuitry,
Instruction decoder, ALU, Pointer
and Index register, Flag register.
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 EXECUTION UNIT

 Decodes instructions fetched by the BIU

 Generate control signals,
 Executes instructions.
 EU is called execution heart of the processor

The main parts are:

 Control Circuitry
 Instruction decoder
 ALU

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EXECUTION
EXECUTION UNIT
UNIT –– General
General Purpose
Purpose Registers
Registers
16 bits

8 bits 8 bits

AH AL
AX Accumulator

BH BL Base
BX
CH CL Count
CX

DX DH DL
Data
SP Stack Pointer
Pointe
BP Base Pointer
r
SI
Source Index
Index
DI Destination
Index
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 Registers

4 bit Register
Register as data storage
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 Pointer And Index Registers
 used to keep offset addresses.
 Used in various forms of memory addressing.
 In the case of SP and BP the default reference to form a
physical address is the Stack Segment (SS-will be
discussed under the BIU)
 The index registers (SI & DI) and the BX generally default
to the Data segment register (DS).
SP: Stack pointer
– Used with SS to access the stack segment
BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments

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 SI: Source Index register
– is required for some string operations
– When string operations are performed, the SI
register points to memory locations in the data
segment which is addressed by the DS register. Thus,
SI is associated with the DS in string operations.

 DI: Destination Index register

– is also required for some string operations.
– When string operations are performed, the DI
register points to memory locations in the data
segment which is addressed by the ES register. Thus,
DI is associated with the ES in string operations.

 The SI and the DI registers may also be used to access

data stored in arrays
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 EXECUTION UNIT – Flag
Register
 A flag is a flip flop which indicates some
conditions produced by the execution of an
instruction or controls certain operations of the
EU .
 In 8086 The EU contains
 a 16 bit flag register
9 of the 16 are active flags and remaining 7
are undefined.
 6 flags indicates some conditions- status flags
3 flags –control Flags

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 EXECUTION UNIT – Flag Register

Flag Purpose
Carry (CF) Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated by some
programs and procedures .
Parity (PF) PF=0;odd parity, PF=1;even parity.

Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
(for example, in BCD addition or subtraction.)
Zero (ZF) Shows the result of the arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is 0
Sign (SF) Holds the sign of the result after an arithmetic/logic
instruction
execution. S=1; negative, S=0
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 Flag Purpose
A control flag.
Trap (TF) Enables the trapping through an on-chip debugging
feature.
A control flag.
Interrupt (IF) Controls the operation of the INTR (interrupt request)
I=0; INTR pin disabled. I=1; INTR pin enabled.
A control flag.
Direction (DF) It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions.
Overflow occurs when signed numbers are added or
Overflow (OF) subtracted. An overflow indicates the result has exceeded
the capacity of the Machine

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 BUS INTERFACE UNIT (BIU)
Contains
 6-byte Instruction Queue (Q)
 The Segment Registers (CS, DS, ES, SS).
 The Instruction Pointer (IP).
 The Address Summing block (Σ)

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 Functional Units of Microprocessor –

Does the calculations

Everything else in the computer is there to service this unit
Handles integers
May handle floating point (real) numbers
May be separate FPU (maths co-processor)
May be on chip separate FPU (486DX +)

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 ALU using IC 74181

 74LS181 4-Bit Arithmetic Logic Unit

 4-bit Arithmetic Logic
 16 logic operations
 Provides 16 arithmetic operations
 Provides all 16 logic operations of two
variables
 Full lookahead for high speed
arithmetic operation on long words

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Cont..

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 Cont..

 M=High=Logical operation
 M=Low=Arithmetic operation

 Device can be use with either active

low inputs producing active low output

 Active HIGH inputs producing Active

High

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4-bit Multiplier circuit using ALU and
shift registers.

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 Complex
 Work out partial product for each digit
 Take care with place value (column)
 Add partial products

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 Memory Organization

 Memory Hierarchy
 Memory is used for storing programs and data that are
required to perform a specific task.
 For CPU to operate at its maximum speed, it required an
uninterrupted and high speed access to these memories that
contain programs and data. Some of the criteria need to
be taken into consideration while deciding which
memory is to be used:
 • Cost
 • Speed
 • Memory access time
 • Data transfer rate
 • Reliability
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 A computer system contains various types of memories
like auxiliary memory, cache memory, and main memory.

 Auxiliary Memory

 Main Memory

 Cache Memory
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 Main Memory

 Central storage unit in a computer

system
 Large memory
 Made up of Integrated chips
Types:

 RAM (Random access memory)

 ROM (Read only memory)
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 Cont..

 RAM (Random Access Memory)

 Random access memory (RAM) is the best
known form of computer memory. RAM is
considered "random access" because you can
access any memory cell directly if you know
the row and column that intersect at that cell.
 Types of RAM:-
 •Static RAM (SRAM)
 •Dynamic RAM (DRAM)
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 Static RAM (SRAM)

 a bit of data is stored using the state of

a flip-flop.
 Retains value indefinitely, as long as it
is kept powered.
 Mostly uses to create cache memory of
CPU.
 Faster and more expensive than DRAM.
 •
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 Dynamic RAM (DRAM)

 Each cell stores bit with a capacitor

and transistor.
 Large storage capacity
 Needs to be refreshed frequently.
 Used to create main memory.
 Slower and cheaper than SRAM.

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 RAM and ROM Chips

 A RAM chip is better suited for

communication with the CPU if it has one
or more control inputs that select the chip
when needed
 •The Block diagram of a RAM chip is
shown next slide, the capacity of the
memory is 128 words of 8 bits (one byte)
per word
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RAM

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ROM

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 Memory Address Map

 Memory Address Map is a pictorial

representation of assigned address space for
each chip in the system
 To demonstrate an example, assume that a
computer system needs 512 bytes of RAM and
512 bytes of ROM
 •he RAM have 128 byte and need seven
address lines, where the ROM have 512 bytes
and need 9 address lines
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 The hexadecimal address assigns a
range of hexadecimal equivalent
address for each chip
 Line 8 and 9 represent four distinct
binary combination to specify which
RAM we chose
 When line 10 is 0, CPU selects a RAM.
And when it’s 1, it selects the ROM
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Cache memory

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Digital circuit using decoder and registers for memory operations

 Fig shows the diagram of a 8x8 bit

memeory.
 For storing 8 bytes ,it uses 8 registers

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Digital circuit using decoder and registers for memory
operations

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 For performing read /write operation on
aspecific memory location
 3:8 decoder used selecting one of the
eight memory location from 000 to
111.
 Uses address lines

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 Applications

 Industrial Controller
 Computer Peripheral
 Instruments
 Household
 Medical
 Database Management
 Electrical Power

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