2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM)

Approximate Brent Kung Adder For Image

2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM) | 979-8-3503-7118-5/23/$31.00 ©2023 IEEE | DOI: 10.1109/iTechSECOM59882.2023.10435122

Processing Applications
Tummala Prudhvi Dantla Sudhakar Reddy Musala Sarada
Department of ECE Department of ECE Department of ECE
Vignan's Foundation for Science Vignan's Foundation for Science Vignan's Foundation for Science
Technology and Research Technology and Research Technology and Research
Vadlamudi, Andhra Pradesh, India Vadlamudi, Andhra Pradesh, India Vadlamudi, Andhra Pradesh, India
[email protected] [email protected] [email protected]

Kanapala Satish
Department of ECE
Vignan's Foundation for Science
Technology and Research
Vadlamudi, Andhra Pradesh, India
[email protected]

Abstract—An approximate parallel prefix adder is a type of computation results, which are nearly accurate, are
circuit that can perform addition operations on binary evaluated as approximate, thus confirming their suitability
numbers with extremely high speed, low latency, and much less for practical use in Image Processing Applications
power. Nowadays, thinking about fuzzy computing, that is, [5],[6],[7].
sacrificing computational expectations for computational
efforts, has emerged as a promising graphical approach. Over
the past decade, various research works have explored II. EXACT AND EXISTING APPROXIMATE
approximate computation at both the software level and the
BRENTKUNG ADDER
hardware abstraction level, with encouraging results. At the
stage of hardware abstraction, adders (which are the most A. Exact Brent Kung Adder
widely used and mandatory information operators in digital
systems) have generated great interest in the approximation The parallel arithmetic operations performed by the
used in digital systems used in image processing applications. Brent-Kung adder are implemented using a tree structure.
The approximate Brent-Kung adder (AxBK) is a variant of the Richard Peirce Brent and Hsiang Te Kung first proposed it
simple Brent-Kung adder that introduces a degree of in 1982[8]. This is a great choice for low-power designs as it
approximation into its operation. A new approximate BK is designed to reduce chip space and facilitate
adder is proposed with high-speed overall performance and manufacturing. The gray and black cells make up the Brent-
low error cost. Its BK adder and AxBK adder are restricted to Kung adder, with each black cell having two AND gates and
bits 8,16,32 using software called Xilinx Vivado and MATLAB. one OR gate. Compared to other adder topologies, it has
greater regularity, which reduces cable clutter and improves
performance. Figure 1 shows the structure of the 16-bit
Keywords—Brent-Kung (BK), Approximate Parallel Prefix Brent Kung adder [9]. Calculating the carry from the least
Adder (AxPPA), Approximate Brent-Kung (AxBK) significant bit adder (LSB) to the most significant bit adder
(MSB) determines the critical route in the BK adder, which
is why one tries to shorten the critical path so that the
storage unit can reach the MSB [10],[11],[12].
I. INTRODUCTION
In Approximate vlsi, parallel prefix adders [1],[2] are
significantly used in processing chips to add two large
binary values to perform the addition operation. Mainly, the
requirements of this type of adder are to minimize area,
improve speed, and reduce error rate. In this article, we
present BK and its AxBK adder. The total output can be
generated using an XOR operation between the P spread and
the previous Ci-1 gain for an 8.16-bit AxBK adder.To
address the challenges in the Exact BK adder area,
improvements were made to enhance efficiency and reduce
delay [3],[4]. The introduction of the existing AxBK adder
aimed to achieve these objectives by minimizing the area,
decreasing delay, and improving error rates. However, to
further optimize the delay and error rate, the Proposed
AxBK Adder was developed. This innovative solution aims Fig.1 Exact 16-Bit Brent Kung Adder Structure
to deliver superior results at the output by reducing delay
even further while maintaining a minimal error rate. The

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 2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM)

B. Existing Approximate Brent Kung Adder In Which i=0 to 7

Ci= (C7& Pi+1) + Gi+1 -------(6)

In Which i=8 to 15

S0=P0 -----------------------------------(7)
Si=Pi+1 ^ Ci-1 ----------------------(8)
In Which i=1 to 16

Fig.2 Block Diagram of Existing Approximate Brent Kung Adder

The AxBK adder which is shown in Figure 2 [13],[14] is

composed of a set of prefix computing steps. It is a 16-bit
adder has the propagate[P] and generate [G] with prefix
computing operation. The 16 bits may be divided into two
parts: the first 8 bits are used for the AxBK adder operation
(shown in Figure 3), and the last 8 bits are used for the
precise BK adder (shown in Figure 4), which performs the
output sum using the XOR operation [15],[16],[17].

Fig. 4 Exact Block (8-Bit MSB) of Approximate 16-bit Brent Kung Adder
Structure

TABLE I. AN EXAMPLE FOR ADDITION, OPERATIONAL STAGES

OF THE EXACT AND EXISTINGAPPROXIMATE KOGGE STONE
ADDER

Example
Decimal
Input Binary bits
value
A 0101101011000011 23235 --------------
B 1110100011111001 59641
Sum 10100001110111100 82876 Exact Addition
Sum 10100001110111000 82872 ApproximateAddition
Sum 10100001110111010 82874 Proposed AxAddition
Process

Fig. 3 Approximate Block (8-Bit LSB) of Existing Approximate 16-Bit Exact Addition Approximate Addition
Brent Kung Adder Structure
Generate Generate[G]
Stages Propagate[P] bits Propagate[P]bits
[G] bits bits
0 10110010 01001000 00111010 11000001
The operational formulation for the AxBK adder is given 1 0100 1010 ------ ------
below [18],[19],[20]. 2 00 11 ------ ------
Pi= Ai ^ Bi ---------------------------(1)
3 0 1 ------ ------
Gi=Ai& Bi --------------------------(2) 4 0 1 ------ ------
In Which i=0 to 16 5 000 110 ------ ------
6 11111010 11000001
ipi=Pi+1& Pi+2 ----------------------(3)
igi= (Gi+1&Pi+2) + Gi+2 ------(4) Final
10100001110111000 82872
Result
In Which i=0 to 16

Ci=Gi -----------------------------------(5)

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 2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM)

III. PROPOSED APPROXIMATE BRENT KUNG ADDER and E8F9 input to all three adders, and the sum values of
Exact BK, AxBK, and Proposed AxBK Adders are
43BC,43B8, and 43BA respectively. The error rates for
existing and proposed AxBK are0,0.0843,0.0434. Table 2
gives the quantitative analysis of delay and area in terms of
LUTs of the existing and Proposed AxBK Adders of 8-bit,
16-bit, and 32-bit. From Table 2, it can be observed that the
proposed AxBK 32-bit adder takes less area and less delay.

Fig.5 Block Diagram of Proposed Approximate BK Adder

Proposed Approximate BK Adder which is proven

in Figure 5. In the area of the XOR gate Replaced with the
OR gate at the LSB facet for Approximate 8-bits from sum
S0 to S7 and ultimate 8-bits at MSB aspect are equal to
Fig.7Simulation Result of Exact BK 16-Bit Adder
actual BK adder which is proven in Figure 6 with this
operation the approximate price of sum is nearer to specific
fee with much less error charge and high-speed overall
performance with excellent effectivity and discount of place
the usage of FPGA implementation with hardware
connection to get the correct outcomes.

Fig.8Simulation Result of AxBK 16-Bit Adder

Fig. 9. Simulation Result of Proposed AxBK 16-Bit Adder

Fig.6. Approximate Block (8-Bit LSB) of Proposed Approximate 16-Bit
Brent Kung Adder Structure TABLE II. ANALYSIS OF AREA AND DELAY OFEXISTING AND
PROPOSED AXBK ADDER
The operational formulation for Proposed AxBK Adder is
Exact Proposed
given below. Exact
BK AxBK
AxBK Proposed
No. BK Adder
Adder AxBK
of Adder AxBKAdder
Ci = Gi--------------------------(9) Adder Delay Adder
bits Delay LUT
LUT (ns) LUT
Where i=0 to 7 (ns) Delay(ns)

8 1387 8.769 1388 7.861 1385 8.625

S0=P0 ------------------------(10)
Si=Pi+1 + Ci-1------------(11) 16 1460 9.583 1455 8.494 1453 8.629
Where i=1 to 7 32 1696 8.204 1652 7.314 1651 7.201

IV. SIMULATION AND OUTPUT RESULTS Output results of Exact BK, AxBK, and Proposed
AxBK Adders for 16,32 bits are shown in Figures
Simulation results of Exact BK, AxBK, and Fig.12,13,14, and Fig.15,16,17 respectively. From those
Proposed AxBK Adders for 16 bits are shown in Figures figures, we can observe that the two input images applied are
Fig.7, Fig.8, and Fig.9 respectively. From those figures, we shown in Fig.10 and Fig.11 input to all three adders, and the
can observe that the two input numbers applied are 5AC3 PSNR values of Exact BK, AxBK, and Proposed AxBK
Adders are calculated respectively in Table 3.

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 2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM)

Fig.14 Result Image of 16-bit Proposed AxBK Adder

Fig.10 Input Image1

Fig.15 Result Image of 32-bit Exact BK Adder

Fig.11 Input Image2

Fig.16 Result Image of 32-bit Existing AxBK Adder

Fig .12 Result Image of Exact 16-bit BK Adder

Fig.13 Result Image of 16-bit Existing AxBK Adder

Fig.17 Result Image of 32-bit propsed AxBK Adder

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 2023 International Conference on Intelligent Technologies for Sustainable Electric and Communications Systems (iTech SECOM)

[13] P. P. Potdukhe and V. D. Jaiswal, Design of High-Speed Carry Select

TABLE III. ANALYSIS OF PSNR FOR BK ADDER Adder Using Brent Kung Adder [doi:10.1109/ICEEOT.2016.7754762].
[14] N. Udaya Kumar and K. Bala, Sindhuri; K. Durga Teja; D. Sai Satish,
No of Exact BK AxBK Proposed AxBK Implementation and comparison of VLSI architectures of 16-bit carry
bits Adder Adder Adder select adder using Brent Kung adder.
[15] K. Golda, Hepzibah; CP. SubhaA Novel Implementation of High-
8 46.459701 27.987721 27.908850 Speed Modified Brent Kung Carry Select Adder.
[16] G. G., S. S. Raju, and S. Suresh, "Parallel Prefix Speculative Han
16 62.230587 53.218859 53.217293 Carlson Adder," in IOSR Journal of Electronics and Communication.
[17] B. Koyada et al., "A comparative study on adders" in IEEE
32 190.974765 103.570406 103.570350 Conference on Wireless Communication, Signal Processing and
Networking, 2017 [doi:10.1109/WiSPNET.2017.8300155].
[18] B. Mohamad et al., "Template matching using the sum of squared
difference and normalized cross-correlation" in Proc. IEEE Student
Conference Res. Develop. (Scorned), Dec. 2015, pp. 100-104.
V. CONCLUSION
[19] M. M. A. da Rosa et al., "'Exploring efficient adder compressors for
In this paper proposed an approximate BK Adder the power-efficient sum of squared differences design,' in Proc.,"
for 8,16 bits. This Adder can be used to function the n bit Circuits Syst. (ICECS) 27th IEEE Int. Conf. Electron., Nov. 2020, pp.
1-4.
binary addition with excessive performance, location
[20] A. V. Gupta et al., Low-Power Digital Signal Processing Using
effectivity with much less prolong and error price is Approximate.
decreased at output. we evaluated our proposed
Approximate Brent Kung adder for much less error price
with changing of OR gate at LSB aspect to get sum output
for 8-bit S0 to S7 and closing function the equal operation
of Approximate BK adder. The range of good judgment
tiers used is moreover determined to be less. It is an
excessive velocity addition that can be completed for large
values with much less lengthen and higher outcomes at
output. This Proposed AxBK adder can used in future
purposes like photograph processing, ALU units, Fir
filters, digital signal processing, and so on widely used for
Future Applications.

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