24itu03 Digital Fundamentals and Architecture

CIA II-24ITU03- II Digital Fundamentals and Architecture
Department Name : Information Technology

Subject : Digital Fundamentals and Architecture(IT) Standard: Semester I -UG
Date & Time of Exam Max. Marks : 100.00
Section1
1. 1. ________ number systems has a base of 16?(1.00)
a) A. Decimal b) B. Binary
c) D. Octal d) C. Hexadecimal
2. The addition of these binary numbers 101001+ 010011 would generate ________(1.00)
a) A. 101110 b) C. 111100
c) B. 000111 d) D. 010100
3. The subtraction of these binary numbers 101001 – 010110 would generate________(1.00)
a) A. 010010 b) C. 100110
c) B. 011001 d) D. 010011
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4. The multiplication of these binary numbers 10100 * 01011 would generate________(1.00)
a) C. 011001100 b) A. 011100011
c) D. 011011000 d) B. 011011100
5. The radix of an octal number system is________(1.00)
a) A. 8 b) B. 2
c) C. 16 d) D. 10
6. ________format is used to store data(1.00)
a) A. Decimal b) B. Octal
c) D. Hexadecimal d) C. BCD
7. 8. Subtraction in computers is carried out by ________(1.00)
a) A. 1' s Copmplement b) B. 2' s Copmplement
c) D. All of these above d) C. 10' s Copmplement
8. In ________form the computer stores its data in memory(1.00)
a) A. Hexadecimal form b) B. Octal form
c) C. Binary form d) D. Decimal form

9. Which system groups number by sixteen and power of sixteen________(1.00)
a) A. Binary b) B. Hexadecimal
c) C. Octal d) D.None of these
10. Counting in hex, each digit can be increment from ____________:(1.00)
a) A. 0 to F b) B. 0 to G
c) D. 0 to J d) C. 0 to H
11. ________ number can be converted into binary numbers by converted each hexadecimal digit.(1.00)
a) A. Binary number b) B. Decimal number
c) C. Octal number d) D. Hexadecimal number
12. Binary numbers can also be expressed in this same notation by ____________(1.00)
a) A. Floating point b) B. Binary point
c) C. Decimal point d) D. All of these
13. Floating point representation of a number consists ________(1.00)
a) A. 4 b) B. 2
c) C. 3 d) D. 5

14. The first part of floating point represents a signed fixed point number called as ________(1.00)
a) A. Exponent b) D. Mantissa
c) B. Digit d) C. Number
15. The second part of floating point designates the position of the decimal point and is called as ___(1.00)
a) A. Mantissa b) D. Exponent
c) B. Binomial d) C. Octal
16. The exponent contains the decimal number ________(1.00)
a) A. 5 b) B. 3
c) C. 4 d) D. 7
17. ________ expression shows the commutative law of multiplication(1.00)
a) A. AB = B + A b) B. A + B = B + A
c) D. All of these d) C. AB = BA
18. ________ expression express the distributive law of Boolean algebra.(1.00)
a) A. A(B + C) = AB + AC b) B. (A + B) + C = A + (B + C)
c) C. A(BC) = (AB) + C d) D. None of these

19. The equation is C + CD is equal to ________(1.00)
a) A. C + D b) C. A
c) B. D d) D. None of these
20. In Boolean algebra, ________ is meant of this word “literal”(1.00)
a) A. the inverse function b) B. a product term
c) D. All of the above d) C. a variable or its complement
21. Two important fields of an instruction are Opcode and Operand (State True OR False)(1.00)
a) A. True b) B. False
22. Each operation has its Unique opcode(1.00)
23. And gate represents multiplication operation(1.00)

24. Not gate represents the complement of the input(1.00)
25. When both the inputs are low in the OR gate the output is High(1.00)
26. Example of the use of an S-R flip-flop is as ___________(1.00)
a) A. Transition pulse generator b) B. Racer
c) C. Switch debouncer d) D. Astable oscillator
27. The truth table for an S-R flip-flop has _________ VALID entries(1.00)
a) A. 1 b) B. 2
c) C. 3 d) D. 4
28. When both inputs of a J-K flip-flop cycle, the output will ___________(1.00)
a) A. Be invalid b) B. Change
c) C. Not change d) D. Toggle

29. ___________is correct for a gated D-type flip-flop(1.00)
a) A. The Q output is either SET or RESET as soon as the D input goes HIGH b) B. The output complement follows the input when enabled
c) C. Only one of the inputs can be HIGH at a time d) D. The output toggles if one of the inputs is held HIGH
The logic circuits whose outputs at any instant of time depends only on the present input but also on the past Outputs are Called_______(1.00)
30.
a) A. Combinational circuits b) B. Sequential circuits
c) C. Latches d) D. Flip-flops
31. Sequential circuits types are _______(1.00)
a) A. 2 b) B. 3
c) C. 4 d) D. 5
32. The sequential circuit is also called ___________(1.00)
a) A. Flip-flop b) B. Latch
c) C. Strobe d) D. Adder
33. In S-R flip-flop, if Q = 0 the output is said to be ___________(1.00)
a) A. Set b) B. Reset
c) C. Previous state d) D.Current state

34. Trigger pulse is a ______(1.00)
a) A. A pulse that starts a cycle of operation b) B. A pulse that reverses the cycle of operation
c) C. A pulse that prevents a cycle of operation d) D. A pulse that enhances a cycle of operation
35. 13. One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is _________(1.00)
a) A. The inputs of NOR latch are 0 but 1 for NAND latch b) B. The inputs of NOR latch are 1 but 0 for NAND latch
c) C. The output of NAND latch becomes set if S’=0 & R’=1 and vice d) D.The output of NOR latch is 1 but 0 for NAND latch
36. The difference between a flip-flop & latch is ____________(1.00)
a) A.Both are same b) B. Flip-flop consist of an extra output
c) C. Latches has one input but flip-flop has two d) D. Latch has two inputs but flip-flop has one
37. The S-R flip flop consist of ____________(1.00)
a) A. 4 AND gates b) B. Two additional AND gates
c) C. An additional clock input d) D. 3 AND gates
38. _______is a flip-flop said to be transparent?(1.00)
a) A. When the Q output is opposite the input b) B. When the Q output follows the input
c) C. When you can see through the IC packaging d) D. When the Q output is complementary of the input

39. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ____________(1.00)
a) A. The clock pulse is LOW b) B. The clock pulse is HIGH
c) C. The clock pulse transitions from LOW to HIGH d) D. The clock pulse transitions from HIGH to LOW
40. The asynchronous input can be used to set the flip-flop to the ____________(1.00)
a) 1 state b) 0 state
c) either 1 or 0 state d) forbidden State
41. Input clock of RS flip-flop is given to ____________(1.00)
a) A. Input b) B. Pulser
c) C. Output d) D. Master slave flip-flop
42. D flip-flop is a circuit having ____________(1.00)
a) 2 NAND gates b) 3 NAND gates
c) 4 NAND gates d) 5 NAND gates
43. Input or output devices that are connected to computer are called ______________.(1.00)
a) A. Input/Output Subsystem b) B. Peripheral Devices
c) C. Interfaces d) D. Interrupt

44. Keyboard and Mouse Comes under________(1.00)
a) A. Input peripherals b) B. Output peripherals
c) C. Input-Output peripherals d) D. None of the above
45. The method which offers higher speeds of I/O transfers is ___________(1.00)
a) Interrupts b) Memory mapping
c) Program-controlled I/O d) DMA
46. In memory-mapped I/O ____________(1.00)
a) The I/O devices have a separate address space b) The I/O devices and the memory share the same address space
c) A part of the memory is specifically set aside for the I/O operation d) The memory and I/O devices have an associated address space
47. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________(1.00)
a) The clock pulse is LOW b) The clock pulse is HIGH
c) The clock pulse transitions from LOW to HIGH d) The clock pulse transitions from HIGH to LOW
48. The asynchronous input can be used to set the flip-flop to the ____________(1.00)
a) 1 state b) 0 state
c) either 1 or 0 state d) forbidden State

49. Input or output devices that are connected to computer are called ______________.(1.00)
a) Input/Output Subsystem b) Peripheral Devices
c) Interfaces d) Interrupt
50. _______ types of modes of I/O Data Transfer(1.00)
a) 2 b) 3
c) 4 d) 5
51. Keyboard and Mouse Comes under________(1.00)
a) Input peripherals b) Output peripherals
c) Input-Output peripherals d) None of the above
53. In memory-mapped I/O ____________(1.00)
a) The I/O devices have a separate address space b) The I/O devices and the memory share the same address space
c) A part of the memory is specifically set aside for the I/O operation d) The memory and I/O devices have an associated address space

54. The CPU activities the ____________ output to inform the external DMA that the buses are in the high-impedance state.(1.00)
a) Bus request b) Bus Grant
c) Cycle stealing d) None of these
55. Division by zero causes an error of class_____________(1.00)
a) Trap b) Timer interrupt
c) I/O interrupt d) Hardware failure
56. Interrupts that are initiated by an instruction are________(1.00)
a) internal b) external
c) software d) None of these
57. A priority interrupt may be accomplished by___________(1.00)
a) Polling b) Daisy chain
c) Parallel method of priority interrrupt d) All of the above
58. BIOS is________(1.00)
a) A collection of I/O driver programs b) part of OS to perform I/O operation
c) Firmware consisting of I/O driver programs d) a program to certain one of the I/O peripherals

59. ______ is the length of the code sent by the device in vectored interrupt is(1.00)
a) 2 bits b) 4-8 bits
c) 16 bits d) 64 bits
60. DMA stands for_______(1.00)
a) A. Direct memory access b) B. Data memory access
c) C. Distributed memory access d) D. None of these
62. The control unit controls other units by generating ___________(1.00)
a) Control signals b) Timing signals
c) Transfer signals d) Command Signals
63. ______ are numbers and encoded characters, generally used as operands.(1.00)
a) Input b) Data
c) Information d) Stored Values

64. ______ bus structure is usually used to connect I/O devices.(1.00)
a) Single bus b) Multiple bus
c) Star bus d) Rambus
65. The I/O interface required to connect the I/O device to the bus consists of ______(1.00)
a) Address decoder and registers b) Control circuits
c) Address decoder, registers and Control circuits d) Only Control circuits
66. ________ dealing with multiple devices interrupts, which mechanism is easy to implement(1.00)
a) Polling method b) Vectored interrupts
c) Interrupt nesting d) None of the mentioned
67. The starting address sent by the device in vectored interrupt is called as __________(1.00)
a) Location id b) Interrupt vector
c) Service location d) Service id
68. Serial priority interrupt method uses register whose bits are set separately by interrupt signal for each device.(1.00)
a) True b) False

69. The interrupt-request line is a part of the data line(1.00)
a) True b) False
70. ________is not a logic gate(1.00)
a) AND b) OR
c) IF d) NOT
71. XOR circuits can be constructed using_______________(1.00)
a) OR gates only b) AND, OR gates
c) AND, NOT gates d) AND, NOT and OR gates
72. _________ are the alternative form of canonical form(1.00)
a) A Sum of products b) Product of sums
c) Both a and b d) None of the above
73. The sum of products canonical forms also known as ________(1.00)
a) Minterm expansion b) Disjunctive normal form
c) Both a and b d) None of the above

74. ________ number of gates does ultra large scale integration contain(1.00)
a) 100 gates b) 1000 gates
c) 10000 gates d) More than 100,000 gates
75. The basic gate of the CMOS logic family is _____(1.00)
a) NAND b) NOT
c) NAND/ NOR d) None of the above
76. _______ is the Boolean expression of OR logic gate.(1.00)
a) X=A+B b) A-B
c) X=AB d) None of the above
77. The output of the sequential circuit depends upon _________(1.00)
a) Present input b) Past input
c) Present input and present state d) None of the above
78. The flip flops are categorized into ________(1.00)
a) One b) Two
c) Three d) Four

79. _________ is the standard form of S-R flip flop(1.00)
a) Set Reset b) Simple-Reset
c) Single-Reset d) None of the above
80. Example of the use of an S-R flip-flop is as ___________(1.00)
a) Transition pulse generator b) Racer
c) Switch debouncer d) Astable oscillator
81. The truth table for an S-R flip-flop has _________ VALID entries(1.00)
a) 1 b) 2
c) 3 d) 4
82. When both inputs of a J-K flip-flop cycle, the output will ___________(1.00)
a) A. Be invalid b) B. Change
c) C. Not change d) D. Toggle
The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called ________________(1.00)
83.
a) A. Combinational circuits b) B. Sequential circuits
c) C. Latches d) D. Flip-flops

84. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________(1.00)
a) A. The clock pulse is LOW b) B. The clock pulse is HIGH
c) C. The clock pulse transitions from LOW to HIGH d) D. The clock pulse transitions from HIGH to LOW
85. The I/O interface required to connect the I/O device to the bus consists of ______(1.00)
a) A. Address decoder and registers b) B. Control circuits
c) C. Address decoder, registers and Control circuits d) D. Only Control circuits
86. Daisy Chain method is used to establish priority by serially connecting all devices that request an interrupt.(1.00)
87. Serial priority interrupt method uses register whose bits are set separately by interrupt signal for each device.(1.00)
88. Mask register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt.(1.00)

89. The added output of the bits of the interrupt register and the mask register is set as an input of Priority decoder(1.00)
90. The interrupt-request line is a part of the data line(1.00)
91. A number system that uses eight digits,0,1,2,3,4,5,6, and 7 is called an ____________(1.00)
a) A. Binary number system b) B. Decimal number system
c) C. Octal number system d) D. None of these
92. Binary numbers can also be expressed in this same with Reverse notation by ____________ representation(1.00)
a) A. Floating point b) B. Binary point
c) C. Decimal point d) D. All of these
93. How many bits of mantissa________(1.00)
a) A. 4 b) B. 8
c) C. 10 d) D. 16

94. A group of 4 binary bits is called as Byte(1.00)
95. ________ expression shows the commutative law of multiplication(1.00)
a) A. AB = B + A b) B. A + B = B + A
c) C. AB = BA d) D. All of these
96. Boolean algebra, OR is represented by ________(1.00)
a) A. + b) B. –
c) C. *D. /
97. In Boolean algebra, the bar sign ¯ indicates ________(1.00)
a) AND operation b) NOT operation
c) NOR operation d) OR operation
98. And gate represents multiplication operation(1.00)

99. The output of the sequential circuit depends upon _________(1.00)
a) A. Present input b) B. Past input
c) C. Present input and present state d) D. None of the above
100. One major difference between a NAND based S’-R’ latch & a NOR based S-R latch is ____________(1.00)
a) A. The inputs of NOR latch are 0 but 1 for NAND latch b) B. The inputs of NOR latch are 1 but 0 for NAND latch
c) C. The output of NAND latch becomes set if S’=0 & R’=1 and vice versa d) D.The output of NOR latch is 1 but 0 for NAND latch

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CIA II-24ITU03- II Digital Fundamentals and Architecture

Department Name : Information Technology

Date & Time of Exam Max. Marks : 100.00

1. 1. ________ number systems has a base of 16?(1.00)

3. The subtraction of these binary numbers 101001 – 010110 would generate________(1.00)

Sep 21, 2024 Powered by iLearningEngines Page 1 of 21

4. The multiplication of these binary numbers 10100 * 01011 would generate________(1.00)

5. The radix of an octal number system is________(1.00)

6. ________format is used to store data(1.00)

7. 8. Subtraction in computers is carried out by ________(1.00)

a) A. 1' s Copmplement b) B. 2' s Copmplement

c) D. All of these above d) C. 10' s Copmplement

8. In ________form the computer stores its data in memory(1.00)

a) A. Hexadecimal form b) B. Octal form

c) C. Binary form d) D. Decimal form

Sep 21, 2024 Powered by iLearningEngines Page 2 of 21

9. Which system groups number by sixteen and power of sixteen________(1.00)

c) C. Octal d) D.None of these

10. Counting in hex, each digit can be increment from ____________:(1.00)

a) A. Binary number b) B. Decimal number

c) C. Octal number d) D. Hexadecimal number

a) A. Floating point b) B. Binary point

c) C. Decimal point d) D. All of these

13. Floating point representation of a number consists ________(1.00)

Sep 21, 2024 Powered by iLearningEngines Page 3 of 21

16. The exponent contains the decimal number ________(1.00)

17. ________ expression shows the commutative law of multiplication(1.00)

18. ________ expression express the distributive law of Boolean algebra.(1.00)

c) C. A(BC) = (AB) + C d) D. None of these

Sep 21, 2024 Powered by iLearningEngines Page 4 of 21

19. The equation is C + CD is equal to ________(1.00)

20. In Boolean algebra, ________ is meant of this word “literal”(1.00)

a) A. the inverse function b) B. a product term

c) D. All of the above d) C. a variable or its complement

22. Each operation has its Unique opcode(1.00)

23. And gate represents multiplication operation(1.00)

Sep 21, 2024 Powered by iLearningEngines Page 5 of 21

24. Not gate represents the complement of the input(1.00)

26. Example of the use of an S-R flip-flop is as ___________(1.00)

a) A. Transition pulse generator b) B. Racer

c) C. Switch debouncer d) D. Astable oscillator

c) C. Not change d) D. Toggle

Sep 21, 2024 Powered by iLearningEngines Page 6 of 21

29. ___________is correct for a gated D-type flip-flop(1.00)

a) A. Combinational circuits b) B. Sequential circuits

31. Sequential circuits types are _______(1.00)

32. The sequential circuit is also called ___________(1.00)

33. In S-R flip-flop, if Q = 0 the output is said to be ___________(1.00)

c) C. Previous state d) D.Current state

Sep 21, 2024 Powered by iLearningEngines Page 7 of 21

34. Trigger pulse is a ______(1.00)

36. The difference between a flip-flop &amp; latch is ____________(1.00)

a) A.Both are same b) B. Flip-flop consist of an extra output

37. The S-R flip flop consist of ____________(1.00)

a) A. 4 AND gates b) B. Two additional AND gates

c) C. An additional clock input d) D. 3 AND gates

38. _______is a flip-flop said to be transparent?(1.00)

Sep 21, 2024 Powered by iLearningEngines Page 8 of 21

a) A. The clock pulse is LOW b) B. The clock pulse is HIGH

36. The difference between a flip-flop & latch is ____________(1.00)