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Dynamic and Domino Logic

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Shashank N
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40 views18 pages

Dynamic and Domino Logic

Uploaded by

Shashank N
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Dynamic and

domino logic
Dynamic Logic
Dynamic CMOS logic utilizes temporary storage of charge
on a capacitor to perform logic operations, unlike static
CMOS logic which uses a constant flow of current.

Operation Phases
Dynamic CMOS logic operates in two phases:
!) Precharge Phase
2) Evaluation Phase

Speed
Dynamic CMOS logic is generally faster than static CMOS logic

Area Efficiency
It occupies less area than static CMOS logic
Dynamic Logic
Contd...
Power Consumption
It can have lower dynamic power consumption due
to reduced transistor count and capacitance

Noise Sensitivity
Dynamic CMOS logic is more sensitive to noise and
charge leakage because it relies on the storage of
charge on the capacitor.

Clock Synchronization
Requires a clock signal for operation, introducing
the need for precise clock synchronization across
the circuit.
Charge Sharing Problem
It can suffer from charge sharing issues, where charge can
redistribute among the capacitors, potentially leading to
incorrect logic levels.

Application
Commonly used in high-speed, high-performance
applications like microprocessors and digital signal
processors where speed and area efficiency are critical.

Design Complexity
The design of dynamic CMOS circuits can be more complex
due to the need to manage charge leakage and ensure proper
clock timing.
Structure of DYNAMIC Structure of STATIC CMOS
CMOS logic logic

PMOS : K
NMOS : K

PMOS : 1
NMOS : K+1
case 1 : clk = 0
i/p = 1
case 2 : clk = 1
i/p = 1
case 3 : clk = 0
i/p = 0
case 4 : clk = 1
i/p = 0
Cascading effect in
dynamic logic
The problem in cascading conventional dynamic CMOS occurs when one or more inputs
make a 1 to 0 transition during evaluation

Domino circuits can fix the above problem:


During the evaluation, each buffer output can make at most one transition (from 0 to 1),
and thus each input of all subsequent logic stages can also make at most one (0 to 1)
transition.
Domino Logic
Domino CMOS logic is a type of dynamic logic that is widely used in
high-speed digital circuits

Precharge and Evaluation Phases


Like dynamic logic, Domino logic also has two operating phases:
1. Precharge Phase
2. Evaluation Phases

Clock Dependency
The operation of domino logic relies heavily on the clock signal, which
controls the transitions between the precharge and evaluation phases.

High Speed
Domino logic can achieve very high speeds because it reduces the
number of transistors in the critical path and minimizes capacitive
loading.
Domino Logic
Structure
A typical domino logic gate consists of the following components:

1. Precharge Transistor: A PMOS transistor connected to the


clock signal, used to precharge the output node during the
precharge phase.
2. Pull-Down Network (PDN): An NMOS transistor network that
implements the logic function. During the evaluation phase,
depending on the inputs, the PDN can discharge the
precharged output node.
3. Static Inverter: A CMOS inverter that follows the dynamic
stage, providing a stable, static output.
4. The number of PMOS and NMOS transistors are as follows:
Number of PMOS - 2
Number of NMOS - K+2
case 1 : clk = 0
i/p = 1
case 2 : clk = 1
i/p = 1

Domino logic is solving the issue of


cascading but it falls in a problem race.
case 3 : clk = 0
i/p = 0
case 4 : clk = 1
i/p = 0
Thank you
very much!

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