Verilog Common Reference Guide

1. Verilog Syntax Basics

Module Definition
module module_name(input wire a, b, output wire y);
assign y = a & b;
endmodule

 Ports: Defines input/output signals of the module.

 Keywords: module, endmodule, input, output.

Comments

 Single Line: // Your comment

 Multi-Line: /* Your comment */

2. Data Types
wire

 Used for combinational logic.

 Example:

wire result;
assign result = a & b;

reg

 Used for sequential logic (inside procedural blocks).

 Example:

reg result;
always @(posedge clk) begin
result <= a & b;
end

3. Procedural Blocks
Always Block (Sequential Logic)

 Used for clocked (sequential) logic. Use non-blocking assignments (<=)

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always @(posedge clk) begin
out <= a + b;
end

Always Block (Combinational Logic)

 Triggered when inputs change. Use blocking assignments (=).

always @(*) begin

out = a & b;
end

Always # Statement

 Delays the execution within the always block

always @(posedge clk) begin

#5 a <= b; // Delays assignment by 5 units after clk edge
end

4. Conditional Statements
If-Else Statement

always @(a or b) begin

if (a)
out = b;
else
out = c;
end

Case Statement

 Used when checking for multiple conditions.

always @(sel or a or b) begin

case (sel)
2'b00: out = a;
2'b01: out = b;
default: out = 0;
endcase
end
end

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5. Blocking vs Non-blocking Assignments
Blocking Assignment (=)

 Executes in order, suitable for combinational logic.

always @(posedge clk) begin

a = b; // Blocking
b = a;
end

Non-blocking Assignment (<=)

 Executes in parallel, suitable for sequential logic.

always @(posedge clk) begin

a <= b; // Non-blocking
b <= a;
end

6. Loops in Verilog
For Loop

 Useful for iterating over arrays or bits.

for (i = 0; i < 8; i = i + 1) begin

sum = sum + data[i];
end

Generate-For Loop

 Synthesis-friendly loop, used to generate repetitive hardware.

genvar i;
generate
for (i = 0; i < 8; i = i + 1) begin
assign y[i] = a[i] & b[i];
end
endgenerate

Forever Loop

 Repeats indefinitely; typically used in testbenches.

initial forever begin

#5 clk = ~clk; // Toggle clk every 5 time units
end

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7. Timing Controls in Verilog
#delay

 Introduces simulation delays, not synthesizable.

#10; // Delay by 10 time units

@posedge and @negedge

 Trigger actions on signal edges

always @(posedge clk) begin
q <= d;
end
wait

 Suspends execution until a condition is true.

wait (signal == 1);

8. Functions and Tasks

Functions

 Return values and can be used in expressions. Must execute in a single time unit.

function [7:0] add;

input [7:0] a, b;
begin
add = a + b;
end
endfunction

Tasks

 Can span multiple time units and may not return a value.

task delay_task;
begin
#5;
$display("Task completed");
end
endtask

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Calling Functions and Tasks

 Function Call:

y = add(a, b);

 Task Call:

delay_task(); // Calls a task

Difference between Functions and Tasks

Aspect Functions Tasks
Return Value Must return a value Can have no return value
Calls in Allowed Allowed
Always
Execution Must complete in a single time Can span multiple time units
Time unit (using #, @)
Use Cases Typically used for combinational Often used for sequential logic
logic

9. Parameters
Parameterized Module

 Allows setting constant values for modules.

module adder #(parameter WIDTH = 8) (input [WIDTH-1:0] a, b, output [WIDTH-

1:0] sum);
assign sum = a + b;
endmodule

Local Parameters

 Internal to a module, not modifiable from outside.

localparam MAX = 255;

10. Synthesis vs Simulation

Aspect Synthesis Simulation
Purpose Converts HDL to hardware Verifies functionality of the
(FPGA/ASIC) design
Delays Does not include delays (#, @) Includes all delays
Timing Timing controls not synthesized Fully simulates timing control
Controls
Tool Tools like Synopsys, Xilinx Tools like ModelSim, VCS

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11. Latches and Race Conditions
Latch Inference

 Occurs when all cases are not covered in combinational logic.

 Example: Missing else clause

if (a) y = b; // Incomplete case, can cause latch inference

 Solution: Ensure all cases are covered with else or default assignments.

Race Conditions

 Caused by using blocking assignments in sequential logic.

a = b; // Blocking causes race conditions

b = a;

 Solution: Use non-blocking assignments (<=) for sequential logic.

Issue Cause Solution

Latch Inference Missing else/default cases in Cover all cases with else or
combinational logic default
Race Condition Using blocking (=) in sequential Use non-blocking (<=) for
logic sequential logic
Combinational Circular dependencies in Avoid circular dependencies
Loop combinational logic

12. Testbench Constructs

Construct Description Example
$monitor Monitors signal changes and prints $monitor("a=%b, b=%b", a, b);
them automatically
$display Prints values once at a specific $display("a=%b, time=%0t", a,
$time);
point in the simulation
$finish Ends the simulation initial $finish;
$stop Halts the simulation for debugging initial $stop;
$time Returns the current simulation $display("Simulation time:
%0t", $time);
time

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13. Final Summary

 Procedural Blocks: Ensure all conditions are covered in combinational logic to

avoid latch inference.
 Blocking vs Non-blocking: Use non-blocking (<=) in sequential logic and
blocking (=) in combinational logic to avoid race conditions.
 Synthesis vs Simulation: Remember that some constructs (e.g., timing delays)
are valid only in simulation and not in synthesis.
 Functions vs Tasks: Choose functions for combinational logic and tasks when
timing controls are needed.

Table 1: Basic Verilog Syntaxes

Syntax Description Example
module and Defines the start and end of a Verilog module adder(input a, b,
output sum); ... endmodule
endmodule module, which contains the code
describing the hardware.
input / Declares input and output ports for a input wire a, b; output
output wire sum;
module.
wire Declares combinational logic wire result; assign result
connections. Used in assign = a & b;
statements.
reg Declares variables that hold values reg [7:0] data; always
@(posedge clk) data <=
between clock cycles. Required for data + 1;
sequential logic inside procedural
blocks.
assign Used for continuous assignments assign y = a & b;
(combinational logic).
always Defines a block of procedural code always @(posedge clk)
begin out <= a + b; end
that executes whenever a triggering
event occurs (for sequential or
combinational logic).
initial Executes procedural code once at the initial begin a = 0; b =
1; end
beginning of the simulation (used for
testbenches).
if-else Conditional statement, executes a if (a == 1) b = 0; else b
= 1;
block if a condition is true, otherwise
executes the else block.
case Used for multi-way branching based case (sel) 2'b00: out = a;
2'b01: out = b; default:
on the value of an expression. out = 0; endcase
for Iterative loop, typically used for for (i = 0; i < 8; i = i +
1) sum = sum + data[i];
generating hardware structures or
iterating over arrays.
forever Infinite loop, often used in initial forever begin #5
clk = ~clk; end
testbenches for clock generation or
repetitive behavior.

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 generate Synthesis directive used to replicate generate for (i = 0; i <
8; i = i + 1) assign
hardware structures in a out[i] = in1[i] & in2[i];
parameterized way. endgenerate

Table 2: Advanced Constructs and Timing Control

Syntax Description Example
function Declares a function that performs a function [7:0] add;
input [7:0] a, b; add =
specific task and returns a value. a + b; endfunction
task Declares a task that performs a task delay_task; #5;
endtask
specific action but may not return a
value and can include time delays.
parameter Declares constant values that can be parameter WIDTH = 8;
used in modules and changed during
instantiation.
localparam Declares constants local to the localparam MAX = 255;
module, not modifiable from outside.
# (Delay Introduces a simulation delay, often #10; // Delay for 10
time units
Statement) used in testbenches.
posedge / Triggers procedural code based on always @(posedge clk)
negedge the rising or falling edge of a signal.
wait Suspends execution until a specific wait (ready == 1);
condition is met.
force Forces a signal to a specific value force clk = 1;
during simulation.
release Releases a previously forced signal, release clk;
returning control to the design.
fork...join Executes multiple statements in fork stmt1; stmt2; join
parallel.
begin...end Groups multiple procedural begin stmt1; stmt2; end
statements into a block.
# (delay) Introduces simulation delay (cannot #5 a = 1;
be synthesized).

Learning platform Verilog

Simulation EDA play ground

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Table 3: Testbench Constructs and Utilities
Syntax Description Example
$monitor Continuously monitors and prints signal $monitor("time=%0t
a=%b", $time, a);
changes throughout simulation
(testbenches).
$display Prints signal values once during $display("a=%b, b=%b",
a, b);
simulation at a specific point.
$finish Ends the simulation. initial $finish;
$stop Pauses simulation for debugging initial $stop;
purposes.
$time Retrieves the current simulation time. $display("Time: %0t",
$time);
disable Terminates a block of code or named disable my_block;
block in a function or task.
primitive Defines a basic gate primitive (AND, OR, primitive my_and(out, a,
b); ... endprimitive
etc.) in Verilog.
defparam Changes the value of a parameter after defparam
my_instance.WIDTH = 16;
module instantiation (not preferred).
always_comb Used to define combinational logic that always_comb out = a & b;
should run anytime any input changes
(SystemVerilog, a stricter version of
always @*).
always_ff Defines sequential logic driven by a always_ff @(posedge clk)
q <= d;
clock edge (SystemVerilog, stricter
version of always @(posedge clk)).

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