9-Verilog Coding and Synthesis Methodology Guidelines
9-Verilog Coding and Synthesis Methodology Guidelines
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VERILOG FOR SYNTHESIS
a
b c
// Using a reg
//
wire a,b;
reg c;
always @ (a or b)
c = a & b;
// Using a wire
//
wire a,b,c;
assign c = a & b;
// if c is an output
//
output c;
reg a,b;
assign c = a & b;
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2.2 Multiplexers
// 1. using an always a
always@(a or b or sel)
1
b
if (sel == 1’b1) c 0
c = a;
else
c = b;
sel
Use default assignments
to prevent latches: every
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VERILOG FOR SYNTHESIS
sel
2’b10 2’b11
2
= =
c 0
0
b 1 d
1
a
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VERILOG FOR SYNTHESIS
// 2. using an if statement
always @ (sl or a or b or c)
if (sel == 2’b11)
d = a;
else if (sel ==2’b10)
d = b;
else
d = c;
sel
2’b10 2’b11
2
= =
c 0
0
b 1 d
1
a
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VERILOG FOR SYNTHESIS
c 2’b0x
b 2’b10 d
a 2’b11
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enable
d[3:0]
c[3:0]
4
4
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e = {a[1],b[3:2]}
a[3]
a[2]
a[1] e[2]
a[0] e[1]
b[3] e[0]
b[2]
b[1]
b[0]
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VERILOG FOR SYNTHESIS
a[0] b[0]
a[1] b[1]
b[2]
b[3]
// bus replication
wire [1:0] a;
wire [3:0] b;
assign b = {2{a}};
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VERILOG FOR SYNTHESIS
2.6 Comparators
// 1. using a wire
wire d;
assign d = (a == c);
// 2. using a reg
reg d;
always @ (a or c)
d = (a == c);
a[3:0]
4
= 1
d
c[3:0]
4
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VERILOG FOR SYNTHESIS
d q
d q
clock
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VERILOG FOR SYNTHESIS
reset
clock
clock
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clock
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q
d
enable
clock
d q
clock
enable
gclk
enable signal must be
glitch free
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2.10 Latches
// 1. latch
always @ (enable or d)
if (enable)
q = d; d q
enable
// 2.resettable latch
always @ (enable or d or reset)
if (reset)
q = 1’b0;
reset
else if (enable)
q = d;
d q
enable
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VERILOG FOR SYNTHESIS
// 2. using a wire
wire y;
assign y = enable ? d : 1’bz;
// 3. using a primitive
bufif1 (y,d,enable);
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2.12 Counter
3 bit asynchronously resettable counter which counts 0, 1, 2, 3, 4, 5,
// 3 bit asynchronously resettable
// partial range counter
always @ (posedge clock or posedge reset)
if (reset)
count <= 3’b0;
else
if (count == 3’b101)
count <= 3’b0;
else
count <= count + 3’b001;
reset
3’b001
3’b000 1 count
0 3
3
enable
=
3’b101 clock
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VERILOG FOR SYNTHESIS
data_out
data_in
clock
enable
endmodule
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VERILOG FOR SYNTHESIS
12
b e
5
6
d
Note that the * and + and - signs give you unsigned arithmetic. If you need signed arithmetic, you may need special
instaces recognizable to the synthesis tool.
• Adding two five bit numbers gives a siz bit result (the extra bit is the carry out bit).
• The multiplication of two number means that the output is twice the width of the inputs.
wire [5:0] c = a + b;
wire [11:0] e = c * d;
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// Good commenting
// 8 bit unsigned adder for data signals ‘a’ and ‘b’
// output is sent to UART2
always @ (a or b)
c = a + b;
• Don’t make the code any more complicated than it needs to be. Your priorities should be correctness, then read-
ability and finally code efficiency.
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state encoding
wait stop
ack = 1’b1
PAUSE
offline = 1’b0
online = 1’b1 2’b01 output values
FINISH
2’b11 ack = 1’b1
stop offline = 1’b0
online = 1’b1
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VERILOG FOR SYNTHESIS
// IO declaration section
input clock;
input reset;
input start, transmit, wait, stop;
output ack, offline, online;
// interal variables declaration section
reg [1:0] state, next_state;
reg ack, offline, online;
endmodule
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