International Journal on Recent and Innovation Trends in Computing and Communication

Volume: 1 Issue: 4 263 – 268

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Implementation of serial communication using UART with configurable baud rate
*
Ms.Neha R. Laddha Prof.A.P.Thakare
ME-DE. Professor a n d
Sipna C.O.E.T, Amravati (MS) INDIA Head of Electronics & Telecomm.Deptt.
[email protected] Sipna C.O.E.T, Amrava ti (MS) INDIA

Abstract:- Today in real world the actual applications, usually needed only a few key features of UART. Specific interface chip will cause
waste of resources and increased cost. Particularly in the field of electronic design, SOC technology is recently becoming increasingly
mature. This situation results in the requirement of realizing the whole system function in a single or a very few chips. Universal
Asynchronous Receiver Transmitter (UART) is a kind of serial communication protocol. In parallel communication the cost as well as
complexity of the system increases due to simultaneous transmission of data bits on multiple wires. Serial communication alleviates this
drawback of parallel communication and emerges effectively in many applications for long distance communication as it reduces the signal
distortion because of its simple structure. The UART implemented with VHDL language can be integrated into the FPGA to achieve
compact, stable and reliable data transmission. This paper presents implementation of Multi UART with configurable baud rate. Also we
can verify the output using LED’s on Altera’s DE1 board.

Keywords:- UART; Asynchronous serial communication; VHDL; Quartus II; simulation, Altera DE1 Cyclone II board.
_____________________________________________________*****______________________________________________________

I. INTRODUCTION UART; RXD is the receiver, the input of UART. UART‟s

basic features are: There are two states in the signal line, using
Universal Asynchronous Receiver Transmitter logic 1 (high) and logic 0
(UART) is a kind of serial communication protocol; mostly (low) to distinguish respectively. For example, when the
used for short-distance, low speed, low-cost data exchange transmitter is idle, the data line is in the high logic state.
between computer and peripherals. UARTs are used for Otherwise when a word is given to the UART for
asynchronous serial data communication by converting data asynchronous transmissions, a bit called the "Start Bit" is
from parallel to serial at transmitter with some extra overhead added to the beginning of each word that is to be transmitted.
bits using shift register and vice versa at receiver. Serial The Start Bit is used to alert the receiver that a word of data is
communication reduces the distortion of a signal, therefore about to be sent, and to force the clock in the receiver into
makes data transfer between two systems separated in great synchronization with the clock in the transmitter.
distance possible. It is generally connected between a After the Start Bit, the individual data bits of the
processor and a peripheral, to the processor the UART appears word are sent, with the Least Significant Bit (LSB) being sent
as an 8-bit read/write parallel port. The UART implemented first. Each bit in the transmission is transmitted for exactly the
with VHDL language can be integrated into the FPGA to same amount of time as all of the other bits, and the receiver
achieve compact, stable and reliable data transmission [3]. “looks” at the wire at approximately halfway through the
Various designs are found in literatures for UART as different period assigned to each bit to determine if the bit is a 1 or a 0.
systems have different requirements and attributes which When the entire data word has been sent, the
require data communication between its functional units. In transmitter may add a Parity Bit that the transmitter generates.
recent years the researchers have proposed various UART The Parity Bit may be used by the receiver to perform simple
designs like automatic baud rate synchronizing capability[2], error checking. Then at least one Stop Bit is sent by the
predictable timing behavior to allow the integration of nodes transmitter. When the receiver has received all of the bits in
with imprecise clocks in time-triggered real-time systems[4], the data word, it may check for the Parity Bits (both sender
recursive running sum filter to remove noisy samples[2], and receiver must agree on whether a Parity Bit is to be used),
integration of only core functions into a FPGA chip to achieve and then the receiver looks for a Stop Bit.
compact, stable and reliable data transmission to avoid waste Regardless of whether the data was received correctly
of resources and decrease cost[1], programmable logic to or not, the UART automatically discards the Start, Parity and
enable interfacing between asynchronous communications Stop bits. If the sender and receiver are configured identically,
protocols and DSP having synchronous serial ports. these bits are not passed to the host. If another word is ready
Basic UART communication needs only two signal for transmission, the Start Bit for the new word can be sent as
lines (RXD, TXD) to complete full-duplex data soon as the Stop Bit for the previous word has been sent.
communication. TXD is the transmit side, the output of Because asynchronous data are “self synchronizing”, if there
are no data to transmit, the transmission line can be idle. The
UART frame format is shown in Fig. 1.

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International Journal on Recent and Innovation Trends in Computing and Communication

Volume: 1 Issue: 4 263 – 268

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complex as complete blocks of memory. FPGAs that store
their configuration internally in nonvolatile flash memory,
such as Micro semi‟s ProAsic 3 or Lattice's XP2
programmable devices, do not expose the bitstream and do not
need encryption. In addition, flash memory for LUT provides
SEU protection for space applications. Advantages of FPGA is
as follows:

Ability to re-program in the field to fix bug.

Fast prototyping and turn-around time.
NRE cost is zero.
High-Speed.
Low cost.
Fig 1. UART Frame Format
III. ALTERA DE1 DEVELOPMENT AND
In this paper, we present UART which includes three modules
EDUCATIONAL BOARD
which are the baud rate generator, receiver and transmitter.
The proposed design of UART satisfies the system
Altera DE1 board become one of the most widely
requirements of high integration, stabilization, low bit error
development FPGA board which is used to development of
rate, and low cost. It also supports configurable baud rate
FPGA design and implementations. The purpose of the Altera
generator with data length of 8 bits per frame. The
DE1 Development and Education board is to provide the ideal
configurable baud rate generator has been implemented using
vehicle for learning about digital logic, computer organization,
two switches of cyclone II FPGA in DE1 Board which
and FPGAs. It uses the state-of the art technology in both
specifies the baud rate of input and accordingly input data can
hardware and CAD tools to expose researchers and
verified with start bit and stop bit on LED‟s of cyclone II
professionals to a wide range of topics. The board offers a rich
FPGA in DE1 Board.
set of features that make it suitable for research work Altera
provides a suite of supporting materials for the DE1 board,
including tutorials, “ready-to-teach” laboratory exercises, and
II. FPGA:
illustrative demonstrations [Altera] Figure (2) gives the block
diagram of the DE1 board. To provide maximum flexibility
FPGA or Field Programmable Gate Arrays can be for the user, all connections are made through the Cyclone II
programmed or configured by the user or designer after FPGA device. Thus, the user can configure the FPGA to
manufacturing and during implementation. Hence they are implement any system design.
otherwise known as On-Site programmable. Unlike a The DE1 board features a state-of-the-art Cyclone® II 2C20
Programmable Array Logic (PAL) or other programmable FPGA in a 484-pin package. All important components on the
device, their structure is similar to that of a gate-array or an board are connected to pins of this chip, allowing the user to
ASIC. Thus, they are used to rapidly prototype ASICs, or as a control all aspects of the board‟s operation. For simple
substitute for places where an ASIC will eventually be used. experiments, the DE1 board includes a sufficient number of
This is done when it is important to get the design to the robust switches (of both toggle and push-button type), LEDs,
market first. The programming of the FPGA is done using a and 7-segment displays. For more advanced experiments,
logic circuit diagram or a source code using a Hardware there are SRAM, SDRAM, and Flash memory chips. For
Description Language (HDL) to specify how the chip should experiments that require a processor and simple I/O interfaces,
work. FPGAs have programmable logic components called it is easy to instantiate Altera‟s Nios II processor and use
‚logic blocks‛, and a hierarchy or reconfigurable interconnects interface standards such as RS-232 and PS/2. For experiments
which facilitate the ‚wiring‛ of the blocks together. The that involve sound or video signals, there are standard
programmable logic blocks are called configurable logic connectors for microphone, line-in, line-out (24-bit audio
blocks and reconfigurable interconnects are called switch CODEC), SD memory card connector, and VGA; these
boxes. Logic blocks (CLBs) can be programmed to perform features can be used to create CD-quality audio applications
complex combinational functions, or simple logic gates like and video. Finally, it is possible to connect other user defined
AND and XOR. In most FPGAs the logic blocks also include boards to the DE1 board by means of two expansion headers.
memory elements, which can be as simple as a flip-flop or as

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International Journal on Recent and Innovation Trends in Computing and Communication

Volume: 1 Issue: 4 263 – 268

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Assume that the system clock is 50MHz, baud rate is 9600bps,

and then the output clock frequency of baud rate generator
should be 1* 9600Hz.
Therefore the frequency coefficient (M) i.e. counts
value of the baud rate generator is:
M =50MHz/1*9600Hz=5208
When the UART receives serial data, it is very
critical to determine where to sample the data information.
The ideal time for sampling is at the middle point of each
Fig 2. Cyclone II FPGA 2C20 serial data bit.
In this design, we designed configurable baud rate
IV. IMPLEMENTATION OF MULTI-UART. generator which can selected by using two switch of cyclone
II DE1 board. The selection of baud rate is as shown.
The UART serial communication module is divided
into three sub-modules: the baud rate generator, receiver S0 S1 Baud Rate(BPS)
module and transmitter module, shown in Fig. 3. Therefore, 0 0 2400
the implementation of the UART communication module is 0 1 4800
actually the realization of the three sub-modules. The baud 1 0 9600
rate generator is used to produce a local clock signal which is 1 1 19200
much higher than the baud rate to control the UART receive Default 9600
and transmit; The UART receiver module is used to receive
the serial signals at RXD, and convert them into parallel data; Hence, different baud rate has different frequency
The UART transmit module converts the bytes into serial bits coefficient (M) i.e. count value of the baud rate generator.
according to the basic frame format and transmits those bits For 2400Hz, M =50MHz/1*2400Hz=20833
through TXD. For 4800Hz, M =50MHz/1*2400Hz=10416
For 9600Hz, M =50MHz/1*2400Hz=5208
For 19200Hz, M =50MHz/1*2400Hz=2604

B. Receiver Module
During the UART reception, the serial data and the
receiving clock are asynchronous, so it is very important to
correctly determine the start bit of a frame data. The receiver
module receives data from RXD pin. RXD jumps into logic 0
from logic 1 can be regarded as the beginning of a data frame.
When the UART receiver module is reset, it has been waiting
the RXD level to jump. As we know, the ideal time for
sampling is at the middle point of each serial data bit. Hence,
RXD low level lasts at least half of receiving clock cycles is
considered start bit arrives. Once the start bit been identified,
Fig 3. UART Module from the next bit, begin to count the rising edge of the baud
clock, and sample RXD when counting. Each sampled value
A. Baud Rate Generator of the logic level is deposited in the register
Baud Rate Generator is actually a kind of frequency parallel_data_signal [7, 0] by order. When the count equals
divider. The baud rate frequency factor can be calculated 10, all the data bits are surely received, also the 10 serial bits
according to a given system clock frequency and the required are converted into a byte parallel data and deposited in the
baud rate. The calculated baud rate frequency factor is used as resister parallel_data.
the divider factor.

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International Journal on Recent and Innovation Trends in Computing and Communication

Volume: 1 Issue: 4 263 – 268

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The state machine includes five states: R_Initial (waiting for
the start bit), R_Center (find midpoint), R_Delay (Waiting for The function of transmit module is to convert the sending 8-bit
the sampling), R_Shift register (sampling), and R_Stop parallel data into serial data, adds start bit at the head of the
(receiving stop bit). data as well as stop bits at the end of the data. When the
UART transmit module is reset by the reset signal, the
transmit module immediately enters the ready state to send. In
this state, the 8-bit parallel data is read into the Shift register
[7: 0]. The transmitter only needs to output 1 bit every
bit_count. The order follows 1 start bit, 8 data bits and 1 stop
bit. Fig.5 shows the transmit module state diagram. This state
machine has 5 states: X_Initial (free), X_Start (start bit),
X_Delay (shift to wait), X_Shift register (shift), X_Stop (stop
bit).

Fig 4. Reciever FSM

R_Initial Status: Initially, the UART receiver is reset; the

receiver state machine will be in this state. In this state, the
state machine has been waiting for the RXD level to be at
logic 0, i.e. the start bit. Start bit indicates the beginning of a
new data frame. Once the start bit is identified, the state
machine will be transferred to Center state. Also, In this state,
start_flag is set to 1.

R_Center Status: For asynchronous serial signal, in order to

detect the correct signal each time, and minimize the total
error in the later data bits detection. Obviously, it is the most Fig 5. Transmitter FSM
ideal to detect at the middle of each bit. In this state, the task is
to find the midpoint of each bit through the start bit. The X_Initial Status: When the UART is reset, the state machine
method is by counting the number of clk_count. will be in this state. In this state, the UART transmitter has
been waiting a data frame. When data frame is arrived, the
R_Delay Status: When the state machine is in this state, state machine transferred to Start , get ready to send start bit.
waiting for counting to reach final count value, then entering Start bit indicates the beginning of a new data frame.
into shift register to sample the data bits. At the same time
determining the received data in 10 bit with start and stop bit. X_Start Status: In this state, sends a logic 0 signal to the TXD
for one bit time width, the start bit. Then the state machine
R_Shift register Status: In this state, data bits are sampled and transferred to delay state.
stored it into shift register which is of 8 bit. After sampling the
state machine transfers to delay state unconditionally, waits X_Delay Status: Similar with the R_delay state of UART
for the arrival of the next start bit. Also in this state, the receive state machine.
start_flag is reset.
X_Shift register Status: In this state, the state machine realizes
R_Stop Status: when stop bit is 1. State machine doesn‟t the parallel to serial conversion of outgoing data. Then
detect RXD in stop. After the stop bit, state machine turns immediately return to X_delay state.
back to R_START state, waiting for the next frame start bit.
X_Stop Status: Stop bit transmit state. When the data frame
transmit is completed, the state machine transferred to this
state, and sends logic 1 signal, that is, 1 stop bit. The state
C. Transmit Module
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International Journal on Recent and Innovation Trends in Computing and Communication

Volume: 1 Issue: 4 263 – 268

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machine turns back to X_Initial state after sending the stop bit,
and waits for another data frame to transmit.

V. OVERALL SIMULATION OF MODULES

The simulation software is ModelSim. Fig. shows simulation

of UART as a single entity. From simulation waveform, we
select baud rate as 19200 using "sel" pin as "11" , as changes
happen on "rxd" lines that serial data is stored in shift register
and gives parallel data which contains start bit, data bit(8) and
Stop bit.

Since, the baud rate is 9600 bps, we have to select switch „s0‟
as “1” & „s1‟ as “0” which specified that the selected baud
rate on Altera DE1 is 9600 bps which means that both baud
rate are synchronized. The input data send by USART hyper
Fig 6. Simulation Result terminal of micro C AVR software is „A‟ which as a binary
value of 8 bit „01000001‟. The corresponding output is shown
on FPGA board using respected LED‟s with start bit and stop
VI. RESULTS: bit. The output for data is shown in following figure.

The synthesis is done with Quartus II. After synthesis, code is Considering second input shown below. Here the
burn on Altera‟s DE1 Cyclone II FPGA: EPC215AF484C7 selected baud rate is 19200 bps to send data „B‟.
board. In this design instead of using PC hyper terminal,
USART hyper terminal of micro C AVR software is used, for
any key board character transmission and reception.
Considering first input shown below. Here the selected baud
rate is 9600 bps to send data „A‟.

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International Journal on Recent and Innovation Trends in Computing and Communication

Volume: 1 Issue: 4 263 – 268

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Since, the baud rate is 19200 bps, we have to select switch REFERENCES
„s0‟ as “1” &‟ s1‟ as “1” which specified that the selected [1] Fang Yi-yuan; Chen Xue-jun; , "Design and Simulation of
baud rate on Altera DE1 is 19200 bps which means that both UART Serial Communication Module Based on VHDL,"
baud rate are synchronized. The input data send by USART Intelligent Systems and Applications (ISA), 2011 3rd
hyper terminal of micro C AVR software is „B‟ which as a International Workshop on , vol., no., pp.1-4, 28-29 May
binary value of 8 bit “01000010”. The corresponding output is 2011.
shown on FPGA board using respected LED‟s with start bit
[2] Himanshu Patel; Sanjay Trivedi; R. Neelkanthan; V. R.
Gujraty; , "A Robust UART Architecture Based on Recursive
Running Sum Filter for Better Noise Performance," VLSI
Design, 2007. Held jointly with 6th International Conference
on Embedded Systems., 20th International Conference on ,
vol., no., pp.819-823, Jan. 2007.

[3] Gallo, R.; Delvai, M.; Elmenreich, W.; Steininger, A.; ,

"Revision and verification of an enhanced UART," Factory
Communication Systems, 2004. Proceedings. 2004 IEEE
International Workshop on , vol., no., pp. 315- 318, 22-24
Sept. 2004.

[4] Elmenreich, W.; Delvai, M.; , "Time-triggered

communication with UARTs," Factory Communication
Systems, 2002. 4th IEEE International Workshop on , vol.,
no., pp. 97- 104, 2002J. Clerk Maxwell, A Treatise on
Electricity and Magnetism, 3rd ed., vol. 2.Oxford: Clarendon,
1892, pp.68–73.

and stop bit. The output for data is shown in following figur

VII. CONCLUSION:

This paper describes the architecture of Multi UART that

supports 8 bit data word length, start bit as well as stop bit and
configurable baud rates for serial transmission of data.
Working principle of this UART has been tested using
Modelsim simulator and quartus II is used for synthesis.
Additionally we can verify the output using LED‟s on Altera
DE1 board.

VIII. ACKNOWLEDGMENT:

We would like to acknowledge the Faculties of Electronics

& Telecommunication Department, Sipna College of
Engineering & Technology, Amravati for their support. I Neha
R. Laddha specially want to thank my guide Prorfessor and
H.O.D A.P.Thakare sir for their valuable guidance and
constant encouragement towards the work.

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