Proc. IEEE 2004 Int. Conference on Microelectronic Test Structures. Val 17. March 2004.

235

8.17
Direct Extraction Methodology for Geometry-Scalable RF-CMOS Models
drain
Sorin P. Voinigescu', Mihai Tazlauanu2, P.C. Ho', and M.T.Yang'
source
1) ECE Department, University
# of Toronto, 10 King's College Rd. Toronto, ON, M5S 3G4, Canada,
2) Quake Technologies Inc., 80 Hines Rd. Ottawa, ON, K2K 2T8 Canada,
E
3) TSMC, No.9, Creation Rd. 1, Science-based Industrial Park, Hsin-Chu, Taiwan, R.O.C.
I
Abstract-A new method to directly extract the MOSFET @-range. Second, with the MOSFET biased in strong
small-signal parameters - including non-quasi-static effects
- from Z and Y parameter measurements is presented. This
& -
inversion Vcs = 0.8 V and Vos = 0.01 V, the extrinsic
resistive elements R,, R8, and Rd are extracted from the high-
technique is employed to generate a scalable BSIM3v3 frequency limit of the measured RelZiJ. Re{Z,{-Z,?), and
model valid for standard, low and high-threshold p- and n- Re{Z22-Z,2/data, respectively. The Y matrix of the inmnsic
channel MOSFETs at frequencies up to SO GHz. The model equivalent circuit (dashed box in Fig. 1) is then obtained by
accurately captures cutoff frequency degradation for unit Z-to-Y matrix conversion after de-embedding R,, R , and Rd
gate finger widths below 1 p m and was employed to verify from the measured Z matrix. Next, the majority of the
the measured jitter of a 10-Ghls MOS-CML output driver. intrinsic circuit parameters are extracted directly, at each
bias point, as illustrated in Figs. 3-6, using the eqns. (1)-(4)
INTRODUCTION * = z below.

As the minimum feature size of MOSFETs approaches R,=%I(YjI+YJ'I Rgd=%I-KiI (1)

100 nm, the gate-source and gate-drain overlap and fringing
capacitances become comparable to the internal gate
capacitance and contribute significantly to the degradation
of RF and high-speed device performance. The degradation

#
of logic performance is particularly severe because most
digital cells rely on minimum size transistors with W/L
ratios lower than 5, where gate-bulk overlap capacitance
further reduces speed and inevitably leads to increased
power dissipation.
Following a trend set by bipolar model extraction Ryd-
techniques, it has been recognized recently [1]-[2] that
fitting, or a combination of fitting and direct extraction of The measurement accuracy and the validity of the NQS
capacitances and substrate network from S parameters equivalent circuit are first confirmed by the fact that the
measured on typical size transistors is a crucial step towards values of C . , c s d , g., R8,, calculated at each frequency are
improving MOSFET models for RF and high-speed practically constant over a large frequency range up to SO
applications. Even in that case, unless the source, gate, and GHz. 4 is obtained from the slope of the measured phase
drain series resistance are adequately de-embedded at high curves (4). as shown in Fig. 4. The output conductance and
frequency, the extracted device capacitance values can be the total output capacitance are derived from the sub I-GHz
underestimated by as much as 20%. range of
This paper extends the direct extraction approach [I] to g * = ~ I Y , + Y , , I ; ~ * + ~ , =aw
~ ~ J i Y , * + Y , (*5 )l l
avoid these pitfalls and proves that it is possible to construct
a scalable, multiple-threshold, non-quasi-static NQS RF
equivalent circuit (Fig. 1) directly from measured Z and Y Finally, processing the measured data above 40 GHz and
parameters. removing gdc,the substrate network parameters R h C*, and
C& are obtained, using eqns. (5-6)as illustrated in Fig.7.
SINGLE-TRANSISTOR EXTRACTION R , s ~ R ( ( Y , , + Y , , - g , ) - ' l ; C * i . la~ ( 3 [ y ~ , + y d (6)
TECHNIQUE

The extraction methodology is based on the small signal

Figs. 8-13 summarize the impact of de-embedding R, R,,
circuit of Fig.1. NQS effects are represented by the channel
and FL on the accuracy of the small-signal equivalent circuit
source and drain resistance R, and RZd,respectively, and by
parameters. By not adequately de-embedding these series

·
the transconductance delay 4. First, a two-step series-shunt parasitics from the measured S parameter data,
de-embedding technique is employed to remove the 15-fF transconductance and capacitance can be overestimated by
pad capacitance and series interconnect inductance (30-50 more than 15%, and the NQS parameters R, Rgr, and 4 by
pH and resistance (0.5 -1 a ) .As shown in Fig. 2, the pads more than 200%. The latter are particularly sensitive to the
behave as ideal, lossless capacitors up to 50 GHz. This is values of R, R , and & and their accurate experimental
important in minimizing de-embedding errors and makes it extraction remains questionable.
possible to accurately extract gate capacitance values in the

0-7803-8262-5/04/$I7.0002004 IEEE 04CH37S I6

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 236

The single-transitor extraction methodology was applied =

L

to a minimal set of appropriately selected low, standard,

-
Ry Ryd
.

over gate width (Figs. 18-22) and over thieshold voltage Cds . 0 10 20 30 40 50
(Figs. 23 and 24). The model accurately captures fr
degradation (Fig. 22) for minimum gate width, as well as
Frequency (GHz)
the continued improvement in fMAX beyond 120 GHz as the Figure 2 Measured input pad and output pad capacitance
unit finger width, and hence gate resistance, is reduced. as afunction offiequency for a iypical transistor test
Note that the transconductance remains unchanged at structure. Note that there is no noticeable resistive loss.
lmSlp m even for a unit finger width of 0.5 p m indicating
that fr degardation is solely due to gate-bulk overlap LVT NMOS: L=0.13pm, N=10, W=4wm
capacitance.
The model was next (Figs 25-28) employed to simulate
the performance of a MOS-CML driver, using low- and
staandard V, MOSFETs, and operating at 10-to-20 Gbls
data rates from a 1.2-V supply. The agreement is very good
for both small-signal S-parameters, as well as for the jitter
and risdfall times of eye diagrams measured at 10- to-14- Rg. R,. RG de-embedding
Gbls data rates.

CONCLUSIONS

A technique for the direct extraction of the NQS

equivalent circuit parameters of 0 . 1 3 . ~m MOSFETs was
presented. This allowed for the development of a scalable 20 30 40 50
RF subcircuit usable for devices with variable gate length, Frequency (GHz)
width and thershold. The model accurately captures fr and Figure 3 Frequency dependence of the extracted R&sing
f, behaviour for the entire bias range and useful device eqn. ( I ) wifh and without de-embedding 5 R8 andRh
geometries. Its validity was verified on the S-parameter
and jitter performance of 10-Gbls output drivers.
LVT NMOS: L=O.l3pm, W = 4 ~ m N=10
,
REFERENCES

[ 11 F.X. Pengg, "Direct parameter extraction on RF-

CMOS," RFIC-Symp. Digest, pp.271-274,2002.
[2]Y-S. Lin, S-S. Lu, T-H.Lee and H-B.Liang,
"Characterization and modeling of small-signal
substrate resistance effect in RF CMOS," RFIC-Symp.
Digest, pp.161-164,2002.
Zirgin
9 V,,.;0.8V, 1
3 VGs= 0.3V to 1.2V step 0.075V C
G y 3 ; T z IRd D
=
F
..-......( .......................
Rr

Figure I Small signal equivalent circuit.

X
Y11 =
ggs +jw(gs I = YILVI + Yiz V
Yiz Iz = Y2Vl + VzV2
=
ggd +jogd
Y21 =

gm + ggd +jwgd
Yzz + (b)
=

gds gdb +ju

+ s

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 237

LVT NMOS, VDS=O.8V

50

40

up
10
6al 17 vDs=o.av,
0

Al
L
VG,= 0.3V to 1.2V step 0.075V
9 15 0 0.5 1 1.5
0 10 2030 40 SX8HE
50 VGdV)
Frequency (GHz) Figure 8 Ewtracted transconductance and ouput
5x136 conductance as afunction of V,, before and after de-
,, after de-embedding &, R, and Rd. m
Figure 5 Extracted C
embedding ofRs,R, and %..
LVT NMOS L=0.13pm, N 4 0 . W=4pm
... -
1.70 LVT NMOS: L=0.13pm, W=4pm. N110
vD,=o.av
?i
%
vGS=
0.3V to 1 . 2 ~step 0.075V li
U
50
1 AfterR R,,R,de-embedding

-
\ 5,
e 1.65
U
.-U
w
0
1.60 a
m
c
n
5
0
30
U!
1.55rs' ' " ' ' " " 8
0 10 20 30 40 50 9 20
Frequency (GHz) 0 0.5 1 1.5
VGSW
Figure 6 Extraction of tau (1sfrom the slope of the
measured phase in eqn. (4). Figure 9 Extracted C,, as afunction of V, before and
after de-embedding of &, R, and Rs

LVT NMOS L=O.l3pm, N=10. Wn4prn LVT NMOS: L=0.13pm, W=4pm, N=lO
vDs=o.av
-
25

VI
80 VGs= 1.2V to 0.3V step 0.75 .- Before RS. RD, RGde-embedding
U
'n1 60
U
U 40 ~

\
1 After RS. Ro, R, de-embedding
20r ' ' ' ' ' ' ' ' ' 1 15 " " " " " " "

0 10 20 30 40 50 0 0.5 1 1.5
Frequency (GHz) V,S(V)
Figure 7 Extraction of C, and Cdbafter de-embedding R Figure I O Extracted C
,, as afunction of V, before and
Rzand Rs after de-embedding o f R , R, and R d .

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 O A Before LVT NMOS, Vos=0.8V LVT NMOS: L=0.13pm, N=10
L=0.13pm. W=4pm, N=10

- 75
de-embedding
Measured
- Trendline

+ 45
n

25 R2 0.9948

0 0.5 1 1.5
vGS(V) 0 2 4 6 8 10
Figure I 1 Extracted Cmand C, as afunction of V, before W (brn)
and after de-embedding of Q R, and R, Figure 14 Extracted gate resistance & as a function of
unit gate finger width, W.
LVT NMOS: L=0.13pm, W=4pm. N-1
vDs=o.8v LVT NMOS: L=0.13prn, N=10
z vDs=o.av,v,=o.~v
--2 0.3
Measured
- Trendline

.-
C
Cgd = 4.3128'W + 2.391
e lo
0 1 ' " " ' ' iLLLLuj 0 R2 0.9985
&
c
0 0.5 1 1.5
vGS(v)
0 2 4 6 8 10
(w)
'

Figure I 2 Extracted transconductance delay as afunction W

of V,, before and after de-embedding of Q R, and & Figure 15 Extracted gate-drain capacitance as a function
of unit gatefinger width, CY.

-
LVT NMOS: L=0.13prn, N=10
v,,=o.oiv, v,,=o.av LVT NMOS: L=0.13pm, N=10
vDs=o.8v, vGs=o.av

1
,

i1
Measured &loo I
- Trendline
U Measured
80 Trendline/
Trendline

z
~

U
60
U
Rs = 19.411MI. 0.9593
~

R2 0.9991 y = 9.6817~+ 2.9637

W
0 0.5 1 1.5 2 2.5 9 0
IMI (prn-') 0 2 4 6 8 10
Figure 13 Extracted source series resistance I& as a W (bm)
function of unit gatefinger width, W. Figure 16 Extracted gate-source capacitance as a
function of unit gatefinger width, W

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 239

I
LVT NMOS: W=2ym, N=2 NMOS-LVT: L=0.13pm, N=10, VD,=0.8V
VDs=0.8V, V~sz0.8V

...
100 I I
40 Measured: Symbols
Slmulrtcd Lines
--,----e

iii
.-U
m
0 10 Cgd =4.0371*L+ 1.8346
U R2= 0.9922
..A....
yi. &.........'A 20
0
0
0 0.2 0.4 0.6 0.8 1
L (pm) 0.2 0.4 0.6 0.8 1 1.2
VG, (V)
Figure 17 Extracted C,, and C,,as afunclion of unit gate
length, L. Figure 20 Measured vs. simulated g, as afunction of V,,
and unit gatefinger width, W
NMOS-LVT: L=0.13pm, N=10, Vos=0.8V
100 L V l NMOS: L=0.13bm, N=lO
Measured: Symbols
Simulated: Liner vDs=o. I
Measured: Symbols
Simulated: Lines

-
0 " " ' " ' " " " "
0.2 0.4 0.6
v,, (VI
0.8

Figure 18 Measured vs. simulated C,, as afunction of V,

and unit gatefinger width, W
1 1.2

0.1
H,- 1
Drain Current (mA)
,,
.--.
*+
10
WO.5pm
W2pm
HW 4 p m
w.8 prn
, , , ,

100

Figure 21 Measured vs. simulatedf, as afunction oftDs

and unit gatefinger width, W.
NMOS-LVT: L=0.13pm, N=10, VDs=0.8V
50
1 Measured: Symbols
LVT NMOS: L=0.13pm, N=10, VDS=O.8V

i Simulated: Liner
Measured: Symbols
Simulated: Lines

· B

0
0.2 0.4 0.6 0.8 1 1.2 40 0.0 =
v, (v) 0
Figure 19 Measuredvs. simulated C,, as afunction of&
and unit gatefinger width, W. Figure 22 Measured vs. simulatedpeakf, f- and g,J
(Nw) as afunction of unit gatefinger width, W

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 240
SI :

521 :
20

80
***
Q 60
E meas: Lines& symbols
0
v
dins: dashed lines 5 I Measured: Symbols
340 I Simulated: Lines

0 5 10 15 20
Frequency (GHz)
Figure 26 Measured vs. simulated (using logic and RF-
models) single-ended gain vs. frequency characteristics of
02 0.4 0.6 OS 1.0 12 driver tesf structure.
'GS
Figure 23 Measured vs. simulatedfr as afunction of V ,for
0.13-p m n-MOSFETs with 1 0 x 4 m ~ gatefingers.

80 -

60-
9 ineds: Lines& symbols
X siins: dashed lines
U 2 40: 0 5 10 15 20
Frequency (GHz)
Figure 27 Measured gain of 3-cell and 5-cell driver lest
20 - structures after redesign using the RF scalable model.

11 v
vDs=0.8

'GS
Figure 24 Measured vs. simulated f i as afunction of V,,
for 0.13-p m n-MOSFETs with 1 0 x 4 ~m gatefingers.

de D
Figure 25 Schematics of broadbaid driver test structure
with three inductively-peaked gain cells, 5M2 output Figure 28 Measured IO-Gb/s eye of 3-cell driver test
stage, and source-follower input. structure with 50-mVpp input signal

F
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