APW8722A

APW8722/A/B/C/D
5V to 12V Single Buck Voltage Mode PWM Controller
Features General Description

• Wide 5V to 12V Supply Voltage The APW8722 is a voltage mode, fixed 200kHz/300kHz/
• Power-On-Reset Monitoring on VCC 600kHz switching frequency, synchronous buck converter.
• Excellent Output Voltage Regulations The APW8722 allows wide input voltage that is either a
- 0.6V Internal Reference for APW8722/A/D single 5~12V or two supply voltage(s) for various
- 0.8V Internal Reference for APW8722B/C applications. A power-on-reset (POR) circuit monitors the
- ±0.6% Over-Temperature Range VCC supply voltage to prevent wrong logic controls. A built-
• Integrated Soft-Start in soft-start circuit prevents the output voltages from over-
shoot as well as limits the input current. An internal 0.6V
• Voltage Mode PWM Operation with External
temperature-compensated reference voltage with high
Compensation
accuracy is designed to meet the requirement of low out-
• Up to 90% Duty Ratio for Fast Transient Response
put voltage applications. The APW8722 provides excel-
• Constant Switching Frequency lent output voltage regulations against load current
- 300kHz ±10% for APW8722/B variation.
- 200kHz ±10% for APW8722C The controller’s over-current protection monitors the out-
- 600kHz ±10% for APW8722A/D put current by using the voltage drop across the RDS
• Integrated Bootstrap Forward P-CH MOSFET (ON) of low-side MOSFET, eliminating the need for a cur-
• 50% Under-Voltage Protection rent sensing resistor that features high efficiency and
• 125% Over-Voltage Protection low cost. In addition, the APW8722 also integrates excel-
lent protection functions. The over-voltage protection (OVP)
• Adjustable Over-Current Protection Threshold
, under-voltage protection (UVP). OVP circuit which moni-
- Using the RDS(ON) of Low-Side MOSFET
tors the FB voltage to prevent the PWM output from over
• Shutdown Control by COMP
voltage, and UVP circuit which monitors the FB voltage to
• SOP-8P Package prevent the PWM output from under voltage or short circuit.
• Lead Free and Green Devices Available The APW8722 is available in SOP-8P packages
(RoHS Compliant)
Applications
• Graphic Cards
• DSL, Switch HUB
• Wireless Lan
• Notebook Computer
• Mother Board
• LCD Monitor/TV
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Rev. A.3 - Jun., 2013
Free Datasheet http://www.datasheet4u.com/

APW8722/A/B/C/D
Simplified Application Circuit
VVCC
VIN
5 1
BOOT
VCC
7 2
COMP UGATE
OFF
ON APW8722 VOUT
8
PHASE
4
LGATE
6
FB
GND
3
Ordering and Marking Information

APW8722/A/B/C/D Package Code
KA : SOP-8P
Assembly Material Operating Ambient Temperature Range
I : -40 to 85 oC
Handling Code
Handling Code
Temperature Range TR : Tape & Reel
Package Code Assembly Material
G : Halogen and Lead Free Device
APW8722X
APW8722/A/B/C/D KA : XXXXX X A/B/C/D XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
APW8722/B/C/D APW8722A
BOOT 1 8 PHASE BOOT 1 8 PHASE

UGATE 2 7 COMP UGATE 2 7 COMP
GND 3 9 GND 6 FB OCSET 3 9 GND 6 FB
LGATE/OCSET 4 5 VCC LGATE 4 5 VCC
SOP-8P SOP-8P
(top view) (top view)

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Absolute Maximum Ratings (Note 1)

Symbol Parameter Rating Unit
VVCC VCC Supply Voltage (VCC to GND) -0.3 ~ 16 V
BOOT Supply Voltage (BOOT to PHASE) -0.3 ~ 16 V
VBOOT
BOOT Supply Voltage (BOOT to GND) -0.3 ~ 32 V
> 20ns -0.3 ~ VBOOT+0.3 V
VUGATE UGATE Voltage (UGATE to PHASE)
< 20ns -5 ~ VBOOT+5 V
> 20ns -0.3 ~ VVCC+0.3 V
VLGATE LGATE Voltage (LGATE to GND)
< 20ns -5 ~ VVCC+5 V
> 20ns -0.3 ~ 16 V
VPHASE PHASE Voltage (PHASE to GND)
< 20ns -5 ~ 25 V
FB ,COMP to GND -0.3 ~ 7 V
POK to GND -0.3~VCC+0.3 V
TJ Maximum Junction Temperature 150 °C
TSTG Storage Temperature -65 ~ 150 °C
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 °C
Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are
stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recom-
mended operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
Thermal Characteristics
Symbol Parameter Typical Value Unit
(Note 2)
Thermal Resistance -Junction to Ambient
θJA °C/W
SOP-8P 60
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions (Note 3)

Symbol Parameter Range Unit
VVCC VCC Supply Voltage (VCC to GND) 4.5 ~ 13.2 V
Converter Output Voltage for APW8722/A/D 0.6 ~ 5 V
VOUT
Converter Output Voltage for APW8722B/C 0.8 ~ 5 V
VIN Converter Input Voltage 3~13.2 V
IOUT Converter Output Current 0 ~ 25 A
TA Ambient Temperature -40 ~ 85 °C
TJ Junction Temperature -40 ~ 125 °C
Note 3: Refer to the application circuit for further information.

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Electrical Characteristics
Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -40°C to 85°C, unless otherwise
noted. Typical values are at TA = 25°C.
APW8722
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
INPUT SUPPLY VOLTAGE AND CURRENT
UGATE and LGATE open;
VCC Supply Current (Shutdown Mode) - - 550 µA
IVCC COMP=GND
VCC Supply Current UGATE and LGATE open - 2.5 10 mA
POWER-ON-RESET(POR)
Rising VCC POR Threshold 3.8 4.1 4.4 V
VCC POR Hysteresis 0.3 0.5 0.6 V
OSCILLATOR
For APW8722/B 270 300 330
FOSC Oscillator Frequency For APW8722C 180 200 220 kHz
For APW8722A/D 540 600 660
∆VOSC
(Note 4)
Oscillator Sawtooth Amplitude (1.2V~2.7V typical) - 1.5 - V
DMAX Maximum Duty Cycle - - 90 %
REFERENCE
APW8722/A/D Reference Voltage TA = -40 ~ 85°C 0.596 0.6 0.604
VREF V
APW8722B/C Reference Voltage TA = -40 ~ 85°C 0.795 0.8 0.805
ERROR AMPLIFIER
Open-Loop GAIN (Note 4) RL = 10kΩ, CL = 10pF - 90 - dB
Open-Loop Bandwidth (Note 4) RL = 10kΩ, CL = 10pF - 20 - MHz
FB Input Leakage Current VFB = 0.6V - - 0.1 µA
GATE DRIVERS
High-side Gate Driver Source Current VBOOT= 12V, VUGATE-PHASE = 6V - 1.0 -
High-side Gate Driver Sink Current VBOOT= 12V, VUGATE-PHASE = 6V - 1.1 -
Low-side Gate Driver Source Current VVCC = 12V, VLGATE-GND = 6V - 1.8 - A
Low-side Gate Driver Sink Current VVCC = 12V, VLGATE-GND = 6V - 2.0 -

TD Dead-time (Note 4) - 30 - ns
PROTECTIONS
VFB_UV FB Under-Voltage Protection Trip Point Percentage of VREF 45 50 55 %
Under-Voltage Debounce Interval - 2 - µs
Under-Voltage Protection Enable
- 1.5 - ms
Delay
FB Over-Voltage Protection Rising
VFB_OV VFB rising 120 125 130 %
Threshold
FB Over-Voltage Protection Falling
VFB falling 100 105 110 %
Threshold
Over-Voltage Debounce Interval - 2 - µs
VOCP_MAX Built-in Maximum OCP Voltage - 1200 - mV
IOCSET OCSET Current Source 9 10 11 µA

Rev. A.3 - Jun., 2013
FreeDatasheethttp://www.datasheet4u.com/
APW8722/A/B/C/D
Electrical Characteristics (Cont.)

Refer to the typical application circuit. These specifications apply over VVCC = 12V, TA = -40°C to 85°C, unless otherwise
noted. Typical values are at TA = 25°C.
APW8722
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
SOFT-START
VDISABLE Shutdown Threshold of VCOMP - - 0.4 V
TSS Internal Soft-Start Interval (Note 4) - 1.5 - ms
Note 4: Guaranteed by design, not production tested.

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Typical Operating Characteristics

Reference Voltage vs. Junction Efficiency vs. Load Current
Temperature FSW=300KHz, VOUT=1.2V
0.61
VCC = 12V
90
Reference Voltage (V)
0.605
85
Efficiency (%)
80
0.6
75
70
0.595
65
0.59 60
-20 0 20 40 60 80 100 120 0.1 1 10.0 20.0
Junction Temperature (oC) Output Current (A)
Switching Frequency vs. Junction Switching Frequency vs. Junction

Temperature Temperature
350 650
340 640
Switching Frequency (kHz)
330
Switching Frequency (kHz)
630
320 620
310 610
300 600
290 590
280 580
270 570
260 560
250 550
-20 0 20 40 60 80 100 120 -20 0 20 40 60 80 100 120
o
Junction Temperature ( C) Junction Temperature (oC)
Load Regulation IOCSET vs. Junction Temperature
0.3 11.4
0.2 11
Output Voltage Variation (%)
OCSET Current Source (uA)
10.6
0.1
10.2
0
9.8
-0.1
9.2
-0.2
8.8
-0.3 8.2
0 2 4 6 8 10 -20 0 20 40 60 80 100 120
Output Current (A) Junction Temperature (oC)

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Operating Waveforms
Refer to the typical application circuit. The test condition is VIN=12V, TA= 25oC unless otherwise specified.
Power On Power Off
Enable Shutdown

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Operating Waveforms
Over-Current Protection Under-Voltage Protection
UGATE Rising UGATE Falling

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Operating Waveforms
Load Transient

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Pin Description
PIN
No. Function Description
Name
APW8722A APW8722/B/C/D
This pin provides the bootstrap voltage to the high-side gate driver for
driving the N-channel MOSFET. An external capacitor from PHASE to
1 1 BOOT
BOOT, an internal switch generates the bootstrap voltage for the
high-side gate driver (UGATE).
High-side Gate Driver Output. This pin is the gate driver for high-side
2 2 UGATE
MOSFET.
- 3 GND Signal and Power ground. Connecting this pin to system ground.
Current-Limit Threshold Setting Pin. There is an internal source current
10uA through a resistor from OCSET pin to GND. This pin is used to
3 - OCSET
monitor the voltage drop across the Drain and Source of the low-side
MOSFET for current-limit
Output of The Low-side MOSFET Driver. Connect this pin to the low-side
4 - LGATE
MOSFET.
Low-side Gate Driver Output and Over-Current Setting Input. This pin is
LGATE/ the gate driver for low-side MOSFET. It also used to set the maximum
- 4
OCSET
inductor current. Refer to the section in “Function Description” for detail.
Power Supply Input. Connect a nominal 5V to 12V power supply voltage
to this pin. A power-on reset function monitors the input voltage at this
5 5 VCC
pin. It is recommended that a decoupling capacitor (1 to 10µF) be
connected to GND for noise decoupling.
Feedback Input of Converter. The converter senses feedback voltage via
6 6 FB FB and regulates the FB voltage at 0.6V/0.8V. Connecting FB with a
resistor-divider from the output sets the output voltage of the converter.
This is a multiplexed pin. During soft-start and normal converter
operation, this pin represents the output of the error amplifier. It is used to
compensate the regulation control loop in combination with the FB pin.
7 7 COMP Pulling COMP low (VDISABLE = 0.4V max.) will shut down the controller.
When the pull-down device is released, the COMP pin will start to rise.
When the COMP pin rises above the VDISABLE trip point, the APW8722 will
begin a new initialization and soft-start cycle.
This pin is the return path for the high-side gate driver. Connecting this
pin to the high-side MOSFET source and connect a capacitor to BOOT
8 8 PHASE
for the bootstrap voltage. This pin is also used to monitor the voltage drop
across the low-side MOSFET for over-current protection.
9 9 Thermal Pad. Connect this pad to the system ground plan for
GND
(Exposed Pad) (Exposed Pad) good thermal conductivity.

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Block Diagram
VCC
IOCSET Power-On
Regulator Sample BOOT
(10 µA typical) Reset
and Hold
Sense Low
Side UGATE
V REF VROCSET
To
(0 .6V /0.8V typical)
LGATE
PHASE
UVP VROCSET
0.5 Comparator Soft Start
and IZCMP
Fault Logic
VCC
OVP Inhibit
Comparator Gate
1.25 Control LGATE
Soft-start
Error Amplifier PWM

Comparator
VREF
Oscillator
0 .4V
Disable
FB COMP GND

Rev. A.3 - Jun., 2013
Free Datasheet http://www.datasheet4u.com

APW8722/A/B/C/D
Typical Application Circuit

For APW8722/B/C/D
VCC Supply
(5~12V) VIN
R4 C IN1 C IN2
C4
2R2
1µF 1 C3 1µF 220µF x 2
5 BOOT
VCC 0.1µF
2 Q1
7 UGATE
OFF COMP APM 2510
ON C1 C2 APW8722 L1 VOUT
100pF 8
Q3 100nF PHASE
0.5µH
2N7002 R2
4.7kΩ LGATE/ 4 Q2 C OUT
6 OCSET APM 2556
FB 1000 µF x 2
R OCSET
GND
3
R1
R2 1kΩ
1kΩ
C3 R3
22 nF 1kΩ
For APW8722A
VCC Supply
(5~12V) VIN
R4 APW8722(SOP-8OP) C IN1 C IN2
C4
2R2
1 µF 1 C3 1µF 220µF x 2
5 BOOT
VCC 0.1µF
Q1
7 2
COMP UGATE APM 251
OFF 0
ON C1 C2 L1 VOUT
100pF 8
Q3 100nF PHASE
0.5µH
2N7002 R2 Q2
4.7kΩ
LGATE 4 APM 255
C OUT
6 6 1000µF x 2
FB
OCSET
3
R OCSET
R3 R1
1kΩ 1kΩ
C3 R3
22nF 1kΩ

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Function Description
Power-On-Reset (POR) A resistor (ROCSET), connected from the LGATE/OCSET to
GND, programs the over-current trip level. Before the IC
The Power-On-Reset (POR) function of APW8722 con-
initiates a soft-start process, an internal current source,
tinually monitors the input supply voltage (VCC) and en-
IOCSET (10µA typical), flowing through the ROCSET develops
sures that the IC has sufficient supply voltage and can
a voltage (VROCSET) across the ROCSET. The device holds
work well. The POR function initiates a soft-start process
VROCSET and stops the current source IOCSET during normal
while the VCC voltage just exceeds the POR threshold;
operation. When the voltage across the low-side MOSFET
the POR function also inhibits the operations of the IC
exceeds the VROCSET, the APW8722 turns off the high-side
while the VCC voltage falls below the POR threshold.
and low-side MOSFET,and the device will enters hiccup
Soft-Start mode until the over-current phenomenon is released.
The APW8722 builds in a soft-start function about 1.5ms For avoid large inductor current occurring in short circuit
(Typ.) interval, which controls the output voltage rising as before power on, the controller reduces internal current
well as limiting the current surge at the start-up. During source, Iocset, to half during soft start time. It means that
soft-start, an internal ramp voltage connected to the one when APW8722 is in soft start interval, the internal cur-
of the positive inputs of the error amplifier replaces the rent source, Iocset, is only 5µA (typical).
reference voltage (0.6V typical) until the ramp voltage The APW8722 has an internal OCP voltage, VOCP_MAX, and
reaches the reference voltage. The soft-start circuit inter- the value is 1.2V (typical). When the ROCSET x IOCSET exceed
val is shown as figure 1. 1.2V or the ROCSET is floating or not connected, the VROCSET
will be the default value 1.2V. The over current threshold
Voltage(V) would be 1.2V across low-side MOSFET. The threshold
POK Delay Time of the valley inductor current-limit is therefore given by:
VVCC
OCSET count completed
OCSET count start
(OCSET duratiom, t2-t1, less than 0.9ms) 2 × IOCSET × ROCSET
VPOK ILIMIT =
RDS(ON) (low − side)
0.9xVREF
VOUT
For the over-current is never occurred in the normal oper-
ating load range, the variation of all parameters in the
above equation should be considered:
t0 t1 t2 t3 t4
Time - The RDS(ON) of low-side MOSFET is varied by tempera-
ture and gate to source voltage. Users should deter-
Figure 1. Soft-Start Interval mine the maximum RDS(ON) by using the manufacturer’s
datasheet.
Over-Current Protection of the PWM Converter - The minimum IOCSET (9µA) and minimum ROCSET should
The over-current function protects the switching converter be used in the above equation.
against over-current or short-circuit conditions. The con- - Note that the ILIMIT is the current flow through the low-
troller senses the inductor current by detecting the drain- side MOSFET; ILIMIT must be greater than valley inductor
to-source voltage which is the product of the inductor’s current which is output current minus the half of induc-
current and the on-resistance of the low-side MOSFET tor ripple current.
during it’s on-state. This method enhances the converter’s
∆I
efficiency and reduces cost by eliminating a current sens- ILIMIT > IOUT(MAX ) −
2
ing resistor required. Where ∆I = output inductor ripple current
- The overshoot and transient peak current also should
be considered.

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Function Description (Cont.)

Adaptive Shoot-Through Protection of the PWM Con-
Under-Voltage Protection
verter
The under-voltage function monitors the voltage on FB The gate drivers incorporate an adaptive shoot-through
(VFB) by Under-Voltage (UV) comparator to protect the PWM protection to prevent high-side and low-side MOSFETs
converter against short-circuit conditions. When the VFB from conducting simultaneously and shorting the input
falls below the falling UVP threshold (50% VREF), a fault supply. This is accomplished by ensuring the falling gate
signal is internally generated and the device turns off high- has turned off one MOSFET before the other is allowed to
side and low-side MOSFETs. The device will enters hic- rise.
cup mode until the under-voltage phenomenon is During turn-off the low-side MOSFET, the LGATE voltage
released. is monitored until it is below 1.5V threshold, at which
time the UGATE is released to rise after a constant delay.
Over-Voltage Protection (OVP) of the PWM Converter During turn-off of the high-side MOSFET, the UGATE-to-
PHASE voltage is also monitored until it is below 1.5V
The over-voltage protection monitors the FB voltage to
threshold, at which time the LGATE is released to rise
prevent the output from over-voltage condition. When the
after a constant delay.
output voltage rises above 125% of the nominal output
voltage, the APW8722 turns off the high-side MOSFET
and turns on the low-side MOSFET until the output volt-
age falls below the falling below 105%, the OVP com-
parator is disengaged and both high-side and low-side
drivers turn off.
This OVP scheme only clamps the voltage overshoot and
does not invert the output voltage when otherwise acti-
vated with a continuously high output from low-side
MOSFET driver. It’s a common problem for OVP schemes
with a latch. Once an over-voltage fault condition is set, it
can be reset by releasing COMP or toggling VCC power-
on-reset signal.
Shutdown and Enable
The APW8722 can be shut down or enabled by pulling

low the voltage on COMP. The COMP is a dual-function
pin. During normal operation, this pin represents the out-
put of the error amplifier. It is used to compensate the
regulation control loop in combination with the FB pin.
Pulling the COMP low (VDISABLE = 0.4V maximum) places
the controller into shutdown mode which UGATE and
LGATE are pulled to PHASE and GND respectively.
When the pull-down device is released, the COMP volt-
age will start to rise. When the COMP voltage rises above
the VDISABLE threshold, the APW8722 will begin a new ini-
tialization and soft-start process.

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Application Information
Output Voltage Selection lower output ripple voltage. The ripple current and ripple
The output voltage can be programmed with a resistive voltage can be approximated by:
VIN − VOUT VOUT
divider. Use 1% or better resistors for the resistive divider IRIPPLE = ×
FSW × L VIN
is recommended. The FB pin is the inverter input of the
error amplifier, and the reference voltage is 0.6V. The where Fs is the switching frequency of the regulator.
output voltage is determined by: ∆VOUT = IRIPPLE x ESR
 R  A tradeoff exists between the inductor’s ripple current and
VOUT = 0.6 × 1 + 1 
 R 2 the regulator load transient response time. A smaller in-
Where R1 is the resistor connected from VOUT to FB and ductor will give the regulator a faster load transient re-
R2 is the resistor connected from FB to the GND. sponse at the expense of higher ripple current and vice
versa. The maximum ripple current occurs at the maxi-
Output Capacitor Selection mum input voltage. A good starting point is to choose the
The selection of COUT is determined by the required effec- ripple current to be approximately 30% of the maximum
tive series resistance (ESR) and voltage rating rather than output current.
the actual capacitance requirement. Therefore, selecting Once the inductance value has been chosen, selecting
high performance low ESR capacitors is intended for an inductor is capable of carrying the required peak cur-
switching regulator applications. In some applications, rent without going into saturation. In some types of
multiple capacitors have to be paralleled to achieve the inductors, especially core that is make of ferrite, the ripple
desired ESR value. If tantalum capacitors are used, make current will increase abruptly when it saturates. This will
sure they are surge tested by the manufactures. If in doubt, result in a larger output ripple voltage.
consult the capacitors manufacturer.
PWM Compensation
Input Capacitor Selection
The output LC filter of a step down converter introduces a
The input capacitor is chosen based on the voltage rat-
double pole, which contributes with -40dB/decade gain
ing and the RMS current rating. For reliable operation,
slope and 180 degrees phase shift in the control loop. A
select the capacitor voltage rating to be at least 1.3 times
compensation network among COMP, FB, and V OUT
higher than the maximum input voltage. The maximum
should be added. The compensation network is shown in
RMS current rating requirement is approximately IOUT/2
Figure 5. The output LC filter consists of the output induc-
where IOUT is the load current. During power up, the input
tor and output capacitors. The transfer function of the LC
capacitors have to handle large amount of surge current.
filter is given by:
If tantalum capacitors are used, make sure they are surge
1
tested by the manufactures. If in doubt, consult the ca- FESR =
2 × π × ESR × COUT
pacitors manufacturer.
For high frequency decoupling, a ceramic capacitor be- The FLC is the double poles of the LC filter, and FESR is the
tween 0.1µF to 1µF can connect between VCC and ground zero introduced by the ESR of the output capacitor.
pin. V PHASE L V OUT
Inductor Selection
C OUT
The inductance of the inductor is determined by the out-
put voltage requirement. The larger the inductance, the
ESR
lower the inductor’s current ripple. This will translate into
Figure 2. The Output LC Filter

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Application Information(Cont.)
The poles and zeros of the transfer function are:
1
FLC FZ1 =
2 × π × R2 × C2
-40dB/dec 1
FZ2 =
2 × π × (R1 + R3) × C3
1
FP1 =
GAIN (dB)
 C1× C2 
2 × π × R2 ×  
FESR  C1 + C2 
1
FP2 =
-20dB/dec 2 × π × R3 × C3
C1
R3 C3 R2 C2
V OUT
Frequency(Hz)
R1 FB V COMP
Figure 3. The LC Filter GAIN and Frequency
V REF
The PWM modulator is shown in Figure 4. The input is Figure 5. Compensation Network
the output of the error amplifier and the output is the
PHASE node. The transfer function of the PWM modulator The closed loop gain of the converter can be written as:
is given by:
GAINLC X GAINPWM X GAINAMP
VIN
GAINPWM =
∆VOSC Figure 6. shows the asymptotic plot of the closed loop
V IN converter gain, and the following guidelines will help to
Driver design the compensation network. Using the below
OSC
PWM guidelines should give a compensation similar to the
V OSC Comparator curve plotted. A stable closed loop has a -20dB/ decade
Output of
PHASE slope and a phase margin greater than 45 degree.
Error Amplifier 1. Choose a value for R1, usually between 1K and 5K.
Driver 2. Select the desired zero crossover frequency

FO: (1/5 ~ 1/10) X FS >FO>FESR
Figure 4. The PWM Modulator
Use the following equation to calculate R2:
The compensation network is shown in Figure 5. It ∆VOSC FO
R2 = × × R1
provides a close loop transfer function with the highest VIN FLC
zero crossover frequency and sufficient phase margin. 3. Place the first zero FZ1 before the output LC filter double
The transfer function of error amplifier is given by: pole frequency FLC.
1  1 
//  R2 +  FZ1 = 0.75 X FLC
VCOMP sC1  sC2 
GAINAMP = =
VOUT  1  Calculate the C2 by the equation:
R1//  R3 + 
 sC3  1
C2 =
2 × π × R2 × FLC × 0.75
 1   1 
s + ×s + 
=
R1 + R3
×
 R2 × C2   (R1 + R3) × C3 
R1× R3 × C1  C1 + C2   1 
s s + × s + 
 R2 × C1× C2   R3 × C3 

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Application Information(Cont.)
MOSFET Selection
4. Set the pole at the ESR zero frequency FESR:
The selection of the N-channel power MOSFETs is deter-
FP1 = FESR mined by the RDS(ON), reverse transfer capacitance (CRSS),
Calculate the C1 by the equation: and maximum output current requirement.The losses in
C2 the MOSFETs have two components: conduction loss and
C1 =
2 × π × R2 × C2 × FESR − 1 transition loss. For the upper and lower MOSFET, the
5. Set the second pole FP2 at the half of the switching losses are approximately given by the following equations:
frequency and also set the second zero FZ2 at the output LC PUPPER = IOUT2 (1+ TC)(RDS(ON))D + (0.5)(Iout)(VIN)(tsw)FSW
filter double pole FLC. The compensation gain should not
PLOWER = IOUT2 (1+ TC)(RDS(ON))(1-D)
exceed the error amplifier open loop gain, check the
compensation gain at FP2 with the capabilities of the error
amplifier. where IOUT is the load current
TC is the temperature dependency of RDS(ON)
FP2 = 0.5 X FS
FSW is the switching frequency
FZ2 = FLC tsw is the switching interval
Combine the two equations will get the following component D is the duty cycle
calculations: Note that both MOSFETs have conduction losses while
1 + s × ESR × COUT the upper MOSFET includes an additional transition loss.
GAINLC = 2
s × L × COUT + s × ESR × COUT + 1 The switching internal, tsw, is the function of the reverse
transfer capacitance CRSS. Figure 7 illustrates the switch-
The poles and zero of this transfer functions are:
ing waveform internal of the MOSFET.
1
FLC = The (1+TC) term factors in the temperature dependency
2 × π × L × COUT
of the RDS(ON) and can be extracted from the “RDS(ON) vs Tem-
R1
R3 = perature” curve of the power MOSFET.
FS
−1
2 × FLC VDS
1
C3 =
π × R3 × FS
drain and source of MOSFET
Voltage across
FZ1 FZ2 FP1 FP2

GAIN (dB)
20log Compensation
(R2/R1) Gain
20log
(VIN/ VOSC)
tsw Time
FLC
FESR Converter Figure 7. Switching Waveform Across MOSFET
Gain
PWM & Filter
Gain
Frequency(Hz)
Figure 6. Converter Gain and Frequency

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Application Information (Cont.)

Layout Consideration
In any high switching frequency converter, a correct lay- - The drain of the MOSFETs (VIN and PHASE nodes) should
out is important to ensure proper operation of the be a large plane for heat sinking.
regulator. With power devices switching at 300kHz,the - The ROCSET resistance should be placed near the IC as
resulting current transient will cause voltage spike across close as possible.
the interconnecting impedance and parasitic circuit
elements. As an example, consider the turn-off transition
of the PWM MOSFET. Before turn-off, the MOSFET is car- APW8722
VIN
rying the full load current. During turn-off, current stops
flowing in the MOSFET and is free-wheeling by the lower VCC
MOSFET and parasitic diode. Any parasitic inductance of
the circuit generates a large voltage spike during the BOOT
switching interval. In general, using short and wide printed L

O
circuit traces should minimize interconnecting imped UGATE A
D
ances and the magnitude of voltage spike. And signal PHASE
and power grounds are to be kept separate till combined ROCSET
LGATE VOUT
using ground plane construction or single point
grounding. Figure 8. illustrates the layout, with bold lines
indicating high current paths; these traces must be short Close to IC
and wide. Components along the bold lines should be Figure 8. Layout Guidelines
placed lose together. Below is a checklist for your layout:
- Keep the switching nodes (UGATE, LGATE, and PHASE)
away from sensitive small signal nodes since these
nodes are fast moving signals. Therefore, keep traces
to these nodes as short as possible.
- The traces from the gate drivers to the MOSFETs (UG
and LG) should be short and wide.
- Place the source of the high-side MOSFET and the drain
of the low-side MOSFET as close as possible. Minimiz-
ing the impedance with wide layout plane between the
two pads reduces the voltage bounce of the node.
- Decoupling capacitor, compensation component, the
resistor dividers, and boot capacitors should be close
their pins. (For example, place the decoupling ceramic
capacitor near the drain of the high-side MOSFET as
close as possible. The bulk capacitors are also placed
near the drain).
- The input capacitor should be near the drain of the up-
per MOSFET; the output capacitor should be near the
loads. The input capacitor GND should be close to the
output capacitor GND and the lower MOSFET GND.

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Package Information
SOP-8P
-T- SEATING PLANE < 4 mils
SEE VIEW A
D1
E2
THERMAL
E1
E
PAD
h X 45o
e b c
A2
0.25
A1
NX
aaa c GAUGE PLANE
SEATING PLANE
L
VIEW A
S SOP-8P
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 1.60 0.063
A1 0.00 0.15 0.000 0.006
A2 1.25 0.049
b 0.31 0.51 0.012 0.020
c 0.17 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
D1 2.50 3.50 0.098 0.138
E 5.80 6.20 0.228 0.244
E1 3.80 4.00 0.150 0.157
E2 2.00 3.00 0.079 0.118
e 1.27 BSC 0.050 BSC
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050
° 0oC 8oC 0oC 8oC
aaa 0.10 0.004
Note : 1. Followed from JEDEC MS-012 BA.

2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A
E1
F
W
B0
K0 A0 OD1 B A
B
SECTION A-A
T
SECTION B-B
d
H
A
T1
Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0 2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0 0.30 1.75 0.10 5.5 0.05
-0.00 -0.20
SOP-8P P0 P1 P2 D0 D1 T A0 B0 K0
4.0 0.10 8.0 0.10 2.0 0.05 1.5+0.10 1.5 MIN. 0.6+0.00 6.40 0.20 5.20 0.20 2.10 0.20
-0.00 -0.40
(mm)
Devices Per Unit

Package Type Unit Quantity
SOP-8P Tape & Reel 2500

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Taping Direction Information

SOP-8
USER DIRECTION OF FEED
Classification Profile

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
100 °C 150 °C
Temperature min (Tsmin)
150 °C 200 °C
Temperature max (Tsmax)
60-120 seconds 60-120 seconds
Time (Tsmin to Tsmax) (ts)
Average ramp-up rate

3 °C/second max. 3 °C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature
See Classification Temp in table 1 See Classification Temp in table 2
(Tp)*
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max.
Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

3 3
Package Volume mm Volume mm
Thickness <350 ≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
3 3 3
Package Volume mm Volume mm Volume mm
Thickness <350 350-2000 >2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C
Reliability Test Program

Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM 2KV
MM JESD-22, A115 VMM 200V
Latch-Up JESD 78 10ms, 1tr 100mA

Rev. A.3 - Jun., 2013

APW8722/A/B/C/D
Customer Service
Anpec Electronics Corp.

Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

Rev. A.3 - Jun., 2013

APW8722A

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APW8722/A/B/C/D

5V to 12V Single Buck Voltage Mode PWM Controller

Features General Description

Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Free Datasheet http://www.datasheet4u.com/

Simplified Application Circuit

Ordering and Marking Information

BOOT 1 8 PHASE BOOT 1 8 PHASE

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Absolute Maximum Ratings (Note 1)

Recommended Operating Conditions (Note 3)

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Free Datasheet http://www.datasheet4u.com/

Low-side Gate Driver Sink Current VVCC = 12V, VLGATE-GND = 6V - 2.0 -

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Electrical Characteristics (Cont.)

Note 4: Guaranteed by design, not production tested.

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Typical Operating Characteristics

Switching Frequency vs. Junction Switching Frequency vs. Junction

OCSET Current Source (uA)

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Power On Power Off

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Over-Current Protection Under-Voltage Protection

UGATE Rising UGATE Falling

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Copyright  ANPEC Electronics Corp. 9 www.anpec.com.tw

Free Datasheet http://www.datasheet4u.com/

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Error Amplifier PWM

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Typical Application Circuit

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Function Description (Cont.)

Shutdown and Enable

The APW8722 can be shut down or enabled by pulling

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Figure 2. The Output LC Filter

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Driver 2. Select the desired zero crossover frequency

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FZ1 FZ2 FP1 FP2

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Application Information (Cont.)

switching interval. In general, using short and wide printed L