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SAP-2 Computer Architecture - Final

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39 views62 pages

SAP-2 Computer Architecture - Final

Uploaded by

Mohsin Islam Rifat
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Simple As Possible

Computer
(SAP-2)
Reference: Malvino . Brown
Chapter 11

Nafiz Imtiaz
Lecturer, EEE, AUST
Block Diagram
Comparison between SAP1 & SAP2 Computer
Architecture
SAP1 SAP2

Input block 1 2

Output block 1 2

RAM/Memory Size=16×8 Size=64K×8 [first 2k for ROM, rest


Address->4 bit 64k for RAM]
Data-> 8 bit Address->16 bit
Opcode->4 bit Data-> 8 bit
Opcode->8 bit
Registers 2 (A, B) 4 (A, B, C, Temp)

Flags No Yes

Instructions 4 42
Types of instruction

i. Data Transfer instruction { use for changing the location of data }

ii. Data manipulation Instruction { perform arithmetic, Logical, shift operation}

iii. Programmed control instruction { provide decision making capability}

4
Data Transfer Instruction

Name Mnemonic
Load LD
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP

5
Data Manipulation Instruction

Logical and bit manipulation


Arithmetic Instruction
Name Mnemonic Shift Instruction
Name Mnemonic
Increment INC Clear CLR Name Mnemonic
Decrement DEC Complement COM Logical shift Right SHR
Addition ADD And AND Logical shift left SHL
Subtraction SUB OR OR Rotate right ROR
Multiplication MUL XOR XOR Rotate left ROL
Division DIV XNOR XNOR
Negative NEG

6
Program control Instruction

Name Mnemonic
Jump Jump
Call CALL
skip SKP
SAP2
Instructions
(42)
Mnemonics and Op-code
Mnemonics Op code Mnemonics Op code
ADD B 80H HLT 76H
ADD C 81H IN byte DBH
ANA B A0H INR A 3CH
ANA C A1H INR B 04H
ANI byte E6H INR C 0CH
CALL address CDH JM address FAH
CMA 2FH JMP address C3H
DRC A 3DH JNZ address C2H
DCR B 05H JZ address CAH
DCR C 0DH LDA address 3AH
Mnemonics and Op-code
Mnemonics Op code Mnemonics Op code
MOV A,B 78H ORA C B1H
MOV A,C 79H ORI byte F6H
MOV B,A 47H OUT byte D3H
MOV B,C 41H RAL 17H
MOV C,A 4FH RAR 1FH
MOV C,B 48H RET C9H
MVI A,byte 3EH STA address 32H
MVI B,byte 06H SUB B 90H
MVI C,byte 0EH SUB C 91H
NOP 00H XRA B A8H
ORA B B0H XRA C A9HH
Memory-Reference
Instructions
LDA
STA
MVI
MVI
Problem
Solution Machine Code

Assembly Code
Register
Instructions
MOV
MOV
ADD and SUB
ADD and SUB
INR and DCR
INR and DCR
Problem
Solution Machine Code

Assembly Code
Logic Instructions
CMA

If,
A= 25H or 00100101
Then,
after executing CMA
A=11011010
ANA and ORA
ANA and ORA
ANI
ORI
XRI
JUMP and CALL
Instructions
JMP
JMP
JM, JZ, JNZ
CALL and RET
➢ CALL 5000H : Call the
subroutine starting
from 5000H
➢ RET : return, Have to
return to the address
next to the address
where CALL 5000H
was stored
➢ CALL is
unconditional
CALL and RET
➢ When CALL is
executed, the content
of PC is automatically
saved in memory
locations FFFEH and
HLT FFFFH
➢ Infinite Loop?
Problem
Assembly version
Solution
Problem
Solution
Problem
Solution
Practice Problem
▪ 1 + 2 + 3 + ⋯ … … … … … … … … … … … + 100

▪ 1 + 3 + 5 + ⋯ … … … … … … … … … … … + 101

▪ 100 + 101 + 102 + ⋯ … … … … … … … … … + 200

▪ Load a byte in A register and check is it odd or even? If this value is odd
then move 01H in C register otherwise move 00H.
▪ Perform division operation by SAP-2 instruction and store the remainder in
A register, quotient in C register.
[ for 9/4, final output will be, A=1 and C=2
for 9/3, final output will be, A=0 and C=3]
Other
Instructions
NOP

HLT
IN
OUT
RAR and RAL
Problem
Solution
Calculation of
Execution Time of
a Program
Problem
Solution
Total Time:
Problem
Solution
Inner
Loop

Total
Time
Thank You

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