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HDL Module 3

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kim taehyung
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6 views

HDL Module 3

Uploaded by

kim taehyung
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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X <= a nand b;

end DATAFLOW;
architecture Dataflow of Decoder is
begin

led (3) <= bcd (0) and bcd (1);


led (2) <= bcd (e) and (not bcd(1 ) );
l e d ( 1 ) < = ( n o t b c d ( 0 ) ) a n d b c d (1);
led (0) <= (not bcd (0)) and (not
b c d (1) );
end Dataflow;
architecture dataflow of Half-adder is
begi n
sum <= A XOR B;
carry <= A AND B;
end dataflow;
a r c h i te ct ure b e h a v io ra l o f D e c o d er i s
signal S: bit_vector (3 downto 0);
begin

P1: process (bcd, S)


begin

case bcd is
when "00" => S <= "0001"

when "01" => S <= "0010"

when "10" => S <= "0100"

when "11" => S <= "1000"

end case;
led <= S;

end process P1;


end behavioral;
begin
process (A, B)
begin
if (A = '1') and (B = '1') then Z <= '0';
Z <= '1';
else

end if;
end process;
end behave;
(1) Scalar types (values of these types have no elements),
(2) Composite types (values of these types consist of element values),
(3) Access types (provide access to objects of a given type)
(4) Files (provide access to objects that contain a sequence of values of a
given type)
(5) Array Types
(6) Record Types
(7) Predefined VHDL Data Types
(8) Unsupported Data Types
(9) Subtypes
(10) Physical Type
Scalar type is a type whose values have no elements. The scalar type values
cannot contain any composite elements. The Syntax of Scalar Type is :
An object of a composite type is a collection of other objects, called
elements. The Syntax of Composite type is,
Access type allows to manipulate data, which are created dynamically
during simulation.The syntax of access type is :
The array is a composite object, which elements are of the same
subtype. The Syntax of Array Type is,
A physical type allows defining measurement units for some physical quantity, like
length, time, pressure, capacity, etc. The Syntax of Physical Type is :
Subtype declarations are used to define subsets of a type. The Syntax of Subtype is :
VHDL describes specific packages which contain standard set of types and operations.

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