Department of Electrical Engineering SEECS,

NUST

EE 421: Digital System Design

Spring 2024

MEGA ASSIGNMENT

Name CMS

Muhammad Hamza 372191

Muhammad Mustafa 378915

TASK NO 1: PLOTTING SIMPLE PIXCELS ON THE SCREEN
VERILOG CODE:
module vga(CLOCK_50, SW, KEY,VGA_R, VGA_G, VGA_B,VGA_HS, VGA_VS, VGA_BLANK_N, VGA_SYNC_N,
VGA_CLK);

input CLOCK_50;

input [9:0] SW;

input [1:0] KEY;

output [9:0] VGA_R;

output [9:0] VGA_G;

output [9:0] VGA_B;

output VGA_HS;

output VGA_VS;

output VGA_BLANK_N;

output VGA_SYNC_N;

output VGA_CLK;

wire [2:0] colour;

wire [7:0] x;

wire [6:0] y;

assign colour = 3'b111;

assign x = {3'd0, SW[9:5]};

assign y = {2'd0, SW[4:0]};

vga_adapter VGA(.resetn(KEY[0]),.clock(CLOCK_50),.colour(colour),.x(x),.y(y),.plot(~(KEY[1])),

.VGA_R(VGA_R),.VGA_G(VGA_G),.VGA_B(VGA_B),.VGA_HS(VGA_HS),.VGA_VS(VGA_VS),

.VGA_BLANK(VGA_BLANK_N),.VGA_SYNC(VGA_SYNC_N),.VGA_CLK(VGA_CLK));

defparam VGA.RESOLUTION = "160x120";

defparam VGA.MONOCHROME = "FALSE";

defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;

defparam VGA.BACKGROUND_IMAGE = "image.colour.mif";

defparam VGA.USING_DE1 = "TRUE";

endmodule
OUTPUT ON SCREEN:

Task 2: Fill the Screen

You will create a new component that interfaces with the VGA Adaptor Core. It will contain a
simple FSM to fill the screen with colours. This is done by writing to one pixel at a time in the
VGA Adapter core. Each row will be set to a different colour (repeating every 8 rows).
Create an FSM that implements the above algorithm. Your design should have an asynchronous
reset which will be driven by KEY (3). You don’t need to use KEY (0) or any of the switches in this
task. Note that your circuit will be clocked by CLOCK_50.
Test your design on the DE board. You need your DE board with a USB cable, a VGA cable, and a
VGA-capable display. Most new LCD displays have multiple inputs, including DVI (digital) and
VGA (analog). Note: the VGA connection on your laptop is an OUTPUT, so do not connect your
laptop’s VGA port to your DE board. Hint: Modelsim will be very useful for debugging your
component’s outputs.

VERILOG CODE:
module TASK2(input CLOCK_50, input [3:0]KEY, output [9:0] VGA_R, output [9:0] VGA_G, output [9:0]
VGA_B,output VGA_HS, output VGA_VS,output VGA_BLANK_N, output VGA_SYNC_N, output VGA_CLK,input
[9:0]SW);

reg state,next_state;

parameter drawc=0,stop=1;
always @(posedge CLOCK_50) begin

if (~KEY[3])begin

xcoor = 0;

ycoor = 0;

plot = 0;

end

else if (state==drawc)begin

if (xcoor < 159)

begin

xcoor = xcoor + 1;

colour = ycoor %8;

plot = 1;

end

else begin

ycoor =ycoor +1;

xcoor = 0;

colour = ycoor %8;

plot = 1;

end

end

vga_adapter VGA(.resetn(KEY[3]),.clock(CLOCK_50),.colour(colour),.x(xcoor),.y(ycoor),.plot(plot),.VGA_R(VGA_R),

.VGA_G(VGA_G),.VGA_B(VGA_B),.VGA_HS(VGA_HS),.VGA_VS(VGA_VS),.VGA_BLANK(VGA_BLANK_N),

.VGA_SYNC(VGA_SYNC_N),.VGA_CLK(VGA_CLK));

end

defparam VGA.RESOLUTION = "160x120";

defparam VGA.MONOCHROME = "FALSE";

defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;

defparam VGA.BACKGROUND_IMAGE = "image.colour.mif";

defparam VGA.USING_DE1 = "TRUE";

OUTPUT ON THE SCREEN:
Task 3: Bresenham Circle Algorithm
The Bresenham Circle algorithm is a hardware (or software!) friendly algorithm to draw circles
with arbitrary center and radius on the screen.
The algorithm is quite efficient: it contains no multiplication or division (multiplication by
multiples of 2 can be implemented by a shift-register that shifts left). Because of its simplicity
and efficiency, the Bresenham Circle Algorithm can be found in many software graphics libraries,
and in graphics chips. In this task, you will implement a circuit that behaves as follows: 1. The
switch KEY[3] is an asynchronous reset. When the machine is reset, it will start clearing the
screen to black.
Hint: Task2 is basically clearing the screen if you set all pixels to black. Clearing the screen will
take at least 160*120 cycles. 2. Once the screen is cleared, your circuit will idle. At this point,
the user can set switches 7 down to 3 (SW[7:3]), which indicates the radius, and switches 2
down to 0 (SW[2:0]), which indicates one of 8 possible colours used to draw the line.
IMPORTANT: Restrict user entered radius to be within 0 to 59. If you don’t, you will see some
unexpected behavior (strange patterns being drawn instead of a circle). For example, if the user
set the switches to indicate a value of 70 for radius, just clip it to 59. 3. When the user presses
KEY[0], the circuit will draw a circle. Centre of the circle should be the centre of the screen
(location 80,60) and radius as specified by the user. Of course, this will take multiple cycles; the
number of cycles depends on the radius of the circle. 4. Once the circle is done, the circuit will
go back to step 3, allowing the user to choose another radius and color. Do not clear the screen
between iterations. At any time, the user can press KEY[3], the asynchronous reset, to go back
to the start and clear the screen. The reset signal on the VGA Core does not clear the screen.
That’s why you need to do it manually in step 1. But this also means that you don’t have to do
anything special to retain previously drawn circles on the screen. Note that you are using
CLOCK_50, the 50MHz clock, to clock your circuit. You must clearly distinguish the datapath
from the FSM in your Verilog code (i.e. don’t write one giant always block to do everything). The
reason that this is a requirement is that we want you to practice manual partitioning of the
datapath and FSM for now.

VERILOG CODE:

module Task3(

input CLOCK_50,

input [3:0] KEY,

output [9:0] VGA_R,

output [9:0] VGA_G,

output [9:0] VGA_B,

output VGA_HS,

output VGA_VS,

output VGA_BLANK_N,
assign r_check =SW[8:3];

assign r=(r_check<59)?r_check:59;

always @(*) begin

case (state)

BEGIN: next_state = ((r!=0))?S0:BEGIN;

S0: next_state = S1;

S1: next_state = S2;

S2: next_state = S3;

S3: next_state = S4;

S4: next_state = S5;

S5: next_state = S6;

S6: next_state = S7;

S7: next_state = S0;

RESET: next_state=(reset_done)?BEGIN:RESET;

default: next_state = BEGIN;

endcase

end

always @(posedge CLOCK_50 or negedge KEY[3] or negedge KEY[0]) begin

if(~KEY[0])

state<=RESET;

else if (~KEY[3])

state <= BEGIN;

else

state <= next_state;

end

always @(posedge CLOCK_50 ) begin

if (~KEY[0]) begin

xcoor = 0;

ycoor = 0;

x = 0;

y = r;end
if (~KEY[3]) begin

xcoor = 0;

ycoor = 0;

x = 0;

y = r;

d = (3-2*r);

xc = 80;

yc = 60;

colour = SW[2:0];

plot = 0;

reset_done=0;

end

else if ((x <= y) && (r!=0)) begin

case (state)

S0: begin

xcoor = x + xc;

ycoor = y + yc;

plot = 1;

end

S1: begin

xcoor = xc - x;

ycoor = y + yc;

plot = 1;

end

S2: begin

xcoor = x + xc;

ycoor = yc - y;

plot = 1;

end
S3: begin

xcoor = xc - x;

ycoor = yc - y;

plot = 1;

end

S4: begin

xcoor = xc + y;

ycoor = x + yc;

plot = 1;

end

S5: begin

xcoor = xc - y;

ycoor = x + yc;

plot = 1;

end

S6: begin

xcoor = xc + y;

ycoor = yc - x;

plot = 1;

end

S7: begin

xcoor = xc - y;

ycoor = yc - x;

plot = 1;

x = x + 1;

if (d < 0)

d = d + (4*x) + 6;

else begin

d = d + 4*(x-y) + 10;

y = y - 1;

end end
 RESET : begin

if (xcoor < 160)

begin

xcoor = xcoor + 1;

colour = 0;

plot = 1;

end

else if(ycoor <120) begin

ycoor = ycoor +1;

xcoor = 0;

colour = 0;

plot = 1;

end

else begin

reset_done = 1;

end

end

endcase

end

end

vga_adapter VGA( .resetn(KEY[3]),.clock(CLOCK_50),.colour(colour), .x(xcoor),.y(ycoor),.plot(plot),

.VGA_R(VGA_R), .VGA_G(VGA_G),.VGA_B(VGA_B),.VGA_HS(VGA_HS),.VGA_VS(VGA_VS),

.VGA_BLANK(VGA_BLANK_N),.VGA_SYNC(VGA_SYNC_N),.VGA_CLK(VGA_CLK));

defparam VGA.RESOLUTION = "160x120";

defparam VGA.MONOCHROME = "FALSE";

defparam VGA.BITS_PER_COLOUR_CHANNEL = 1;

//defparam VGA.BACKGROUND_IMAGE = "image.colour.mif";

defparam VGA.USING_DE1 = "FALSE";

endmodule
OUTPUT ON SCREEN: