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ARM Interrupts

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31 views4 pages

ARM Interrupts

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dharani
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ARM Interrupts

Interrupts are signals that prompt the processor to pause its current operations and execute a specific piece
of code (the interrupt handler) to address the event that triggered the interrupt. Interrupts can come from
various sources, including hardware devices (like timers, sensors, etc.) and software.

Types of Interrupts
1. External Interrupts: Triggered by external hardware sources.
2. Internal Interrupts: Generated by internal sources, such as timers.
3. Software Interrupts: Generated by software instructions (like the SVC instruction for system calls).
4. System Exceptions: Special interrupts that occur due to processor-specific events (e.g., faults).

ARM Exceptions
Exceptions are a broader category that encompasses both interrupts and faults. They represent unexpected
conditions or events that alter the normal execution flow of a program.

Types of Exceptions

1. Reset:
 Triggered when the processor is reset (e.g., upon power-up).
 Always the highest priority, it clears the current state and initializes the system.

2. Non-Maskable Interrupt (NMI):


 High-priority interrupts that cannot be disabled.
 Used for critical error handling (like power failures).

3. Hard Fault:
 Occurs when the processor detects a serious error (e.g., accessing invalid memory).
 It can lead to the termination of the current task and may require a reset.

4. Memory Management Fault:


 Triggered by violations in memory access rights, such as illegal memory accesses or attempts to
read/write protected memory areas.

5. Bus Fault:
 Occurs when there’s an error accessing memory or peripherals, such as when a device is
unresponsive.

6. Usage Fault:
 Triggered when invalid instructions are executed (e.g., undefined instructions or attempts to
execute a non-executable memory region).

7. SVCall (Supervisor Call):


 Invoked by SVC instruction, it allows user applications to request services from the operating
system.

8. Debug Monitor:
 Allows the debugger to intervene during execution, typically used for debugging processes.

9. PendSV (Pendable Service Call):


 Used for context switching in an operating system, allowing for smooth task switching.

10. SysTick Timer:


 A timer interrupt that generates regular interrupts, useful for system timing and task
scheduling.

NVIC (Nested Vectored Interrupt Controller)

The NVIC is an integral part of ARM Cortex-M microcontrollers, managing the interrupts and exceptions
efficiently. It allows for prioritized, nested interrupt handling, enabling a higher-priority interrupt to preempt
a lower-priority one.

Key Features of NVIC

Features of NVIC

1. Nested Interrupt Handling:

 Supports multiple levels of interrupt priorities, allowing higher-priority interrupts to preempt


lower-priority ones. This is critical for real-time applications.

2. Low Latency:

 Fast context switching and low latency for interrupt handling ensure quick response to critical
events.

3. Dynamic Priority Levels:

 Each interrupt can be assigned a priority level that can be changed at runtime, providing
flexibility in how the system responds to different events.

4. Preemptive Handling:

 Allows for interrupts to interrupt other interrupts based on priority levels, ensuring that the most
critical tasks are serviced first.

5. Vector Table:

 Provides a method for efficiently locating the appropriate interrupt service routine (ISR) for each
interrupt source.
NVIC Registers

The NVIC contains several registers that control and manage interrupts. Here are the key NVIC registers
related to interrupt control:

1. Interrupt Priority Register (IPR):

 Function: Defines the priority of each interrupt.


 Access: 8 bits for each interrupt; lower numbers indicate higher priority.
 Usage: Set the priority levels for interrupts to manage which interrupts can preempt
others.

Example of setting priority:

NVIC->IPR[interrupt_number] = priority_level; // Set interrupt priority

2. Interrupt Set-Enable Register (ISER):

 Function: Enables specific interrupts.


 Access: Each bit corresponds to an interrupt; writing a 1 enables the corresponding
interrupt.
 Usage: Enable desired interrupts for handling.

Example of enabling an interrupt:

NVIC->ISER[0] = (1 << interrupt_number); // Enable the specific interrupt

3. Interrupt Clear-Enable Register (ICER):

 Function: Disables specific interrupts.


 Access: Similar to ISER, but writing a 1 disables the corresponding interrupt.
 Usage: Disable interrupts that are no longer needed.

Example of disabling an interrupt:

NVIC->ICER[0] = (1 << interrupt_number); // Disable the specific interrupt

4. Interrupt Set-Pending Register (ISPR):

o Function: Sets an interrupt as pending.

o Access: Writing a 1 to the corresponding bit makes that interrupt pending.

o Usage: Useful for triggering interrupts programmatically.

Example of setting an interrupt pending:

NVIC->ISPR[0] = (1 << interrupt_number); // Set the interrupt to pending state


5. Interrupt Clear-Pending Register (ICPR):

 Function: Clears the pending status of an interrupt.


 Access: Writing a 1 clears the pending status for the corresponding interrupt.
 Usage: Used after handling the interrupt to clear its pending state.

Example of clearing an interrupt pending:

NVIC->ICPR[0] = (1 << interrupt_number); // Clear the pending interrupt

6. Active Interrupt Register (AIR):

 Function: Indicates which interrupts are currently active.


 Access: Read-only register; provides status of active interrupts.
 Usage: Helpful for debugging and monitoring active interrupts.

Example of checking active interrupts:

uint32_t active_interrupts = NVIC->IABR[0]; // Get active interrupt status

7. Vector Table Offset Register (VTOR):

 Function: Specifies the address of the vector table.


 Access: Allows modification to point to a custom vector table.
 Usage: Essential for changing the default interrupt handling, particularly in real-time
operating systems.

Example of setting the vector table:

NVIC->VTOR = (uint32_t)&custom_vector_table; // Set vector table address

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