Electronics II

LTSpice Tutorial

TA: Yu-Chi Hung

Instructor: Sheng-Shian Li

Institute of NanoEngineering and MicroSystems

National Tsing Hua University, Taiwan

Sep. 2024
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Objective
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• Understand basic elements for circuit simulation

• Learn the basic usage of circuit simulators

• Know the concepts of device models

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 Circuit simulation background
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Circuit Topology

Physics

+
+
Device modeling Circuit simulator (EDA)
(Process dependent)

Device
characterizations
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Spice topology
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• HSpice as an example

Ref: National Chip Implementation Center(CIC), Hsinchu, Taiwan 4

Start your program
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• Install LTSpice IV
• File → Open → Browse your netlist
– Name your netlist as XXX.sp
– Ex: CAD1.sp

• What is “netlist”?
– “Netlist" describes the connectivity of an electronic
design

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Netlist Commends (simplified)
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TITLE First line is input file title

* Asterisk is a command to describe circuit
.LIB / .INCLUDE Cell library of general input files
.OPTIONS Set conditions for simulation
.PARAM Specify parameters
.IC / .NODESET Set initial states
.SUBCKT/.ENDS Define subcircuits
.AC / .DC / .TRAN / .TEMP Statement to set sweep variables
.OP Show DC operating points
.MEAS Provide measurement capability
.STEP Sweep variables
.END Required statement to terminate simulation

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Element and Node naming
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• Either names or numbers (ex: n1, 12, vout1, ….)

• Ground can be 0, gnd, or !gnd

• 0 is always ground

• All nodes are assumed to be local

• “Node Names” can be made across all subcircuits by a

“.GLOBAL” Statement (ex: .GLOBAL VDD VSS )

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Library input statement
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• Syntax
– .lib “filename” entryname
• Entryname is used to define the process corner
(TT, FF, SS…) in foundry CMOS
• No process corners is used in our simple homework.

• To use our “Free035.l” library, use the following:

– .lib “Free035.l”

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Instance and element names
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• Keyword + names
EX:
• VDD
• Cfeedback
• R01

Element names
Keyword, “R” denotes Resistor

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Element names and units
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All length and widths are in

meters

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Source Element
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• Syntax
– Vxxx n+ n- <voltage> ◆Insert Value in < >.
– Ixxx n+ n- <current>

• Examples
– VDD n1 n2 dc 3.3
– Ibias_01 nb1 nb2 dc 30uA
– Vin Vinn 0 dc 1.3 ac 1

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MOSFET
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• Syntax
– Mxx D G S B <model> [L=<len>] [W=<width>]
+ [M=<fingers>]

• Examples
– M26 n1 n3 n2 0 NM L=0.35u W=10u m=4
– Mb3 nbx nbx VDD VDD PM L=3u W=10u m=1

• In this course, model NM for NMOS, PM for

PMOS

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Passive elements
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• Syntax
– Rxx n1 n2 <value>
– Lxx n+ n- <inductance>
– Cxx n+ n- <capacitance>
• Examples
– Rbias VDD nbias 20k
– Ltune n1 n2 19u
– Cdec Vinx vss 20n

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Analysis type
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• .OP
– DC operation point
• .DC
– Sweep DC parameter
• .AC
– Sweep AC parameter, frequency domain
• .TRAN
– Time domain response

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.DC Analysis
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• Syntax
– .dc <srcnam> <Vstart> <Vstop> <Vincr>
+ [<srcnam2> <Vstart2> <Vstop2> <Vincr2>]

• Example
– .DC VDD 0 3.3 0.1 VG1 0 3.3 0.1

Major variable (x-axis)

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.AC analysis
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• Syntax
– .ac <oct, dec, lin> <Nsteps> <StartFreq> <EndFreq>
– Oct = no. of steps per octave
– Dec= no. of steps per decade
– Lin = Total number of linearly spaced steps between
StartFreq and EndFreq
• Example
– .ac dec 10 100k 10G

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.Tran Analysis
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• Syntax
– .TRAN <Tstep> <Tstop> [Tstart [dTmax]] [modifiers]

• Example
– .tran 0.1n 20u

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 Example
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• Common-source Amplifier, AC and DC simulation

• Nodes: VDD, Vin, Vout, VSS

• Assume W=5u, L=0.5u, m=4 for M1
• Assume RD=1.0k, and CL=1.0pF
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Example for .AC simulation
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Title

Obtain model library

Define global variables

Define subcircuits,
pin= Vin and Vout

Instant subckt
Load capacitance of the circuit

Power supplies and

input small-signal

.OP, save dc operation points

.AC, frequency response simulation

Termination command
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Output control
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• After simulation (left click “Run” at the toolbar)

you can see a black window
• Right click the black window, you can see:

列出所有能
觀察的資料
加入新的曲線
刪除曲線

在視窗中分隔出
子視窗

在圖中加入網格

在曲線上標出格點

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Output control
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• Select “Add trace”, you can see:

You can type formula here,

Ex: sqrt(V(vout)) to show the square
root of the output voltage gain

• Select “V(Vout)” and OK, you can get frequency

response.

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V(Vout)
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• Voltage gain: 9.126 dB (2.86 V/V)

• Phase: 180-degree at DC

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Example for .DC simulation
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Click here to show the cursor window

[email protected] = voltage gain= -2.83V/V
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 NATIONAL TSING HUA UNIVERSITY

空一行

叫Library
可視為一個有
兩個腳位的黑盒子
子電路
能夠在電路外使用的接點只有
Vin Vout 和.global中定義的點

叫子電路 X1 腳位1 腳位2 子電路名

名字可不同
其他電路上的
東西

你要跑什麼模擬

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