FPGA Seminar

ALGOSUP
About Me – Russell Merrick
• Vision Pipeline FPGA Designer, BAE Systems
• High reliability, fast signals, video, on aircraft
• Started Nandland after frustrations as an FPGA
beginner

• FPGA Designer, L-3 Communications

• Vision pipeline, low-power applications, high
reliability, small form factor

• FPGA and Embedded, Accion Systems

• Satellites, radiation tolerance, low-power

• Nandland.com
• Created the “Go Board”
• Writer of “Getting Started with FPGAs”
• YouTube channel
FPGA Introduction
• FPGA = Field Programmable Gate Array

• Field Programmable means it can be reprogrammed “in the field”

• Gate Array is an anachronism, no longer true

• Also not always Field Programmable!

• E.g. One Time Programmable FPGAs

• But the name is sticky

Common FPGA Usages
FPGA Usage
• Fast processing

• Unique Requirements

• Lots of Data

• Lots of Math

When you see these, FPGAs might be good tool to use!

Binary
• Have you ever wondered why computers use binary?

• In binary data is represented as:

• 0, 1
• False, true
• Low, high

• At the lowest level, this is the presence (or absence) of voltage

• Transistors are the fundamental component controlling this voltage

Transistor Appreciation Time
• Possibly THE single most important invention in modern times
Transistor Facts
• Created in 1947 at Bell Labs

• Enabled the digital age

• Building block of all integrated circuits (ICs)
• Creates a switch

20 BILLION
• Moore’s Law
• # of transistors in an IC doubles every 2 years
TRANSITORS IN A
MODERN
PROCESSOR!
Transistors and Binary
• Transistors store 0, 1 state

• Binary is 0, 1 state

• We need to understand how binary works

Dec Hex Binary
0 0x0 0000
Binary vs. Hex vs.
1 0x1 Decimal 0001
2 0x2 0010
3 0x3 0011
4 0x4 0100
5 0x5 0101
6 0x6 0110
7 0x7 0111
8 0x8 1000
9 0x9 1001
10 0xA 1010
11 0xB 1011
12 0xC 1100
13 0xD 1101
14 0xE 1110
15 0xF 1111
How many bits do we need?
• For 0, 1 = 1 bit
• For 0, 1, 2, 3 = 2 bits
• For 0, 1, 2, 3, 4, 5, 6, 7 = 3 bits
• For 0-15 = 4 bits
• For 0-31 = 5 bits
• For 0-63 = 6 bits

• In general, 2^N-1 where N is number of bits

FPGA Basics
• Two critical components
• LUT
• Flip-Flop

• Solid understanding of both is required to be a good FPGA designer

• We will introduce these two components and then learn how they
each work in projects
What is a LUT
• One of the 2 most critical components in your FPGA

• What is Boolean algebra?

• How is it performed inside of an FPGA?

• The Look-Up Table (LUT)

• How it can perform any Boolean algebra equation
Exploring Boolean Logic Gates
• Navigate to
https://logic.ly/demo/

• We can see how gates work

• AND
• OR
• NOT
• NOR
• NAND
• etc
And Gate

Truth Table
Input A Input B Output Q
0 0 0
0 1 0
1 0 0
1 1 1
And Gate

Connect circles with

wires by clicking and
drawing

Ensure you’re able to create AND gate. Verify its behavior

Or Gate

Truth Table
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 1
Not Gate

Truth Table
Input A Output Q
0 1
1 0
Nor Gate

Truth Table
Input A Input B Output Q
0 0 1
0 1 0
1 0 0
1 1 0
Xor Gate

Truth Table
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 0
Nand Gate

Truth Table
Input A Input B Output Q
0 0 1
0 1 1
1 0 1
1 1 0
Combining Gates with Boolean Algebra

Truth Table – A*B + A’

Input A Input B Output Q
0 0 1
0 1 1
1 0 0
1 1 1

Create this circuit in logic.ly. Fill in the last column of the truth table
by going through each input combination
 Combining Gates with Boolean Algebra
Truth Table – A+(C*B')
Input A Input B Input C Output Q
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1 Create this circuit in logic.ly. Fill in the last
1 1 0 1 column of the truth table
1 1 1 1 by going through each input combination
The Look-Up Table does all Boolean Algebra!

And gates, Or Gates, Nor Gates, etc, DO NOT EXIST ON A REAL FPGA!

But we can perform those functions with a LUT

4+ Inputs? No Problem

IN4

We can cascade LUTs to do more complicated operations!

Summary
• The LUT is one of the two most fundamental components in your
FPGA

• It can perform any Boolean algebra equation

• Multiple LUTs can be cascaded for more complicated equations

• The LUT output is evaluated IMMEDAITELY!

FPGA History
• Originally, FPGAs could only do
simple boolean algebra

• But this was still very important

in 1980s

• You can now change your circuit!

• FPGAs have gotten much more

complex
The Flip-Flop
• Second critical FPGA component

• Store state, ability to remember

• LUTs are instant, flip-flops have memory

• Knowing passage of time is impossible without flip-flops

D Flip-Flop Block Diagram

Input Data (D)

Input Enable (En)
Input Clock (>)
Output Q
The Clock
• The key to driving all flip-flops
• Main gear / heartbeat

• 99% of the time, rising edge

• 50% Duty cycle

• Frequency (Hz) / Period (ns)

• E.g. 10 MHz = 100 ns
Clock Tree

• Dedicated Input Pin Used

• Dedicated Routing Logic

used to minimize skew
Flip-flop in action

• Assume clock enable always high

• Registers data on rising edge

• Doesn’t “see” changes until edge

of the clock
2nd Example – Clock Enable always high
Flip-Flop example with Clock Enable

We can now remember past values! LUTs cannot, but Flip-Flops can!
Flip-Flop in Logic.ly
• Create this circuit

• Select D-Flip-Flop

• Select Clock

• Ensure to tie PRE’ and CLR’ to 1

(high constant)

• Toggle switch and check that LED

output only changes on rising edge
Chaining flip-flops
Flip-Flop Chain in Logic.ly

Draw the circuit, verify behavior of each Flip-Flop adding delay

T and JK Flip-Flops are a waste of time
• The D Flip-Flop is the workhorse

• T and JK flip-flops are not relevant in modern FPGA design

LUTs and Flip-flops on a real FPGA
Summary
• LUT and Flip-Flop are the two FPGA work-horses

• LUTs handle all Boolean algebra

• Flip-Flops store state (remember past values)

• Clocks are fundamental, your FPGA heartbeat

• They drive all flip-flops in your design
The Go Board
Project: Frogger
Frogger – Hardware Setup

Monitor Go Board

VGA Cable
Frogger
• You control a frog’s movement on the monitor

• Buttons on Go Board are used to direct frog up, down, left right

• Cars move horizontally

• If frog is hit by car the game is over

• Level is indicated on 7-segment display

Project Frogger – Playable Area
20

A single 1x1 cell

Frog can move anywhere within 20x15 grid

(20 x 15 = 300 cells total)
15
If it gets hit by a car the game is over
Project Frogger – Frog control

Frog occupies one 1x1 cell

The frog changes direction based on

button pressed (up, down, left, right)

F
Project Frogger – Car Control
Cars (C) appear

C Can travel either left or right

C
One car per “row”
C
C Cars can move at different speeds
C
Cars can have different lengths
C

F
Project Frogger – Level Display
F When Frog reaches the top row, frog
resets to bottom
C
Level counter on 7-segment display
C
increments
C
C
C

C
Time check for lab component
Programming Language on FPGA
• Type of Hardware Description Language (HDL)
• We are literally designing wires, gates, etc, “describing hardware”

• Verilog and VHDL are the two most popular

• We will be focused on Verilog

• Most similar to C

• Specifically for FPGA development

Coding Tool
• Recommended: Microsoft VS
Code
https://code.visualstudio.com/

• Built-in syntax highlighting for

Verilog

• Lots of extensions (amazing!)

A note about ChatGPT
• ChatGPT is extremely good at helping you along in your FPGA (and
programmer) development

• Back-and-forth questions are the best ways to have success

• But it can make mistakes, so verify all output yourself

Don’t
• In general, if you’re forget
stuck, to thank
ask ChatGPT likethe AIasking
you’re  a teacher
Lab Component
When Should/Shouldn’t you use FPGA
• Often need “smarts” in electronics
• Toys, Consumer Electronics, Industrial Robotics, etc, all needs it.
• Two possible options:
• FPGAs
• Microcontrollers
• (also ASICs for very high volume)
FPGA Basics
• Basic building blocks
• Look-Up Table (LUT)
• Flip-Flop/Register

• Written in VHDL or Verilog

• Program discrete components

and wires

• Often no CPU
Microcontroller Basics
• Has a processor (CPU)

• Often written in C

• Discrete blocks perform functions

FPGA Strengths
• Parallelization
• Lots of math, especially multiply
• Lots of I/O possible
• Highly Customizable
• High Bandwidth throughput
Microcontroller Strengths
• Cost (this is why there are so many!)
• Relative Simplicity (vs. FPGA)
• Physically small
• Many functions built-in
• E.g. USB, UART, SPI, ADC, DAC, etc.
• Thousands of unique variants
• Can pick exactly your need
• Low Power
How to Choose?
• Know your requirements!

• What’s #1, #2, #3 most important?

• Weigh solutions and pick best

Example #1
• Russell is tasked with taking HD image data from a computer, filtering
it, and sending it to an OLED screen to display

• Req #1 - Needs custom interfaces

• Req #2 - Lots of Math
• Req #3 - Low Power
• Req #4 - Cost
Winner – FPGA
• Oculus Rift VR Headset
Example #2
• Russell is tasked with taking ultrasonic sensor data and determining
distance to objects

• Req #1 - Proof of concept needed in 2 months

• Req #2 - Cost
• Req #3 - Low Power
• Req #4 - Basic math, can be slow
Winner - Microcontroller
• Amazon “Scout”
autonomous delivery
When is FPGA the right tool?
• Microcontrollers are easier, faster to program, & cheaper than FPGAs

• FPGAs fill a niche

• Whenever someone asks me to use an FPGA, first question I ask:

• “Are you sure?”

• Engineering is about choosing the right tool for the job

Hardware Setup (~15 min)
• Open source FPGA build tools:
APIO

• OR iCEcube2 from Lattice

• We will be using APIO open

source tools

• Get setup and make sure

Example LED blinky is working!
How to Setup Apio Project
• Open command prompt (Run As Administrator)
• Create new directory for your work
• Type: apio init –b “go-board” –t “project_gates”
• Should see: File 'apio.ini' has been successfully created!

• Open this file and look at it, can manually edit if needed.
How do we know what is where?
• Go Board Schematic has this
information

• Shows all connections on Go Board

• Need to know which PIN NUMBER

the LEDs and Switches are
physically connected to.

• Helpful to have some basic EE

knowledge as FPGA designer
Tell APIO about the Pins
• Physical Constraints File (.pcf)

• Create new file called “Go_Board_Constraints.pcf”

and add these lines to it:

### LED Pins:

set_io o_LED_1 56

## Push-Button Switches
set_io i_Switch_1 53
set_io i_Switch_2 51
Project – LUT
LUT, as And Gate

Truth Table
Input A Input B Output Q
0 0 0
0 1 0
1 0 0
1 1 1
Let’s describe some hardware
module project_gates
(input i_Switch_1, Save your file “project_gates.v”
input i_Switch_2,
output o_LED_1);
module / endmodule
assign o_LED_1 = i_Switch_1 & i_Switch_2;
Inputs first, outputs second
endmodule

“assign” keyword in Verilog is used

to assign an output

“&” is the AND operator

~15 minute project

Post-Synthesis Results
Resource Usage Report for And_Gate_Project

Mapping to part: ice40hx1kvq100

Cell usage:
SB_LUT4 1 use

1 I/O ports: 3
I/O primitives: 3
SB_IO 3 uses

I/O Register bits: 0

Register bits not including I/Os: 0 (0%)
Total load per clock:

Mapping Summary:
2 Total LUTs: 1 (0%)
Project: Implement Gates (~15 min)
• Add two new inputs (i_Switch_3 and i_Switch_4)
• Add one new output (o_LED_2)
• Make sure to add these to your constraint file too!
• i_Switch_3 = Pin 54
• i_Switch_4 = Pin 52
• o_LED_2 = Pin 57

• Create XOR gate, verify with truth tables or Logic.ly

• Notice that both AND gate and XOR gate are running in parallel and the
output is evaluated immediately.
Verilog Code – Project Solution

module project_gates
• Notice that these two assigns
(input i_Switch_1, will execute in parallel (at the
input i_Switch_2,
input i_Switch_3,
same time)
input i_Switch_4,
output o_LED_1,
output o_LED_2);
• They’re always “running” (and
assign o_LED_1 = i_Switch_1 & i_Switch_2; there’s no delay from input to
assign o_LED_2 = i_Switch_3 ^ i_Switch_4;
output)
endmodule
 SW1 SW2 SW3 SW4 LED1 LED2 LED3

Project – Boolean Algebra 0

0
0
0
0
0
0
1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

1. Create this circuit in your FPGA

2. Fill in truth table
~30 minutes 3. Verify with Logic.ly
 SW1 SW2 SW3 SW4 LED1 LED2 LED3

Project – Solution 0
0
0
0
0
0
0
1
1
1
0
0
1
1
0 0 1 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 0 1 1 1 1
0 1 1 0 0 0 0
0 1 1 1 1 1 0
1 0 0 0 1 0 1
1 0 0 1 1 0 1
1 0 1 0 1 1 1
1 0 1 1 1 1 1
1 1 0 0 0 0 0
1 1 0 1 1 1 1
1 1 1 0 1 1 0
1 1 1 1 1 1 1
Project - Code
module project_boolean_algebra
(input i_Switch_1,
input i_Switch_2,
input i_Switch_3,
input i_Switch_4,
output o_LED_1,
output o_LED_2,
output o_LED_3);

assign o_LED_1 = o_LED_2 | o_LED_3;

assign o_LED_2 = (i_Switch_1 & i_Switch_3 ) | (i_Switch_2 & i_Switch_4);
assign o_LED_3 = (i_Switch_1 | ~i_Switch_3 ) & (~i_Switch_2 | i_Switch_4);

endmodule
 module project_boolean_algebra_wires

Project – With Wires (input i_Switch_1,

input i_Switch_2,
input i_Switch_3,
input i_Switch_4,
z1 output o_LED_1,
output o_LED_2,
output o_LED_3);

wire w_z1, w_z2, w_z3, w_z4;

z2
assign w_z1 = i_Switch_1 & i_Switch_3;
assign w_z2 = i_Switch_2 & i_Switch_4;
assign w_z3 = i_Switch_1 | ~i_Switch_3;
assign w_z4 = ~i_Switch_2 | i_Switch_4;
z3 assign o_LED_1 = o_LED_2 | o_LED_3;
assign o_LED_2 = w_z1 | w_z2;
assign o_LED_3 = w_z3 & w_z4;
z4
endmodule

Same circuit being described with intermediary wires.

Always more than 1 way to write the same functional code.

Ternary Operator - ?
• ? allows us to make a selection between two choices

assign output = select ? value_if_true : value_if_false;

Output Selector Assignment Assignment

if true if false

• Useful to create a multiplexer (mux)

Multiplexer (Mux)
• Selects between multiple inputs
to single output

• Ex. Fan control, LED output

select, etc.
sel1 sel2 out
0 0 in1
0 1 in2
1 0 in3
1 1 in4
 Multiplexer in Verilog

sel1 sel2 out

0 0 in1
0 1 in2
1 0 in3
1 1 in4

assign out = !sel1 & !sel2 ? in1 :

!sel1 & sel2 ? in2 :
sel1 & !sel2 ? in3 : in4;

Ternary Operator: ?
Demultiplexer (Demux)
• Opposite of mux

• Takes 1 input, selects to multiple outputs

• Muxes and Demuxes can come in any size

• 7-1 Mux, 1-7 Demux
• 16-1 Mux, 1-16 Demux
• Etc

• Simple to implement in Verilog, doesn’t require dedicated module

Module Instantiation in Verilog
• FPGAs can be thought of like Legos.

• Build up complicated designs from simple building blocks

• Modules allow us to build a component and use it over and over

Module Instantiation in Verilog
• Module Name wire w_Input;
• The module you’re instantiating. wire w_Output;
Matches the .v file name
module_name INSTANCE_NAME
• INSTANCE NAME (.i_1(w_Input),
• Can be anything you like .o_1(w_Output));

• Signal mapping
• Explicit connections between
module signals (left) and high level
signals (right)
Project – And Gates using Module
Instantiation
• Create a module called and_gate
• Two inputs, one output
• Performs AND operation

• Create another module called project_and_gates

• Four inputs (push-button switches)
• Two outputs (LEDs)
• Connect everything together

• Wire up two and_gate modules and verify behavior

Project – Solution module project_and_gates
(input i_Switch_1,
input i_Switch_2,
input i_Switch_3,
input i_Switch_4,
output o_LED_1,
module and_gate output o_LED_2);
(input i_1,
input i_2, and_gate GATE_1
output o_1); (.i_1(i_Switch_1),
.i_2(i_Switch_2),
assign o_1 = i_1 & i_2; .o_1(o_LED_1));

endmodule and_gate GATE_2

(.i_1(i_Switch_3),
.i_2(i_Switch_4),
.o_1(o_LED_2));

endmodule
Summary
• All projects have been working with LUTs only

• Output is evaluated immediately

• We have seen how FPGAs use simple building block

• Modules can be built and used in other modules to create hierarchy

Always Block
• Always blocks allow us to create Flip-
Flops!
• Flip-Flops give FPGA ability to remember

• posedge is reserved word in Verilog always @(posedge i_Clock)

begin
• Sensitivity list is in () // Do something
end
• begin/end are like {} in C

• // is a comment in Verilog
 Creating our first Flip-Flop
reg r_Switch_1;
i_Switch_1 r_Switch_1
always @(posedge i_Clock)
1 begin
r_Switch_1 <= i_Switch_1;
i_Clock end
If/else statements
always @(posedge i_Clock)
• We can use if statements within begin
always blocks
if (Value > Check)
begin
// Do something
• Allows us to check equality, end
compare numbers, check if a
else
pulse is high, etc. begin
// Do something else
end
• Use begin/end like {} end
Reg vs. Wire
• reg is reserved keyword in Verilog
• Short for “register” which is another word for Flip-Flop

• For example: reg r_LED_State;

• I like to put r_ in front of registers
• Create flip-flops (registers) using <= operator

• Wire is also a reserved word.

• I like to put w_ in front of wires: wire w_Switch;

• Signals defined as reg can be assigned in an always block

• Signals defined as wire cannot be assigned in an always block
Thinking about Reg vs. Wire
• Think of Reg as register / Flip-Flop

• Think of wire as a piece of wire, has no storage of state

• What else has no ability to store state? LUT!

• Wire = LUT behavior (or just intermediary signals)

• Reg = Flip-Flop behavior

Project – Light up “LED”
• Light up an LED when button is released

• Will require 2 flip-flops to implement, and one LUT

• Need to look for the falling edge of the button press

Falling Edge Detection

CLK

Falling Edge
SW1 Detection

r_Switch_1
Block Diagram
• Suggest always block diagram

• Helps to define modules and

interfaces

• Shows high level flow of

information
 30 min project
module project_flip_flop • “assign” keyword not needed
(input i_Clk,
input i_Switch_1, inside always blocks
output o_LED_1);

reg r_LED_1;
reg r_Switch_1;
• Use “<=” assignment for flip-
flops
always @(posedge i_Clk)
begin
// 1. Create r_Switch_1 flip-flop
• Inversion achieved with “~”
// 2. Look for falling edge condition (NOT gate)
(switch is released)

// 3. Use that to toggle LED flip-flop

end CLK

Falling Edge
assign o_LED_1 = r_LED_1; SW1 Detection
endmodule
r_Switch_1
Resource + Clock Report
• Resource Usage Report for LED_Toggle_Project
•
• Mapping to part: ice40hx1kvq100
• Cell usage:
• SB_DFF 2 uses
• SB_LUT4 1 use
•
1::Clock Frequency Summary
• I/O ports: 3
==========================================================
• I/O primitives: 3
Number of clocks: 1
• SB_GB_IO 1 use
Clock: i_Clk | Frequency: 654.05 MHz | Target: 25.00 MHz |
• SB_IO 2 uses
•
• I/O Register bits: 0
• 1 Register bits not including I/Os: 2 (0%)
• Total load per clock:
• 2 LED_Toggle_Project|i_Clk: 1
• Mapping Summary:
• 3 Total LUTs: 1 (0%)
Project 2 - Discussion
• First use of clock, needed for Flip-Flop!
• Flip-Flops store state (past/memory)
• Did this line look weird?
• r_LED_1 <= ~r_LED_1;
• Will be updated on NEXT clock cycle

• Thinking in terms of clock cycles and flip-flops takes practice.

• Challenge question: Why does the LED sometimes toggle, but not
always?
Combinational vs. Sequential Logic
• Combinational Logic
• Logic for which the outputs are determined from present inputs, with no
memory of the previous state
• Also called Combinational

• Sequential Logic
• Logic for which the outputs are determined from both present inputs and
previous outputs
• Also called Synchronous

• Flip flops are sequential, because they depend on the previous output
Combinational Always Blocks
• Recommend avoiding

• E.g. always @ (input_1 or input_2)

begin
and_gate <= input_1 & input_2;
end

Dangerous, can cause latches!

Sequential Always Blocks
• Has only clock (or sometimes reset)

• Every time you see an always block, you know it’s going to generate
sequential logic.

always @ (posedge i_Clk)

• Safe, no latches begin
and_gate <= input_1 & input_2;
end
Simulation and Testbenches
• Two ways to find bugs:
• On Hardware
• EXTREMELY time consuming, esp in large designs
• FPGAs are a block box

• In Simulation
• All signals become visible
• Makes the black box a white box

• Story of coworker struggles

The Testbench

• Purpose is to exercise your UUT

• Generates stimulus to UUT

• Monitors outputs of UUT

FPGA Simulation Tools
• Modelsim
• $$$

• Built-in Simulators
• Vivado
• Quartus

• Free Simulator
• EDA Playground
https://edaplayground.com
 Writing Simple Testbench
module And_Gate_Project initial
(input i_Switch_1, begin
input i_Switch_2, $dumpfile("dump.vcd"); $dumpvars;
output o_LED_1); r_In1 <= 1'b0;
r_In2 <= 1'b0;
assign o_LED_1 = i_Switch_1 & i_Switch_2; #10;
r_In1 <= 1'b0;
endmodule r_In2 <= 1'b1;
#10;
module And_Gate_TB(); r_In1 <= 1'b1;
r_In2 <= 1'b0;
reg r_In1, r_In2; #10;
wire w_Out; r_In1 <= 1'b1;
r_In2 <= 1'b1;
And_Gate_Project UUT #10;
(.i_Switch_1(r_In1), $finish();
.i_Switch_2(r_In2), end
.o_LED_1(w_Out)); endmodule
Waveforms
• Can show all signals with your design
• Require visual inspection to show code is functioning as expected
• Great for debugging, but can be tedious in large designs
How to improve this testbench?
• Every time we run the simulation, we need to look at the waveforms
• Tedious, time-consuming, can be prone to error

• If a new designer comes along, or if it’s been years since you’ve

worked it, how do you know everything is working?

• If you change/add code, how to you ensure you didn’t break old
stuff? (big issue!)
Self-Checking Testbenches
• Add “asserts” into your testbenches
• E.g. assert (expected_value == actual_value)
• Produces PASS/FAIL results, no waveform viewing required
• Can run multiple simulations quickly
• Can perform regression testing
• If you modify existing code, you can be confident you didn’t break
some old code
SystemVerilog
• Superset of Verilog (contains everything in Verilog, and much more)

• Used primarily for simulation, test, verification

• Also has new synthesizable features

• E.g. Classes, Interfaces, Sequences, Assertions

Assertions
• Biggest bang-for-buck for writing self-checking testbenches

assert (statement_to_check);