Sequential Logic Implementation

! Models for representing sequential circuits

" " " " " " " " " Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous Mealy machines Verilog specification Deriving state diagram Deriving state transition table Determining next state and output functions Implementing combinational logic

! Finite state machine design procedure

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Mealy vs. Moore Machines

! Moore: outputs depend on current state only ! Mealy: outputs depend on current state and inputs ! Ant brain is a Moore Machine ! We could have specified a Mealy FSM
" Output does not react immediately to input change " Outputs have immediate reaction to inputs " As inputs change, so does next state, doesnt commit until clocking event
L R / TL, F L / TL A react right away to leaving the wall L R / TR, F
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Specifying Outputs for a Moore Machine

! Output is only function of state
" Specify in state bubble in state diagram " Example: sequence detector for 01 or 10
0 B/0 0 reset 0 A/0 1 C/0 1 1 0 E/1 1 0 1 D/1 reset 1 0 0 0 0 0 0 0 0 0 0 input 0 1 0 1 0 1 0 1 0 1 current state A A B B C C D D E E next state A B C B D E C E C B D output 0 0 0 0 0 0 1 1 1 1

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Specifying Outputs for a Mealy Machine

! Output is function of state and inputs
" Specify output on transition arc between states " Example: sequence detector for 01 or 10
0/0 B 0/0 reset/0 A 1/0 C 1/0
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0/1

1/1

reset 1 0 0 0 0 0 0

input 0 1 0 1 0 1

current state A A B B C C

next state A B C B C B C

output 0 0 0 0 1 1 0

Comparison of Mealy and Moore Machines

! Mealy Machines tend to have less states ! Moore Machines are safer to use
" Different outputs on arcs (n^2) rather than states (n) " Outputs change at clock edge (always one cycle later) " In Mealy machines, input change can cause output change as soon as logic is done a big problem when two machines are interconnected asynchronous feedback " React in same cycle don't need to wait for clock " In Moore machines, more logic may be necessary to decode state into outputs more gate delays after
Combinational logic for Next State inputs reg Logic for outputs outputs Logic for outputs Combinational logic for Next State outputs reg

! Mealy Machines react faster to inputs

inputs

state feedback

state feedback

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Mealy and Moore Examples

! Recognize A,B = 0,1
" Mealy or Moore?
A B clock

Q Q

out

Q Q

out

B clock

Q Q

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Mealy and Moore Examples (contd)

! Recognize A,B = 1,0 then 0,1
" Mealy or Moore?
out A D Q Q B D clock Q Q

out A D Q Q B D Q Q clock D D Q Q Q Q

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Registered Mealy Machine (Really Moore)

! Synchronous (or registered) Mealy Machine
" Registered state AND outputs " Avoids glitchy outputs " Easy to implement in programmable logic

! Moore Machine with no output decoding

" Outputs computed on transition to next state rather than after entering " View outputs as expanded state vector
output logic next state logic Current State
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Outputs

Inputs

Verilog FSM - Reduce 1s Example

! Change the first 1 to 0 in each string of 1s
" Example Moore machine implementation
// State assignment parameter zero = 0, one1 = 1, two1s = 2; module reduce (out, clk, reset, in); output out; input clk, reset, in; reg out; reg [1:0] state; // state register reg [1:0] next_state; 0 0 zero [0] 1 one1 [0] 1 two1s [1] 1 0

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Moore Verilog FSM (contd)

always @(in or state) case (state) zero: begin // last input was a zero out = 0; if (in) next_state = one1; else next_state = zero; end one1: begin // we've seen one 1 out = 0; if (in) next_state = two1s; else next_state = zero; end two1s: begin // we've seen at least 2 ones out = 1; if (in) next_state = two1s; else next_state = zero; end default: begin // in case we reach a bad state out = 0; next_state = zero; endcase 0 zero [0] 1 0 one1 [0] 1 two1s [1] 1 0

include all signals that are input to state and output equations

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Moore Verilog FSM (contd)

// Implement the state register always @(posedge clk) if (reset) state <= zero; else state <= next_state; endmodule 0 0 zero [0] 1 one1 [0] 1 two1s [1] 1 0

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Mealy Verilog FSM for Reduce-1s Example

module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg state; // state register reg next_state; parameter zero = 0, one = 1; always @(in or state) case (state) zero: begin // last input was a zero if (in) next_state = one; else next_state = zero; out = 0; end one: // we've seen one 1 if (in) begin next_state = one; out = 1; end else begin next_state = zero; out = 0; end endcase always @(posedge clk) if (reset) state <= zero; else state <= next_state; endmodule
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0/0 zero 0/0 1/0 one1 1/1

Synchronous Mealy Verilog FSM for Reduce-1s Example

module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg state; // state register reg next_state; reg next_out; parameter zero = 0, one = 1; always @(in or state) case (state) zero: begin // last input was a zero if (in) next_state = one; else next_state = zero; next_out = 0; end one: // we've seen one 1 if (in) begin next_state = one; next_out = 1; end else begin next_state = zero; next_out = 0; end endcase always @(posedge clk) if (reset) begin state <= zero; out <= 0; end else begin state <= next_state; out <= next_out; end endmodule
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0/0 zero 0/0 1/0 one1 1/1

Announcements
! Review Session Announcement ! First Midterm, Thursday, 15 February, 2-3:30 PM, 125 Cory Hall

" ??? Quiz-like Questions -- Please Read Them Carefully! They are not intended to be tricky; they should contain all the information you need to answer the question correctly " No calculators or other gadgets are necessary! Dont bring them! No blue books! All work on the sheets handed out! " Do bring pencil and eraser please! If you like to unstaple the exam pages, then bring a stapler with you! Write your name and student ID on EVERY page in case they get separated -it has happened! " Dont forget your two-sided 8.5 x 11 crib sheet!

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Announcements
! Examination, Th, 2-3:30 PM, 125 Cory Hall
" Topics likely to be covered
# Combinational logic: design and optimization (K-maps up to and including 6 variables) # Implementation: Simple gates (minimum wires and gates), PLA structures (minimum unique terms), Muxes, Decoders, ROMs, (Simplified) Xilinx CLB # Sequential logic: R-S latches, flip-flops, transparent vs. edge-triggered behavior, master/slave concept # Basic Finite State Machines: Representations (state diagrams, transition tables), Moore vs. Mealy Machines, Shifters, Registers, Counters # Structural and Behavioral Verilog for combinational and sequential logic # Labs 1, 2, 3 # K&B: Chapters 1, 2 (2.1-2.5), 3 (3.1, 3.6), 4 (4.1, 4.2, 4.3), 6 (6.1, 6.2.1, 6.3), 7 (7.1, 7.2, 7.3)

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Example: Vending Machine

! Release item after 15 cents are deposited ! Single coin slot for dimes, nickels ! No change
Reset

N Coin Sensor D

Vending Machine FSM

Open

Release Mechanism

Clock

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Example: Vending Machine (contd)

! Suitable Abstract Representation
" Tabulate typical input sequences:
# # # # 3 nickels nickel, dime dime, nickel two dimes
Reset

S0 N S1 N S3 N S7 [open] D S4 [open] N S5 [open] D S2 D S6 [open]

" Draw state diagram: " Assumptions:

# Inputs: N, D, reset # Output: open chute # Assume N and D asserted for one cycle # Each state has a self loop for N = D = 0 (no coin)

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Example: Vending Machine (contd)

! Minimize number of states - reuse states whenever possible
Reset present state 0 inputs D N 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 next state 0 5 10 5 10 15 10 15 15 15 output open 0 0 0 0 0 0 0 0 0 1

0 N 5 N D 10 N+D 15 [open] 15 D 10 5

symbolic state table

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Example: Vending Machine (contd)

! Uniquely Encode States
present state inputs Q1 Q0 D N 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 1 1 1 1 next D1 0 0 1 0 1 1 1 1 1 1 state D0 0 1 0 1 0 1 0 1 1 1 output open 0 0 0 0 0 0 0 0 0 1

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Example: Vending Machine (contd)

! Mapping to Logic
D1 Q1 0 0 1 1 0 1 1 1 D X X X X 1 1 1 1 Q0 N D D0 Q1 0 1 1 0 1 0 1 1 X X X X 0 1 1 1 Q0 N D Q1 Open 0 0 1 0 0 0 1 0 X X X X 0 0 1 0 Q0 N

D1 = Q1 + D + Q0 N D0 = Q0 N + Q0 N + Q1 N + Q1 D OPEN = Q1 Q0

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Example: Vending Machine (contd)

! One-hot Encoding
present state Q3 Q2 Q1 Q0 0 0 0 1 inputs D N 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 - next state output D3 D2 D1 D0 open 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 - - - 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 - - - 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 - - - 1 0 0 0 1

D0 = Q0 D N D1 = Q0 N + Q1 D N D2 = Q0 D + Q1 N + Q2 D N D3 = Q1 D + Q2 D + Q2 N + Q3 OPEN = Q3

0 0

0 1

1 0

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Equivalent Mealy and Moore State Diagrams

! Moore machine " outputs associated with state
Reset N D + Reset 0 [0] N D 5 [0] N D 10 [0] N+D 15 [1] Reset N D D/1 N+D/1 15 Reset/1 N D D/0 N/0 10 N D/0

Mealy machine outputs associated with transitions

Reset/0 (N D + Reset)/0

N D N/0

N D/0

N D/0

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Moore Verilog FSM for Vending Machine

module vending (open, Clk, Reset, N, D); input Clk, Reset, N, D; output open; reg open; reg state; // state register reg next_state; parameter zero = 0, five = 1, ten = 2, fifteen = 3; always @(N or D or state) case (state) zero: begin if (D) next_state else if (N) next_state else next_state open = 0; end fifteen: begin if (!Reset) next_state else next_state open = 1; end endcase Reset N D + Reset 0 [0] N = five; = ten; = zero; D 5 [0] N D 10 [0] N+D 15 [1] Reset N D N D

N D

= fifteen; = zero;

always @(posedge clk) if (Reset || (!N && !D)) state <= zero; else state <= next_state; endmodule
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Mealy Verilog FSM for Vending Machine

module vending (open, Clk, Reset, N, D); input Clk, Reset, N, D; output open; reg open; reg state; // state register reg next_state; reg next_open; parameter zero = 0, five = 1, ten = 2, fifteen = 3; always @(N or D or state) case (state) zero: begin if (D) begin next_state = ten; next_open = 0; end else if (N) begin next_state = five; next_open = 0; end else begin next_state = zero; next_open = 0; end end endcase Reset/0 (N D + Reset)/0

0 N/0 D/0 N/0 D/1 N+D/1 15 10 5

N D/0

N D/0

N D/0

Reset/1

always @(posedge clk) if (Reset || (!N && !D)) begin state <= zero; open <= 0; end else begin state <= next_state; open <= next_open; end endmodule
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Example: Traffic Light Controller

! A busy highway is intersected by a little used farmroad ! Detectors C sense the presence of cars waiting on the farmroad

! Assume you have an interval timer that generates:

" " " "

" with no car on farmroad, light remain green in highway direction " if vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the farmroad lights to become green " these stay green only as long as a farmroad car is detected but never longer than a set interval " when these are met, farm lights transition from Green to Yellow to Red, allowing highway to return to green " even if farmroad vehicles are waiting, highway gets at least a set interval as green a short time pulse (TS) and a long time pulse (TL), in response to a set (ST) signal. TS is to be used for timing yellow lights and TL for green lights
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Example: Traffic Light Controller (contd)

! Highway/farm road intersection
farm road car sensors

highway

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Example: Traffic Light Controller (contd)

! Tabulation of Inputs and Outputs
inputs reset C TS TL description place FSM in initial state detect vehicle on the farm road short time interval expired long time interval expired outputs description HG, HY, HR assert green/yellow/red highway lights FG, FY, FR assert green/yellow/red highway lights ST start timing a short or long interval

! Tabulation of unique states some light configurations imply others

state S0 S1 S2 S3 description highway green (farm road red) highway yellow (farm road red) farm road green (highway red) farm road yellow (highway red)

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Example: Traffic Light Controller (contd)

! State Diagram
(TLC)' S0 TS / ST S0: HG S1: HY S2: FG S3: FY TS / ST S2 TL+C' / ST TS' S1 TLC / ST S3 TS' Reset

(TL+C')'

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Example: Traffic Light Controller (contd)

! Generate state table with symbolic states ! Consider state assignments
Inputs C TL 0 0 1 1 1 0 0 1 SA1: SA2: SA3: Present State TS 0 1 0 1 HG = 00 HG = 00 HG = 0001 HG HG HG HY HY FG FG FG FY FY HY = 01 HY = 10 HY = 0010 Next State HG HG HY HY FG FG FY FY FY HG FG = 11 FG = 01 FG = 0100 output encoding similar problem to state assignment (Green = 00, Yellow = 01, Red = 10) Outputs ST H 0 Green 0 Green 1 Green 0 Yellow 1 Yellow 0 Red 1 Red 1 Red 0 Red 1 Red FY = 10 FY = 11 FY = 1000 F Red Red Red Red Red Green Green Green Yellow Yellow

(one-hot)

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Traffic Light Controller Verilog

module traffic (ST, Clk, Reset, C, TL, TS); input Clk, Reset, C, TL, TS; output ST; reg ST; reg state; reg next_state; reg next_ST; parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3; always @(C or TL or TS or state) case (state) S0: if (!(TL && C)) begin next_state = S0; next_ST = 0; else if (TL || C) begin next_state = S1; next_ST = 1; end endcase

(TLC)' S0 TLC TL+C / ST TS' S1

Reset

TS / ST S3 TS'

TS / ST S2

TL+C' / ST

always @(posedge Clk) if (Reset) begin state <= S0; ST <= 0; end else begin state <= next_state; ST <= next_ST; end endmodule

(TL+C')'

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Logic for Different State Assignments

! SA1
NS1 = CTL'PS1PS0 + TSPS1'PS0 + TSPS1PS0' + C'PS1PS0 + TLPS1PS0 NS0 = CTLPS1'PS0' + CTL'PS1PS0 + PS1'PS0 ST = CTLPS1'PS0' + TSPS1'PS0 + TSPS1PS0' + C'PS1PS0 + TLPS1PS0 H1 = PS1 H0 = PS1'PS0 F1 = PS1' F0 = PS1PS0' NS1 = CTLPS1' + TS'PS1 + C'PS1'PS0 NS0 = TSPS1PS0' + PS1'PS0 + TS'PS1PS0 ST = CTLPS1' + C'PS1'PS0 + TSPS1 H1 = PS0 H0 = PS1PS0' F1 = PS0' F0 = PS1PS0 NS3 = C'PS2 + TLPS2 + TS'PS3 NS1 = CTLPS0 + TS'PS1 NS2 = TSPS1 + CTL'PS2 NS0 = C'PS0 + TL'PS0 + TSPS3

SA2

SA3

ST = CTLPS0 + TSPS1 + C'PS2 + TLPS2 + TSPS3 H1 = PS3 + PS2 H0 = PS1 F1 = PS1 + PS0 F0 = PS3

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Vending Machine Example Revisted (PLD mapping)

D0 D1 OPEN = reset'(Q0'N + Q0N' + Q1N + Q1D) = reset'(Q1 + D + Q0N) = Q1Q0
CLK Q0 Seq

DQ

DQ

Q1 Seq

DQ

Open Com

Reset
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Vending Machine (contd)

! OPEN = Q1Q0 creates a combinational delay after Q1 and Q0 change ! This can be corrected by retiming, i.e., move flip-flops and logic through each other to improve delay ! OPEN = reset'(Q1 + D + Q0N)(Q0'N + Q0N' + Q1N + Q1D) = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D) ! Implementation now looks like a synchronous Mealy machine " Common for programmable devices to have FF at end of logic

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Vending Machine (Retimed PLD Mapping)

OPEN = reset'(Q1Q0N' + Q1N + Q1D + Q0'ND + Q0N'D)
CLK Q0 Seq

DQ

DQ

Q1 Seq

OPEN DQ

Open Seq

Reset
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Sequential Logic Implementation Summary

! Models for representing sequential circuits
" " " " " " " " " Abstraction of sequential elements Finite state machines and their state diagrams Inputs/outputs Mealy, Moore, and synchronous Mealy machines Verilog specification Deriving state diagram Deriving state transition table Determining next state and output functions Implementing combinational logic

! Finite state machine design procedure

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