Beyond CMOS Computing - Lec 1-5
Beyond CMOS Computing - Lec 1-5
Beyond CMOS Computing - Lec 1-5
1. CMOS Scaling
Dmitri Nikonov
Thanks to Kelin Kuhn
[email protected]
1 Nikonov 1. CMOS
Outline
2 Nikonov 1. CMOS
Moore’s Law
3 Nikonov 1. CMOS
Moore’s Law
4 Nikonov 1. CMOS
Scaling Falsifies Predictions
5 Nikonov 1. CMOS
How Far Scaling Went
1980 SRAM Cell: 1700 um2 22nm SRAM Cell: 0.092 um2
10000X
6 Nikonov 1. CMOS
Metal Interconnects
9 levels of metal
7 Nikonov 1. CMOS
Contacted Gate Pitch
8 Nikonov 1. CMOS
Economics of Moore’s Law
1010
10
100 As the 109
number of
10-1 transistors 108
10-2 goes UP
$ per 107 Transistors
Transistor 10-3 Price per per Chip
106
10-4 transistor
goes DOWN 105
10-5
10-6 104
10-7 103
’70 ’80 ’90 ’00 ’10
Year
“Doubling of number of transistors per chip every 2 years”.
Lowers cost per transistor.
Self-fulfilling prophesy.
Original paper: G.E. Moore, Electronics 19, 114 (1965)
9 Nikonov 1. CMOS
Classic Scaling
10 Nikonov 1. CMOS
Process Evolution
11 Nikonov 1. CMOS
Inflection in Scaling
THEN NOW
Scaling drove down cost Scaling drives down cost
Scaling drove performance Materials drive performance
Performance constrained Power constrained
Active power dominates Standby power dominates
Independent design-process Collaborative design-process
12 Nikonov 1. CMOS
Short Channel Effects (SCE)
Degradation of
~ 1 / Subthreshold short channel effects
Slope (mV/dec)
V2 > V1
~DIBL (mV/V) ID
Decreasing L
VG
13
Electrostatics Benefits
“On”
Poor Current
SCE
Reduced Threshold
Channel Voltage
Current
(normalized)
Good
SCE
“Off”
Current
Basic ID-VG
14
Threshold Voltage
~Subthreshold
Slope (mV/dec)
~VTlin
~DIBL (mV/V)
http://en.wikipedia.org/wiki/Threshold_voltage
9
On Current, Off Current
~Subthreshold
Slope (mV/dec)
Ioff
IDsat
~VTlin
~DIBL (mV/V)
Idsat (=Ion)
Ioff IDsat
IDsat
9
Performance from Scaling
17 Nikonov 1. CMOS
Where Performance Comes From
4.5
2
1.5
1
0.5
0
90 65 45 32 22
Generation (nm)
Strain and High-k + metal gate are key
enablers past the 90nm node
K.J. Kuhn, Moore's Law past 32nm: Future Challenges in Device Scaling,
Solid State Devices and materials conference, plenary, October 2009
18 Nikonov 1. CMOS
Intel Announced First Tri-Gate (2011)
19 Nikonov 1. CMOS
Close-Up on Tri-gate Transistors
20 Nikonov 1. CMOS
Nomenclature of Non-Planar Devices
21 Nikonov 1. CMOS
Where Non-Planar Can Go?
22 Nikonov 1. CMOS
Working With Atomic Dimensions
23 Nikonov 1. CMOS
International Technology Roadmap for Semiconductors
24 Nikonov 1. CMOS
Limits of Computing
Transistor Limits Interconnect Limits
14nm inverter
neuron
Eswtsw h
Meindl, Proc. IEEE 83, 619 (1995).
26 Nikonov 1. CMOS
Better Fundamental Limits
Thermodynamic limit on bit error ratio OFF
Esw 3kT source gate drain
Higher energy = faster switching
Eswtsw electron
electron
Solving equations together gives
limits
27 Nikonov 1. CMOS
MOSFET Scales Towards the Limit
100 100
10
10 1
0.1 0.0001
0.00001
0.01 0.000001
0.001 0.01 0.1 1 0.001 0.01 0.1 1
LGATE (mm) LGATE (mm)
28 Nikonov 1. CMOS
How long is left for Moore’s law
29 Nikonov 1. CMOS
Summary
30 Nikonov 1. CMOS
Beyond CMOS computing
Dmitri Nikonov
Thanks to Ian Young
[email protected]
Brown
Columbia
Illinois-UC
MIT/U.Virginia
Nebraska-Lincoln
UC Los Angeles Northwestern
UC Berkeley Penn State
Princeton / UT-Austin
UC Irvine Purdue
UC Riverside Stanford
UC Santa Barbara U. Alabama
Portland State UC Berkeley
U. Nebraska-Lincoln UT-Austin Rice Virginia Nanoelectronics
U. Wisconsin-Madison UT-Dallas Texas A&M Center (ViNC)
U. Maryland NCSU University of Virginia
Old Dominion University
College of William & Mary
e-
SpinFET spin-current
All Spin Logic
e
Spin
Torque
Oscillator
Spin
Torque
Triad
RAMA
Injection Domain
Enhanced FET wall ring Hbi
as
substrate
current
Electron
structure
modulation FET Phononic
Excitonic FET
MTJ+STT Graphene thermal
Orbitronic transistor
HetJTFET
gnrTFET
Magnetic source
and drain
Spin polarized
carriers might
not have vacant
states
Parallel
magnetizations
= smaller R
Anti-parallel =
larger R
Graphene electrostatically
doped by p or n carriers
Electrons reflect in
interface dep. On angle
Routs electrons by total
internal reflection
Mux configuration
spin-torque
e
spin-current
e
-V
e-
/2 0 θ
Generic Electronic Switch Generic Spintronic Switch
Barrier 20 kT (from Ion/Ioff) 60 kT (non-volatile)
Voltage 0.5 – 1 V 10-100 mV
Particles Ne = 200 electrons Ns = 10000 spins
Switching Energy Limit 4000kT = Ne*20kT 60 kT
Phenomenon Non collective Collective
SpinFET spin-current
All Spin Logic
e
Spin
Torque
Oscillator
Spin
Torque
Triad
3. Introduction to Non-
Equilibrium Green’s Functions
Dmitri Nikonov
1 Nikonov 3. NEGF
Outline
2 Nikonov 3. NEGF
Quantum States
Schrodinger’s equation
Time dependent Time independent
E H
i H
t
px
sin solution
iEt solution
exp
p 2
E Ep
2m
3 Nikonov 3. NEGF
Green’s functions
E H (in ) Injection or removal of particles,
scattering interaction
1
G
E E p i
4 Nikonov 3. NEGF
Challenges of Green’s functions
Poles in the complex plane Time ordering, propagators
Feynman diagrams
5 Nikonov 3. NEGF
Equilibrium vs. Non-equilibrium
Green’s functions
Supriyo Datta
(Purdue U.)
6 Nikonov 3. NEGF
Reservoirs and distribution functions
Fermi distribution
E gate 1
E 1,2
f1,2 exp 1
V gs k BT
Each contact in
equilibrium
Device in between
NOT in equilibrium
2 1 eVds
Reservoir=thermal bath=electrode=contact
7 Nikonov 3. NEGF
Single-level transistor
Rate of injection to/from source and drain [eV ] / [ s 1 ]
gate Currents
e
I1 f1 N
1 e
N f2
I2 N f2
f1
Population of the level
2
I2 f1 f 2
I1 N
2
Current
e
This direction of current due to
I f1 f 2
2
the negative electron charge
8 Nikonov 3. NEGF
Green’s function for a single level
1
G
E E p i
Density of states, normalized
D ( E ) Im(G ) /
/
GG
p
2
E E 2
9 Nikonov 3. NEGF
Single-level conductance
Current distributed over energies
e
I
2 T (E) f 1 f 2 dE
Transmission coefficient
in general depends on quantum
T ( E ) D ( E ) 1
reflection and tunneling
f 1 f 2 dE 1 2 eVds
I e2 1
Vds 2 26k
10 Nikonov 3. NEGF
Single-level current-voltage
Equal voltage splitting 1 EF Vds / 2
EF 0 E p 0.2 eV
2 EF Vds / 2
Vg=0
1
N f2
f1
2 Conduction gap +/-0.2V
I1 I2
11 Nikonov 3. NEGF
MolcToy
https://nanohub.org/tools/molctoy
12 Nikonov 3. NEGF
Generalize to many levels = matrices
Green’s function [1/eV]
G ( E ) EI H 1 2
1
gate
Density of states
D ( E ) i (G G ) / 2
1
1 2
f2 Electron spectral density [1/eV]
f1
2 G n ( E ) GinG †
in 1 f1 2 f 2
Current spectral density [A/eV]
Hamiltonian H
Tr 1G 2G † f1 f 2
e
I (E)
2
NEGF formalism = inversion and multiplication of matrices
13 Nikonov 3. NEGF
Kinetic energy– hopping
p2 2
2
H Schrodinger’s equation of a free particle
2m 2m x 2
p2 2
n 1 2 n n 1
H finite differences in the atomic basis
2m 2m a2
Hamiltonian = 3 diagonals,
2t t sparse
t 2t t 2
Motion of electrons looks like hopping from one atom to the next
For highly doped semiconductors need this picture to explain conductance.
14 Nikonov 3. NEGF
Hamiltonian – bandstructure
1D 2D 3D
15 Nikonov 3. NEGF
Layered devices
2t t
t 2t t
H
t 2t t
t 2 t
16 Nikonov 3. NEGF
Electrostatics – solve consistently
V(x)
G ( E ) EI H 1 2
1
2t eV1 t
t 2t eV2 t
H
t 2t eVN 1 t
t 2 t eV N
n(x),p(x)
17 Nikonov 3. NEGF
NEGF Formalism, Put Together
G ( E ) E i I H (E)
1
s S ( E ) D ( E )
Hamiltonian = self-energy = incoherent
bandstructure, evolution: injection and
coherent evolution scattering
G ( E ) G G
n in †
electron spectral density from in-flux
G ( E ) G G
p out †
hole spectral density from out-flux
1 G n (E) carrier density
n 3 dE
k , s a 2
ie dE
I j j 1 H j , j 1G nj 1, j ( E ) H j 1, j G nj , j 1 ( E )
k ,s
2 current density – off-diagonal
elements
18 Nikonov 3. NEGF
NanoMOS
https://nanohub.org/resources/nanomos/
Double-gate transistor.
Effective mass
approximation
19 Nikonov 3. NEGF
How to read plots -
density
D(E,x) = local density of
states (LDOS)
Shows where available
states for electrons are.
Depends on energy and
coordinate along the device.
White lines = band edges.
20 Nikonov 3. NEGF
How to read plots -
current
Efs
I(E,x) = spectral density of
current. Efd
It flows only in a certain range
of energies – source density is
sufficient and over the barrier.
Does not change along the
device – ballistic case (no
scattering).
21 Nikonov 3. NEGF
Quantum effects
22 Nikonov 3. NEGF
Electron-phonon interaction
H ep M q aq bq e iq t iqr
bq† e
iq t iqr
e-ph interaction Hamiltonian
q 1
q
aq bb †
qq ' nq qq ' exp 1
2 V q
q q'
k BT
half-amplitude number of phonons
of a phonon
in ( r1 , r2 , E ) M q a q2 exp iq ( r1 r2 ) n q 1 G n ( r1 , r2 , E q )
2
emission
q
M q a q2 exp iq ( r1 r2 ) n qG n ( r1 , r2 , E q ) absorption
2
23 Nikonov 3. NEGF
Diagonal matrices
x=1…N
2t V1 t diagonal in
t 2t V2 t coordinate space =
H zero for coordinate
t 2t VN 1 t indices different by 2
or more
t 2t VN
x=1…N
x=1…N
S 1 scattering
2
self-energies
N 1
D N
x=1…N
24 Nikonov 3. NEGF
Scattering
Contact
1 0 0 0 interaction
0 Inelastic, e.g. optical
s 0 0 phonon scattering.
Connects states with
0 0 s 0 Scattering
different energies.
0 0 0 2
25 Nikonov 3. NEGF
OMEN nanowire
https://nanohub.org/resources/omenwire/
Atomistic basis.
Complete bandstructure.
Nanowire geometry 3D.
26 Nikonov 3. NEGF
Transistor – ballistic transport
27 Nikonov 3. NEGF
Transistor – with phonon scattering
28 Nikonov 3. NEGF
Simple analytics for a transistor
0 mean free path
0 transmission
T
0 L coefficient
2k BTL
vT thermal velocity
my
m y k BTL 2D density factor
N2D
h 2
U ds bias, units kT
ID / w
g v qN 2 D vT T
2
F1 2 S F1 2 S U ds
29 Nikonov 3. NEGF
On current, valid for both ballistic and
diffuse
Adapted from
1 V 2
Lundstrom, Guo
ID W 1 1
“Nanoscale Transistors;
Cox C s 2 L V Device Physics,
vT Modeling and
Simulation”
gate oxide
ballistic
semiconductor scattered
30 Nikonov 3. NEGF
Summary
31 Nikonov 3. NEGF
Beyond CMOS computing
4. Tunneling FETs
Dmitri Nikonov
Thanks to Uygar Avci
[email protected]
1 Nikonov 4. TFET
Outline
Band-to-band tunneling
Tunneling FET operation principles
Experimental realizations
Atomistic simulations
Homojunction TFET
Heterojunction TFET
2 Nikonov 4. TFET
Motivation
• Need lower VDD to lower Switching Energy (~C.VDD2)
• When CMOS supply voltage is scaled <0.5V, performance suffers significantly
InAs [email protected]
TFET
Low-power Switching
0.3 fJ
MOSFET 8x Energy
Leakage
0.5 nW
Power
TFET
Lg=20nm
(VLSI 2011)
3 Nikonov 4. TFET
MOSFET
Vg Gate
Source Drain Subthreshold slope in
Vd MOSFETs is limited by the tail
N i N of the Fermi distribution
1
eV eV
f exp
1 exp
kT kT
To the thermodynamic limit
value
~ 1 / Subthreshold
Slope (mV/dec)
d log( I ) e
60mV / decade
1
SS
dVg kT
Vg Gate
Source Drain Tunnel FETs operate by
Vd tunneling through the S/D
P+ i-InAs N barrier rather than
diffusion over the barrier
Two required conditions:
• Thin enough barrier over
a large enough area for
effective (high current)
tunneling.
• Sufficient density of
states on both the
Tunneli transmission and
receiving sides to
ng provide energetic
barriers locations for the carriers.
Courtsey M. Luisier (Purdue)
M. Luisier and G. Klimeck, EDL, 2009
5
5 Nikonov 4. TFET
Cartoon of density of States
* per 1 spin state
Fermi level
kF
Probability of tunneling
http://en.wikipedia.org/wiki/Quantum_tunneling
w=width=1nm
2 w 2 mbU b mb=mass= 0.2* 9.1*10-31kg
T exp Ub=height=0.8eV
T~0.016
Heavier mass smaller tunneling probability
A~0.3m
2 e V
2
N= 4*1046 /(J*m3)
J TU b2 N l N r a 4
J/V=1.2*1014 S/m2
V / J RA 0.5 m 2
7 Nikonov 4. TFET
TFET Device and Operation
MOSFET-like structure, but with opposite type
doping in Source and Drain
Can use different device geometries like MOSFET
Over
the
Vg Barrier
MOSFET
Through
the
Barrier
TFET Vg
8 Nikonov 4. TFET
Device Operation
S S
D D
S S
D D
9 Nikonov 4. TFET
Device Operation
S S
D D
S S
D D
10 Nikonov 4. TFET
Device Operation
S S
D D
S S
D D
11 Nikonov 4. TFET
Device Operation
S S
D D
S S
D D
12 Nikonov 4. TFET
Homojunction vs. Heterojunction
• Heterojunction can achieve higher tunneling current
Heterojunction
Homojunction
Material- A Material- B
13 Nikonov 4. TFET
Si TFET (UC Berkeley)
• Show of highest possible current with Si with sub-60 mV/dec
SS
– Best published Si or Ge TFET
– Shows high-angle to gate interface tunneling increases current
VLSI 2010
14 Nikonov 4. TFET
SiGe TFET (CEA-LETI)
• Show of high current with no sub-60 mV/dec SS
– Possibly not a TFET but metal contact to channel. No sub-
60mV/dec expected.
VLSI 2012
15 Nikonov 4. TFET
Vertical III-V (Intel, Penn-State, Notre Dame)
• Intel: Showed sub-60mV/dec SS
• Penn-State: High-current capability of heterojunction TFET
• Notre Dame: High-current with tunneling perpendicular to gate
interface
16 Nikonov 4. TFET
Intel TFET Demonstration !
17 Nikonov 4. TFET
Other Experimental TFET
• Stanford (2006): CNT
– Good SS at very low current (pA)
18 Nikonov 4. TFET
Most Experimental Still Poor Performance
S. Mookerjea et al., IEDM ‘09 [1] K. Jeon, et al., VLSI (11.4.1.-1) 2010
[2] W. Choi et al., IEEE-EDL vol.28, no.8, p.743 (2007)
[3] F. Mayer et al., IEDM Tech Dig., p.163 (2008)
[4] T. Krishnamohan et al., IEDM Tech Dig., p.947
(2008)
19 Nikonov 4. TFET
TFET Modeling Approaches
For accurate prediction, quantum solution with band-structure
calculation is chosen
20 Nikonov 4. TFET
Atomistic Quantum Modeling
3D ballistic quantum transport and atomistic full-band tight-
binding band structure calculation
No fitting to experimental electrical characteristics. The only input
parameters are bandstructure of the material and geometry.
Ec
Ev
x
OMEN
21 Nikonov 4. TFET
TFET Sub-threshold Slope
Tunneling current increases sharply at the onset of Source
Valence Band and Channel Conduction Band overlap
TFET
1.E-04
S 1.E-05
ID (A/um)
1.E-06
Ch 1.E-07
1.E-08
D VDS=0.4V
1.E-09
0.0 0.1 0.2 0.3 0.4
VG (V)
22 Nikonov 4. TFET
TFET Sub-threshold Slope
• Tunneling current increases sharply at the onset of Source
Valence Band and Channel Conduction Band overlap
TFET
1.E-04
S
S 1.E-05
ID (A/um)
1.E-06
Ch 1.E-07
1.E-08
Ch
D VDS=0.4V D
1.E-09
0.0 0.1 0.2 0.3 0.4
VG (V)
23 Nikonov 4. TFET
Effect of Gate-length
TFET subthreshold-slope improves significantly at longer
gate-length for a 10nm-body with a single-gate
Lg=25 nm
Id (uA/um)
50 nm
100nm
Single-gate
Vg (V) 10nm body
24 Nikonov 4. TFET
Single-gate vs. Double-gate
Increased gate-control continues to improve TFET
characteristics, whereas MOSFET is limited by 60mV/dec
DG TFET
2.5x
SG TFET
SG or DG
MOSFET
~60
40 <20 mV/dec
5nm body
Lg=100nm
For cnst. IOFF=1nA/um
25 Nikonov 4. TFET
Effect of Body thickness
Thinner body has lower SS and higher drive
The effect is much less pronounced than SG/DG difference
tB=10 nm
20 nm
thinner
Single-gate
Lg=100nm
For cnst. IOFF=1nA/um
26 Nikonov 4. TFET
Effect of Device Geometry on
Subthreshold-Slope
2x Lg
½ tB
SGDG Lg=50nm tB=10nm SG
Lg=100nm tB=10nm SG
Lg=100nm tB=5nm SG
Lg=100nm tB=5nm DG
27 Nikonov 4. TFET
InAs TFET Device Design
• Narrow bandgap (e.g. InAs) required for high ION
• Drain underlap to lower ambi-polar IOFF leakage
1.E+02
1.E+01
ID (uA/um)
1.E+00 LG = 20 nm
tBody = 5 nm
1.E-01
tOx(SiO2) = 1 nm
ITRS Low Power CMOS NSource = 5e19 cm-3
1.E-02
NDrain = 5e18 cm-3
1.E-03
TFET- S/D Symmetric
TFET with Drain underlap
1.E-04
-0.2 -0.1 0.0 0.1 0.2 0.3 0.4 0.5
VDS=0.5V
VG (V)
28 Nikonov 4. TFET
Transistor Characteristics - II
TFET has better Rout in the saturation region (high VDS)
TFET has higher saturation voltage (VDSAT-EFF)
30 VGS 30
TFET =0.35V MOSFET (ITRS)
25 25 0.35V
VDSAT-EFF
20 20
ID (uA/um)
0.3V
15 15 IOFF =1nA/μm
10 0.25V 10 0.3V
VDSAT-EFF
5 0.2V 5
0.25V
0 0 0.2V
0.0 0.1 0.2 0.3 0.0 0.1 0.2 0.3
VDS (V) VDS (V)
29 Nikonov 4. TFET
Transistor Characteristics
• Subthreshold Slope (SS): 34-45 mV/dec
• Strong IOFF dependence on VDS
1.E+02
TFET
1.E+01
1.E+00
ID (uA/um)
1.E-01
1.E-02 0.5V
1.E-03
0.4V VDS
1.E-04 0.3V
1.E-05 0.2V
0.1V
1.E-06
-0.1 0.0 0.1 0.2 0.3 0.4 0.5
VG (V)
30 Nikonov 4. TFET
HTFET Material Considerations
31 Nikonov 4. TFET
InAs TFET, on current
32 Nikonov 4. TFET
InAs/GaSb TFET, on current
33 Nikonov 4. TFET
Heterojunction TFET
Both simulations and experimental data show significant
improvement for heterojunction channel design over
homojunction
Heterojunc.
Lg=15nm
Homojunc. Simulation
(Avci, VLSI Tech ‘12)
Heterojunc.
Lg=100nm
Experimental
Homojunc.
(Dewey, IEDM’11)
34 Nikonov 4. TFET
InAs/GaSb Heterojunction TFET
T-FET ION/IOFF characteristic was improved for both N-type and P-type with:
• Thinner channel
• Changing device material from InAs homo-junction to a GaSb/InAs hetero-junction.
• P-TFET sub-threshold slope has MOS-like thermal behavior ~60mV/dec, due to
low density of sates (DOS) in the conduction band.
N-type P-type
1.E+03 1.E+03
1.E+02 1.E+02
1.E+01 1.E+01
30-45 ~60
Id (uA/um)
Id (uA/um)
1.E+00
mV/dec VDS = 0.5V mV/dec 1.E+00
1.E-01 IOFF = 10pA/um 1.E-01
35 Nikonov 4. TFET
TFET Capacitance
Increased TFET CGD capacitance quoted in literature, due to the
choice of TFET material (Si or Ge). But lower capacitance at
smaller voltages – beneficial for delay.
TFET
S Channel D
EF
EF
Filled
states
1E+20 E
Eff. Density of States (1/cm3)
Valance
Band
1E+19
DOS
EF LOW
1E+18 EF
1E+17
Conduction
HIGH
Band
1E+16
Ge
Si
InGaAs
InSb
InAs
x (nm)
37 Nikonov 4. TFET
TFET Summary
Benefits
Vg Gate
• Steep sub-threshold slope
Source Drain (< 60 mV/dec)
Vd • Large Ion/Ioff ratio
P+ i-InAs N
• Geometry scales well
• Some designs are compatible with
conventional SiGe/Si CMOS
processes
Challenges
• Poor experimental drive currents
• Ambipolar conduction
(high DB leakage for bulk devices)
• No comparable PTFET
• Asymmetric device behavior (issues in
Tunneli SRAM)
ng • Most attractive at very low operating
voltages (where product frequencies
barriers may be not so interesting)
Courtsey M. Luisier (Purdue)
M. Luisier and G. Klimeck, EDL, 2009
38 Nikonov 4. TFET
Summary
39 Nikonov 4. TFET
Beyond CMOS computing
5. Graphene Devices
Dmitri Nikonov
1 Nikonov 5. Graphene
Outline
Graphene TFETs
Graphene p-n junctions
Bilayer graphene FET
Bose condensation at room temperature?
2 Nikonov 5. Graphene
Graphene Hamiltonian
a1 and a2 =
Basis vectors
a2
t=3eV
a1 Hopping
amplitude
E0 h*
H h t 1 exp( ika1 ika 2 )
h E0
3 Nikonov 5. Graphene
Graphene Bandstructure
4 Nikonov 5. Graphene
Graphene real space momentum space -
Brillouin zone
K
K K
4
3a
K K
5 Nikonov 5. Graphene
Nanotube two 2
wrapped periodically subbands a
closest to K, K
degeneracy 2
K K
Ly=
na
K K
K
wrapped periodically
T=3acc 2
2 m a
periodic condition k y , m subbands, m=-n+1,…,n
an
6 Nikonov 5. Graphene
Nanoribbon one subband 2
real edge closest to K, a
degeneracy 1 K
K K
Ly=
na 0
K K
real edge K
T=3acc
m
hardwall condition k y , m subbands, m=1,…,2n
an
7 Nikonov 5. Graphene
Bandgap
Bandgap, eV
0.8
EG (CNT )
D
EG (CNR ) 0.8
2W
Size, nm
Bandgap inversely proportional to nanoribbon width or nanotube
diameter.
8 Nikonov 5. Graphene
Graphene MOSFET
9 Nikonov 5. Graphene
Graphene TFET Prediction
10 Nikonov 5. Graphene
Graphene TFET Better Analysis
11 Nikonov 5. Graphene
Graphene p-n Junction
12 Nikonov 5. Graphene
Reflections at Interface
Reflection behaves as if
negative index of refraction.
Snell’s law.
13 Nikonov 5. Graphene
Bilayer Graphene Bands
14 Nikonov 5. Graphene
Layer Coupling, Like Bose Condensation
15 Nikonov 5. Graphene
Unbalanced Charges Decrease Coupling
16 Nikonov 5. Graphene
More details ?
17 Nikonov 5. Graphene
Current-voltage characteristic
4
SPICE model BiSFET characteristics (V p Vn ) / Vmax
4
I G o (V p Vn ) 1
exp( 1 | V p Vn | / Vmax )
balanced, VG1
= 0 mV
unbalanced,
VG1 = 25 mV Vmax Vmax,o exp( 10 | p n | /( n p ))
18 Nikonov 5. Graphene
Fundamentals of Excitons
me / h 0.054m0 mass of carriers in a bilayer graphene,
McCann E, Fal'ko V I Phys. Rev. Lett. 96 086805 (2006)
mr me / 2 reduced mass in an exciton
mx 2me mass of an exciton
4 s 0 2
Bohr radius, bigger than dielectric thickness,
aB 2
8.7 nm needs accurate simulation
mre 4
mre binding energy, comparable to thermal energy,
Ry 18.3meV Eb=Ry for 3D, Eb=4Ry for 2D,
4 s 0
2 2
2 in between for realistic
2 2 de Broglie wavelength at room temperature,
dB 2 13nm comparable to device size, quantum effects !!!
m x k BT
g4 degeneracy factor = 2 for valley * 3 for spin
20 Nikonov 5. Graphene
Theory of BEC of excitons is OLD !!!
Keldysh L V and Kozlov A N, Zh. Eksp. Teor. Fiz. 54, 978 (1968)
(Sov. Phys.—JETP 27, 521)
Keldysh L V and Kopaev Yu E, Fiz. Tverd. Tela 6, 2791 (1964)
(Sov. Phys.—Solid State 6, 6219)
magnetoexcitons
Lozovik Yu E and Yudson V I, Zh. Eksp. Teor. Fiz. 71, 738 (1976)
(Sov. Phys.—JETP 44, 389)
Lozovik Yu E and Yudson V I, Pis. Zh. Eksp. Fiz. 25, 18 (1977)
(JETP Lett. 66, 355)
Main messages:
excitons are not real, but composite bosons
excitons act as bosons and undergo a condensation at lower density
(BEC regime)
at higher densities, the composite nature (consists of fermions) appears, similar to
Bardeen-Cooper-Schrieffer pairing. Formation of exciton dielectric, superfluidity is
absent
(BCS regime)
re-interpreted in
Comte C and Nozieres P, J. Phys. 43, 1069 (1982)
Nozieres P and Comte C, J. Phys. 43, 1083 (1982)
and the next slide
21 Nikonov 5. Graphene
Critical temperature composite bosons
“Models of coherent exciton condensation” P B Littlewood†, P R Eastham, J M J
Keeling, F M Marchetti, B D Simons and M H Szymanska, cond-mat 0407058v1
BCS
BEC
23 Nikonov 5. Graphene
Outline
24 Nikonov 5. Graphene