1.
Which one of the following offers CPUs as integrated memory or peripheral
interfaces?
a) Microcontroller
b) Microprocessor
c) Embedded system
d) Memory system
ANSWER: A
2. It retains its content when power is removed. What type of memory is this?
a) Volatile memory
b) Non-volatile memory
c) RAM
d) SRAM
ANSWER: B
3. ________ is designed by Zilog.
a) Z80
b) Zigbee
c) 80386
d) None of the above
ANSWER: B
4. Which of the following allows the reuse of the software and the hardware
components?
a) Platform based design
b) Peripheral design
c) Memory design
d) Architecture design
ANSWER: A
5. _______ can be a paired set of 16-bit register.
a) CD
b) HE
c) AB
d) HL
ANSWER: D
6. List out the functions that are provided by integrated memory management unit in
80386 architecture
a) Optional on-chip paging
b) 4 levels of protection
c) Virtual memory support
d) All of the above
ANSWER: D
7. By which instruction does the switching of registers take place
a) Instruction opcodes
b) AXX instruction
c) EXX instruction
d) Register instruction
ANSWER: C
8. RISC based processor is
a) SPARC
b) 80386
c) MC68030
d) MC68020
ANSWER: A
9. Princeton architecture is also known as
a) Harvard
b) Von Neuman architecture
c) RISC
d) CISC
ANSWER: B
10. How is memory accessed in RISC architecture?
a) Load and store instruction
b) Opcode instruction
c) Memory instruction
d) Bus instruction
ANSWER: A
11. While CPU is executing a program, an interrupt exists then it
a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
ANSWER: C
12. Whenever a number of devices interrupt a CPU at a time, and if the processor is able
to handle them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability
ANSWER: C
13. The Programmable interrupt controller is required to
a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request
ANSWER: B
14. What does ISR stand for?
a) interrupt standard routine
b) interrupt service routine
c) interrupt software routine
d) interrupt synchronous routine
ANSWER: B
15. Abbreviate CISC and RISC.
a) Complete Instruction Set Computer, Reduced Instruction Set Computer
b) Complex Instruction Set Computer, Reduced Instruction Set Computer
c) Complex Instruction Set Computer, Reliable Instruction Set Computer
d) Complete Instruction Set Computer, Reliable Instruction Set Computer
ANSWER: B
16. Which of the following capacitor can store more data in DRAM?
a) 1Mb
b) 4-256 Mb
c) 8-128Mb
d) 64-128Mb
ANSWER: D
17. Time duration required for scheduling dispatcher to stop one process and start another
is known as ____________
a) process latency
b) dispatch latency
c) execution latency
d) interrupt latency
ANSWER: B
18. Which type of non-privileged processor mode is entered due to raising of high priority
of an interrupt?
a) User mode
b) Fast Interrupt Mode (FIQ)
c) Interrupt Mode (IRQ)
d) Supervisor Mode (SVC)
ANSWER: B
19. Which of the following memory organisation have the entire memory available to the
processor at all times?
a) segmented addressing
b) paging
c) virtual address
d) linear address
ANSWER: D
20. Where is memory address stored in a C program?
a) stack
b) pointer
c) register
d) accumulator
ANSWER: B
21. Which of the following is also known as loader?
a) Locater
b) Linker
c) Assembler
d) Compiler
ANSWER: D
22. Stack frame contains
a) Address of the function’s parameters
b) Values of the function’s parameters
c) The return addresses
d) All of the above
ANSWER: D
23. During execution of a program, a stack is used to support function calls. The group of
stack entries that pertain to one function call is called
a) Stack
b) Frame base
c) Base frame
d) Stack frame
ANSWER: D
24. The signal sent to the device from the processor to the device after receiving an
interrupt is ___________
a) Interrupt-acknowledge
b) Return signal
c) Service signal
d) Permission signal
ANSWER: A
25. When the process is returned after an interrupt service ______ should be loaded again.
i) Register contents
ii) Condition codes
iii) Stack contents
iv) Return addresses
a) i, iv
b) ii, iii and iv
c) iii, iv
d) i, ii
ANSWER: D
26. The time between the receiver of an interrupt and its service is ______
a) Interrupt delay
b) Interrupt latency
c) Cycle time
d) Switching time
ANSWER: B
27. How can the processor ignore other interrupts when it is servicing one ___________
a) By turning off the interrupt request line
b) By disabling the devices from sending the interrupts
c) BY using edge-triggered request lines
d) All of the above mentioned
ANSWER: D
28. I/O hardware contains ____________
a) Bus
b) Controller
c) I/O port and its registers
d) All of the mentioned
ANSWER: D
29. Device drivers are implemented to interface ____________
a) character devices
b) block devices
c) network devices
d) all of the mentioned
ANSWER: D
30. When hardware is accessed by reading and writing to the specific memory locations,
then it is called ____________
a) port-mapped I/O
b) controller-mapped I/O
c) bus-mapped I/O
d) none of the mentioned
ANSWER: D
31. What is Scheduling?
a) allowing a job to use the processor
b) making proper use of processor
c) all of the mentioned
d) none of the mentioned
ANSWER: A
32. Round robin scheduling falls under the category of ____________
a) Non pre-emptive scheduling
b) Pre-emptive scheduling
c) All of the mentioned
d) None of the mentioned
ANSWER: B
33. With round robin scheduling algorithm in a time shared system ____________
a) using very large time slices converts it into First come First served scheduling
algorithm
b) using very small time slices converts it into First come First served scheduling
algorithm
c) using extremely small time slices increases performance
d) using very small time slices converts it into Shortest Job First algorithm
ANSWER: A
34. In real time operating system ____________
a) all processes have the same priority
b) a task must be serviced by its deadline period
c) process scheduling can be done only once
d) kernel is not required
ANSWER: B
35. For real time operating systems, interrupt latency should be ____________
a) minimal
b) maximum
c) zero
d) dependent on the scheduling
ANSWER: A
36. VxWorks is centered around ____________
a) wind microkernel
b) linux kernel
c) unix kernel
d) none of the mentioned
ANSWER: A
37. Which of the following provides a low-level method of debugging software?
a) high-level simulator
b) low-level simulator
c) onboard debugger
d) cpu simulator
ANSWER: C
38. Which command takes the object file and searches library files to find the routine
calls?
a) simulator
b) emulator
c) debugger
d) linker
ANSWER: D
39. Which of the following gives the final control to the programmer?
a) linker
b) compiler
c) locater
d) simulator
ANSWER: A
40. Semaphore is a/an _______ to solve the critical section problem.
a) hardware for a system
b) special program for a system
c) integer variable
d) none of the mentioned
ANSWER: C
41. What are the two atomic operations permissible on semaphores?
a) wait
b) stop
c) hold
d) none of the mentioned
ANSWER: A
42. The signal operation of the semaphore basically works on the basic _______ system
call.
a) continue()
b) wakeup()
c) getup()
d) start()
ANSWER: B
43. In a multiprogramming environment __________
a) the processor executes more than one process at a time
b) the programs are developed by more than one person
c) more than one process resides in the memory
d) a single user can execute many programs at the same time
ANSWER: C
44. Increasing RAM of a computer typically improves performance because
a) Virtual memory increases
b) Larger RAMs are faster
c) Fewer page faults occur
d) Fewer segmentation faults occur
ANSWER: C
45. Virtual memory is
a) Large secondary memory
b) Large main memory
c) Illusion of large main memory
d) None of the above
ANSWER: C
46. While executing main program, if two or more interrupts occur, then the sequence of
appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt
ANSWER: D
47. The problem of priority inversion can be solved by ____________
a) priority inheritance protocol
b) priority inversion protocol
c) both priority inheritance and inversion protocol
d) none of the mentioned
ANSWER: A
48. Which mode of the Intel 8253 timer can generate a square wave?
a) mode 1
b) mode 2
c) mode 3
d) mode 4
ANSWER: D
49. Which of the following is mode 0 in 8253?
a) interrupt on start count
b) interrupt for wait statement
c) interrupt on terminal count
d) no interrupt
ANSWER: C
50. NMI stands for
a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none of the mentioned
ANSWER: A
