TM

This X24C04 device has been acquired by

IC MICROSYSTEMS from Xicor, Inc.
ICmic
IC MICROSYSTEMS

4K X24C04 512 x 8 Bit

2
Serial E PROM

FEATURES DESCRIPTION
•2.7V to 5.5V Power Supply The X24C04 is a CMOS 4096 bit serial E PROM,
2

•Low Power CMOS internally organized 512 x 8. The X24C04 features a

—Active Read Current Less Than 1 mA serial interface and software protocol allowing
—Active Write Current Less Than 3 mA operation on a simple two wire bus.
—Standby Current Less Than 50 ∝A
•Internally Organized 512 x 8 The X24C04 is fabricated with Xicor’s advanced
•2 Wire Serial Interface CMOS Textured Poly Floating Gate Technology.
—Bidirectional Data Transfer Protocol The X24C04 utilizes Xicor’s proprietary DirectWrite™
•Sixteen Byte Page Write Mode cell providing a minimum endurance of 100,000 cycles
—Minimizes Total Write Time Per Byte and a minimum data retention of 100 years.
•Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
•High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
•8 Pin Mini-DIP, 8 Pin SOIC and 14 Pin SOIC
Packages

FUNCTIONAL DIAGRAM
(8) V
CC
(4) V
SS

(7) TEST
START CYCLE H.V. GENERATION
TIMING
& CONTROL
(5) SDA START
STOP
LOGIC

CONTROL
LOGIC

SLAVE ADDRESS 2
REGISTER XDEC E PROM
(6) SCL LOAD INC 32 X 128
+COMPARATOR

(3) A 2 WORD
(2) A 1 ADDRESS
COUNTER
(1) A 0

R/W YDEC

8
CK D
OUT
PIN DATA REGISTER

D
OUT
ACK 3839 FHD F01

DirectWrite™ is a trademark of Xicor, Inc.

© Xicor, 1991 Patents Pending Characteristics subject to change without notice

1
3839-1
X24C04

PIN DESCRIPTIONS PIN CONFIGURATION

Serial Clock (SCL)

The SCL input is used to clock all data into and out of the DIP/SOIC
device.

A 1 8
Serial Data (SDA) 0 V
CC
A 2 7
SDA is a bidirectional pin used to transfer data into and out 1
X24C04 TEST
of the device. It is an open drain output and may be A 3 6 SCL
2
wire-ORed with any number of open drain or open V 4 5 SDA
SS
collector outputs.
3839 FHD F02
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-Up
Resistor selection graph at the end of this data sheet. SOIC

Address (A0) NC 1 14 NC
A0 is unused by the X24C04, however, it must be tied to VSS 2 13
A
to insure proper device operation. 0 V
CC
A 3 12
1
TEST
NC 4 X24C04 11 NC
Address (A1, A2)
A 5 10
The Address inputs are used to set the appropriate bits of 2 SCL
V 6 9 SDA
the seven bit slave address. These inputs can be used SS

static or actively driven. If used statically they must be tied to NC 7 8 NC

VSS or VCC as appropriate. If driven they must be
driven to VSS or to VCC. 3839 FHD F03

PIN NAMES
Symbol Description
A0–A2 Address Inputs
SDA Serial Data
SCL Serial Clock
TEST Hold at VSS
VSS Ground
VCC Supply Voltage
NC No Connect
3839 PGM T01

2
X24C04

DEVICE OPERATION
Clock and Data Conventions
The X24C04 supports a bidirectional bus oriented protocol. Data states on the SDA line can change only during SCL
The protocol defines any device that sends data LOW. SDA state changes during SCL HIGH are re-
onto the bus as a transmitter, and the receiving device as served for indicating start and stop conditions. Refer to
the receiver. The device controlling the transfer is a Figures 1 and 2.
master and the device being controlled is the slave. The
master will always initiate data transfers, and provide Start Condition
the clock for both transmit and receive operations. All command are preceded by the start condition, which
Therefore, the X24C04 will be considered a slave in all is a HIGH to LOW transition of SDA when SCL is
applications. HIGH. The X24C04 continuously monitors the SDA and SCL
lines for the start condition and will not respond to
any command until this condition has been met.

Figure 1. Data Validity

SCL

SDA

DATA STABLE DATA

CHANGE 3839 FHD F06

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT STOP BIT

3839 FHD F07

3
X24C04

The X24C04 will respond with an acknowledge after

Stop Condition recognition of a start condition and its slave address.
All communications must be terminated by a stop condi-
If the device and a write operation have been selected, the
tion, which is a LOW to HIGH transition of SDA when SCL
X24C04 will respond with an acknowledge after the
is HIGH. The stop condition is also used by the X24C04 to receipt of each subsequent eight bit word.
place the device in the standby power mode after a read
sequence. A stop condition can only be issued after the In the read mode the X24C04 will transmit eight bits of data,
transmitting device has released the bus. release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop
Acknowledge condition is generated by the master, the X24C04
Acknowledge is a software convention used to indicate will continue to transmit data. If an acknowledge is not
successful data transfer. The transmitting device, either detected, the X24C04 will terminate further data transmissions
master or slave, will release the bus after transmitting eight
The master must then issue a stop condition to return the
bits. During the ninth clock cycle the receiver will
X24C04 to the standby power mode and place the device
pull the SDA line LOW to acknowledge that it received the into a known state.
eight bits of data. Refer to Figure 3.

Figure 3. Acknowledge Response From Receiver

SCL FROM
MASTER 1 8 9

DATA
OUTPUT
FROM
TRANSMITTER

DATA
OUTPUT
FROM
RECEIVER

START ACKNOWLEDGE
3839 FHD F08

4
X24C04

DEVICE ADDRESSING The last bit of the slave address defines the operation to be
performed. When set to one a read operation is
Following a start condition the master must output the selected, when set to zero a write operation is selected.
address of the slave it is accessing. The most significant
four bits of the slave are the device type identifier (see Following the start condition, the X24C04 monitors the
Figure 4). For the X24C04 this is fixed as 1010[B]. SDA bus comparing the slave address being transmitted
with its slave address (device type and state of A1
Figure 4. Slave Address and A2 inputs). Upon a correct compare the X24C04
outputs an acknowledge on the SDA line. Depending on the
HIGH state of the R/W bit, the X24C04 will execute a read
ORDER
DEVICE TYPE DEVICE WORD or write operation.
IDENTIFIER ADDRESS ADDRESS
WRITE OPERATIONS
1 0 1 0 A2 A1 A0 R/W
Byte Write
For a write operation, the X24C04 requires a second
3839 FHD F09 address field. This address field is the word address,
comprised of eight bits, providing access to any one of the
512 words of memory. Upon receipt of the word address
The next two significant bits address a particular device. A the X24C04 responds with an acknowledge, and awaits the
system could have up to four X24C04 devices on the next eight bits of data, again responding with an
bus (see Figure 10). The four addresses are defined by the acknowledge. The master then terminates the transfer by
state of the A1 and A2 inputs. generating a stop condition, at which time the X24C04
begins the internal write cycle to the nonvolatile memory.
The next bit of the slave address is an extension of the While the internal write cycle is in progress the X24C04
array’s address and is concatenated with the eight bits
inputs are disabled, and the device will not respond to any
of address in the word address field, providing direct access requests from the master. Refer to Figure 5 for the
to the whole 512 x 8 array. address, acknowledge and data transfer sequence.

Figure 5. Byte Write

S
T SLAVE WORD S
BUS ACTIVITY: A ADDRESS ADDRESS DATA T
MASTER R O
T P

SDA LINE S P
A A A
BUS ACTIVITY: C C C
X24C04 K K K
3839 FHD F10

5
X24C04

It should be noted that the ninth clock cycle of the read

Page Write operation is not a “don’t care.” To terminate a read
The X24C04 is capable of a sixteen byte page write
operation. It is initiated in the same manner as the byte operation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
write operation, but instead of terminating the write cycle after
the first data word is transferred, the master can clock cycle and then issue a stop condition.

transmit up to fifteen more words. After the receipt of each

word, the X24C04 will respond with an acknowledge. Flow 1. ACK Polling Sequence

After the receipt of each word, the four low order address bits
are internally incremented by one. The high order five WRITE OPERATION
COMPLETED
bits of the address remain constant. If the master should ENTER ACK POLLING
transmit more than sixteen words prior to generating the
stop condition, the address counter will “roll over” and the
previously written data will be overwritten. As with the byte ISSUE
write operation, all inputs are disabled until completion of the START
internal write cycle. Refer to Figure 6 for the address,
acknowledge and data transfer sequence.
ISSUE SLAVE
ISSUE STOP
Acknowledge Polling ADDRESS AND R/W = 0
The disabling of the inputs can be used to take advan- tage
of the typical 5 ms write cycle time. Once the stop
condition is issued to indicate the end of the host’s write ACK NO
operation the X24C04 initiates the internal write cycle. RETURNED?

ACK polling can be initiated immediately. This involves

YES
issuing the start condition followed by the slave address
for a write operation. If the X24C04 is still busy with the write NEXT
operation no ACK will be returned. If the X24C04 NO
OPERATION
has completed the write operation an ACK will be A WRITE?
returned and the host can then proceed with the next
read or write operation. Refer to Flow 1. YES

READ OPERATIONS ISSUE BYTE ISSUE STOP

ADDRESS
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the
slave address is set to a one. There are three basic read
operations: current address read, random read and PROCEED PROCEED
sequential read.
3839 FHD F12

Figure 6. Page Write

S
T SLAVE WORD S
BUS ACTIVITY: A ADDRESS ADDRESS (n) DATA n DATA n+1 DATA n+15 T
MASTER R O
T P

SDA LINE S P
A A A A A
BUS ACTIVITY: C C C C C
X24C04 K K K K K

NOTE: In this example n = xxxx 000 (B); x = 1 or 0 3839 FHD F11

6
X24C04

Current Address Read Random Read

Internally the X24C04 contains an address counter that Random read operations allow the master to access any
maintains the address of the last word accessed, memory location in a random manner. Prior to issuing
incremented by one. Therefore, if the last access (either a the slave address with the R/W bit set to one, the master
read or write) was to address n, the next read operation must first perform a “dummy” write opera-
would access data from address n + 1. Upon receipt of the tion. The master issues the start condition, and the slave
slave address with the R/W bit set to one, the address followed by the word address it is to read.
X24C04 issues an acknowledge and transmits the eight bit After the word address acknowledge, the master
word. The read operation is terminated by the master; immediately reissues the start condition and the slave
by not responding with an acknowledge and by issuing a address with the R/W bit set to one. This will be followed by
stop condition. Refer to Figure 7 for the sequence of an acknowledge from the X24C04 and then by the
address, acknowledge and data transfer. eight bit word. The read operation is terminated by the
master; by not responding with an acknowledge and by
issuing a stop condition. Refer to Figure 8 for the
address, acknowledge and data transfer sequence.

Figure 7. Current Address Read

S
T SLAVE S
BUS ACTIVITY: A ADDRESS DATA T
MASTER R O
T P
SDA LINE S P
A
BUS ACTIVITY: C
X24C04 K
3839 FHD F13

Figure 8. Random Read

S S
T SLAVE WORD T SLAVE S
BUS ACTIVITY: A ADDRESS ADDRESS n A ADDRESS DATA n T
MASTER R R O
T T P

SDA LINE S S P
A A A
BUS ACTIVITY: C C C
X24C04 K K K
3839 FHD F14

7
X24C04

The data output is sequential, with the data from address n

Sequential Read
followed by the data from n + 1. The address counter
Sequential Read can be initiated as either a current
address read or random access read. The first word is for read operations increments all address bits, allowing the
entire memory contents to be serially read during
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating it one operation. At the end of the address space (address 511),
the counter “rolls over” to address 0 and the
requires additional data. The X24C04 continues to out- put
data for each acknowledge received. The read X24C04 continues to output data for each acknowledge
received. Refer to Figure 9 for the address, acknowledge
operation is terminated by the master; by not responding with
an acknowledge and by issuing a stop condition. and data transfer sequence.

Figure 9. Sequential Read

SLAVE S
BUS ACTIVITY: ADDRESS A A A T
MASTER C C C O
K K K P

SDA LINE P
A
BUS ACTIVITY: C
X24C04 K DATA n DATA n+1 DATA n+2 DATA n+x
3839 FHD F16

Figure 10. Typical System Configuration

V
CC

PULL-UP
RESISTORS

SDA
SCL

MASTER SLAVE MASTER

SLAVE MASTER
TRANSMITTER/ TRANSMITTER/ TRANSMITTER/
RECEIVER TRANSMITTER
RECEIVER RECEIVER RECEIVER
3839 FHD F17

8
X24C04

ABSOLUTE MAXIMUM RATINGS* *COMMENT

Temperature Under Bias .................. –65°C to +135°C Stresses above those listed under “Absolute Maximum
Storage Temperature ....................... –65°C to +150°C Ratings” may cause permanent damage to the device.
Voltage on any Pin with This is a stress rating only and the functional operation of the
Respect to V SS ............................ –1.0V to +7.0V device at these or any other conditions above those
D.C. Output Current ............................................ 5 mA indicated in the operational sections of this specification is not
Lead Temperature (Soldering, implied. Exposure to absolute maximum rating condition
10 Seconds) ............................. 300°C for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature Min. Max. Supply Voltage Limits
Commercial 0°C 70°C X24C04 4.5V to 5.5V
Industrial –40°C +85°C X24C04-3.5 3.5V to 5.5V
Military –55°C +125°C X24C04-3 3V to 5.5V
3836 PGM T02
X24C04-2.7 2.7V to 5.5V
3836 PGM T03
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified)
Limits
Symbol Parameter Min. Max. Units Test Conditions
ICC1 VCC Supply Current (Read) 1 SCL = VCC x 0.1/VCC x 0.9 Levels
ICC2 VCC Supply Current (Write) 3 mA @ 100 KHz, SDA = Open, All Other
Inputs = GND or VCC – 0.3V
ISB1(1) VCC Standby Current 150 ∝A SCL = SDA = VCC – 0.3V, All Other
Inputs = GND or VCC, VCC = 5.5V
ISB2(1) VCC Standby Current 50 ∝A SCL = SDA = VCC – 0.3V, All Other
Inputs = GND or VCC,
VCC = 3V
ILI Input Leakage Current 10 ∝A VIN = GND to VCC
ILO Output Leakage Current 10 ∝A VOUT = GND to VCC
VlL(2) Input Low Voltage –1.0 VCC x 0.3 V
VIH(2) Input High Voltage VCC x 0.7VCC + 0.5 V
VOL Output Low Voltage 0.4 V IOL = 3 mA
3839 PGM T03

CAPACITANCE TA = 25°C, f = 1.0MHz, VCC = 5V

Symbol Parameter Max. Units Test Conditions
CI/O(3) Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN(3) Input Capacitance (A0, A1, A2, SCL) 6 pF VIN = 0V
3839 PGM T05

Notes:(1)Must perform a stop command prior to measurement.

(2)VIL min. and VIH max. are for reference only and are not tested.
(3)This parameter is periodically sampled and not 100% tested.

9
X24C04

A.C. CONDITIONS OF TEST EQUIVALENT A.C. LOAD CIRCUIT

5.0V
Input Pulse Levels VCC x 0.1 to VCC x 0.9
1533Ο
Input Rise and
Fall Times 10 ns Output
Input and Output 100pF
Timing Levels VCC x 0.5
3839 PGM T02

A.C. CHARACTERISTICS (Over recommended operating conditions unless otherwise specified) Read
& Write Cycle Limits
Symbol Parameter Min. Max. Units
fSCL SCL Clock Frequency 0 100 KHz
TI Noise Suppression Time 100 ns
Constant at SCL, SDA Inputs
tAA SCL Low to SDA Data Out Valid 0.3 3.5 ∝s
tBUF Time the Bus Must Be Free Before a 4.7 ∝s
New Transmission Can Start
tHD:STA Start Condition Hold Time 4.0 ∝s
tLOW Clock Low Period 4.7 ∝s
tHIGH Clock High Period 4.0 ∝s
tSU:STA Start Condition Setup Time 4.7 ∝s
(for a Repeated Start Condition)
tHD:DAT Data In Hold Time 0 ∝s
tSU:DAT Data In Setup Time 250 ns
tR SDA and SCL Rise Time 1 ∝s
tF SDA and SCL Fall Time 300 ns
tSU:STO Stop Condition Setup Time 4.7 ∝s
tDH Data Out Hold Time 300 ns
3839 PGM T06
POWER-UP TIMING
Symbol Parameter Max. Units
t
PUR
(4) Power-up to Read Operation 1 ms
tPUW(4) Power-up to Write Operation 5 ms
3839 PGM T07
Bus Timing
t t t t
F HIGH LOW R

SCL

t t t t t
SU:STA HD:STA HD:DAT SU:DAT SU:STO

SDA IN

t t t
AA DH BUF

SDA OUT

3839 FHD F04

Notes:(4) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These
parameters are periodically sampled and not 100% tested.

10
X24C04

Write Cycle Limits

(5)
Symbol Parameter Min. Typ. Max. Units
tWR
(6) Write Cycle Time 5 10 ms
3839 PGM T08

The write cycle time is the time from a valid stop bus interface circuits are disabled, SDA is allowed to remain
condition of a write sequence to the end of the internal high, and the device does not respond to its slave
erase/program cycle. During the write cycle, the X24C04 address.

Write Cycle Timing

SCL

SDA 8th BIT ACK

WORD n t
WR
STOP START X24C04
CONDITION CONDITION ADDRESS
3839 FHD F05

Notes: (5) Typical values are for TA = 25°C and nominal supply voltage (5V).
(6) tWR is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
device requires to perform the internal write operation.

Guidelines for Calculating Typical SYMBOL TABLE

Values of Bus Pull-Up Resistors WAVEFORM INPUTS OUTPUTS

120 V Must be Will be

R CC MAX steady steady
MIN = =1.8KΟ
100 I
OL MIN
RESISTANCE (KΟ)

t May change Will change

R
80 R
MAX = from Low to from Low to
C
BUS High High
60 MAX.
RESISTANCE May change Will change
from High to from High to
40
Low Low
20 MIN. Don’t Care: Changing:
RESISTANCE Changes State Not
0 Allowed Known
0 20 40 60 80100120
Center Line
BUS CAPACITANCE (pF) N/A is High
3839 FHD F18 Impedance

11
X24C04

PACKAGING INFORMATION

8-LEAD PLASTIC SMALL OUTLINE 8-LEAD PLASTIC DUAL

GULL WING PACKAGE TYPE S IN-LINE PACKAGE TYPE P

0.430 (10.92)
0.360 (9.14)

0.092 (2.34)
0.150 (3.80) 0.228 (5.80) DIA. NOM.
0.158 (4.00) 0.244 (6.20) 0.255 (6.47)
0.245 (6.22)
PIN 1 INDEX
PIN 1 INDEX
PIN 1
PIN 1

0.300 0.060 (1.52)

(7.62) REF. 0.020 (0.51)
0.014 (0.35)
0.019 (0.49)
HALF SHOULDER
WIDTH ON ALL END
0.188 (4.78) PINS OPTIONAL
0.197 (5.00)

0.140 (3.56)
(4X) 7° SEATING 0.130 (3.30)
PLANE

0.150 (3.81) 0.020 (0.51)

0.053 (1.35)
0.125 (3.18) 0.015 (0.38)
0.069 (1.75)
0.062 (1.57)
0.058 (1.47)
0.004 (0.19)
0.050 (1.27) 0.010 (0.25) 0.110 (2.79) 0.020 (0.51)
0.090 (2.29) 0.016 (0.41)

0.010 (0.25)
X 45°
0.020 (0.50) 0.325 (8.25)
0.015 (0.38)
0.300 (7.62)
MAX.

0° – 8°
0.0075 (0.19)
0.010 (0.25)
0°
0.027 (0.683) 15°
0.037 (0.937) TYP. 0.010 (0.25)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

12
X24C04

PACKAGING INFORMATION

14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

0.150 (3.80) 0.228 (5.80)

0.158 (4.00) 0.244 (6.20)

PIN 1 INDEX

PIN 1

0.014 (0.35)
0.019 (0.49)

0.336 (8.55)
0.345 (8.75)

(4X) 7°

0.053 (1.35)
0.069 (1.75)

0.004 (0.19)
0.050 (1.27)
0.010 (0.25)

0.010 (0.25)
X 45°
0.020 (0.50)

0° – 8°

0.0075 (0.19)
0.010 (0.25)

0.027 (0.683)
0.037 (0.937)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

13
X24C04

ORDERING INFORMATION
X24C04 P T G -V VCC Limits
Blank = 4.5V to 5.5V
3.5 = 3.5V to 5.5V
Device 3 = 3.0 to 5.5V
2.7 = 2.7V to 5.5V
G=RoHS Compliant Lead Free package
Blank = Standard package. Non lead free

Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C

Package
P = 8-Lead Plastic DIP
S8 = 8-Lead SOIC
S14 = 14-Lead SOIC

Part Mark Convention

X24C04 XG Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP
S8 = 8-Lead SOIC
S14 = 14-Lead SOIC
G = RoHS compliant lead free
X

Blank = 4.5V to 5.5V, 0°C to +70°C

I = 4.5V to 5.5V, –40°C to +85°C
B = 3.5V to 5.5V, 0°C to +70°C
C = 3.5V to 5.5V, –40°C to +85°C
D = 3.0V to 5.5V, 0°C to +70°C
E = 3.0V to 5.5V, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C

LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no
warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without
notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.

U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402;
4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents
pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurence.

Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

14
X24C04

8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

0.430 (10.92)
0.360 (9.14)

0.260 (6.60)
0.240 (6.10)

PIN 1 INDEX

PIN 1

0.300 0.060 (1.52)

(7.62) REF. 0.020 (0.51)

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL
0.145 (3.68)
SEATING 0.128 (3.25)
PLANE

0.150 (3.81) 0.025 (0.64)

0.125 (3.18) 0.015 (0.38)

0.065 (1.65)
0.045 (1.14)

0.110 (2.79) 0.020 (0.51)

0.090 (2.29) 0.016 (0.41)

0.325 (8.25)
0.015 (0.38)
0.300 (7.62)
MAX.

0°
TYP. 0.010 (0.25) 15°

NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS) 2.
PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

3926 FHD F01

15
X24C04

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

0.150 (3.80) 0.228 (5.80)

0.158 (4.00) 0.244 (6.20)

PIN 1 INDEX

PIN 1

0.014 (0.35)
0.019 (0.49)

0.188 (4.78)
0.197 (5.00)

(4X) 7°

0.053 (1.35)
0.069 (1.75)

0.004 (0.19)
0.050 (1.27)
0.010 (0.25)

0.010 (0.25) 0.050" TYPICAL

X 45°
0.020 (0.50)

0.050"
0° – 8° TYPICAL
0.0075 (0.19)
0.010 (0.25) 0.250"

0.016 (0.410)
0.037 (0.937)

0.030"
TYPICAL
FOOTPRINT 8 PLACES

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS)

3926 FHD F22

16
X24C04

14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

0.150 (3.80) 0.228 (5.80)

0.158 (4.00) 0.244 (6.20)

PIN 1 INDEX

PIN 1

0.014 (0.35)
0.020 (0.51)

0.336 (8.55)
0.345 (8.75)

(4X) 7°

0.053 (1.35)
0.069 (1.75)

0.004 (0.10)
0.050 (1.27)
0.010 (0.25)

0.050" Typical
0.010 (0.25)
X 45°
0.020 (0.50)

0° – 8° 0.050" Typical
0.0075 (0.19)
0.010 (0.25) 0.250"

0.016 (0.41)
0.037 (0.937)

0.030" Typical
FOOTPRINT 14 Places

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FHD F10

17
X24C04

8-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D

0.405 (10.29)
––

0.310 (7.87)
0.220 (5.59)

PIN 1
0.005 (0.13) MIN.
0.300 (7.62) 0.055 (1.40) MAX.
REF.

SEATING 0.200 (5.08)

PLANE 0.140 (3.56)

0.150 (3.81) MIN. 0.200 (5.08) 0.060 (1.52)

0.125 (3.18) 0.015 (0.38)

0.065 (1.65)
0.038 (0.97)
TYP. 0.060 (1.52)
0.110 (2.79)
0.090 (2.29)
0.023 (0.58)
TYP. 0.100 (2.54) 0.014 (0.36)
TYP. 0.017 (0.43)

0.320 (8.13)
0.290 (7.37)
TYP. 0.311 (7.90)

0°
0.015 (0.38) 15°
0.008 (0.20)

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FHD F05

18