Int. j. inf. tecnol.

(August 2022) 14(5):2389–2398

https://doi.org/10.1007/s41870-022-01001-z

ORIGINAL RESEARCH

A common-gate cascaded with cascoded self-bias common source

approach for 3.1–10.6 GHz UWB low noise amplifier
Vikram Singh1 • Nitin Kumar2 • Manoj Kumar3 • Sandeep Kumar Arya4

Received: 24 February 2022 / Accepted: 6 May 2022 / Published online: 28 May 2022
Ó The Author(s), under exclusive licence to Bharati Vidyapeeth’s Institute of Computer Applications and Management 2022

Abstract With the boom in demand of wireless devices Keywords Low noise amplifier  Low power  Self-
operating in ultra-wideband (UWB), the requirement latest cascoded  RF integrated circuit  UWB
low power design of low noise amplifier (LNA) has been
increased. This paper presents the circuit design of an
UWB LNA for 3.1–10.6 GHz wireless applications and 1 Introduction
consumes less than 10 mW of power. This LNA design
utilizes common-gate (CG) configuration with self-biased Federal Communications Commission (FCC) offers
common-source (CS) noise cancelling technique (NC) with 3.1–10.6 GHz UWB frequency range for realization of
UWB input matching with improved noise-figure (NF) wireless communication links with high data rate in the
performance. Cascoded common source (CS) topology year of 2002 [1]. This UWB consists of fourteen bands
with NC filter at the second stage is used to enhance the grouped in five band groups and each band is consisting of
NF, power-gain (S21) and bandwidth (BW) performance of 128 sub-channels. The highest emission power for these
the LNA. A parallel-series LC network is exploited for 128 sub-channels has an upper bound of -41.3 dBm/MHz.
better impedance matching between CG and cascoded CS This makes UWB suitable for many interesting wireless
stage. Simulation results of the presented LNA imple- applications to operate simultaneously and not to destruct
mented in standard 90 nm CMOS node at Vdd supply of the pre-existing links in same locality [1]. This motivates
1.0 V and attains a flat S21 response of 20.5 ± 0.5 dB and researchers and VLSI chip fabrication industries It give
simultaneously achieves NF of 2.4–3.9 dB while dissipat- reason to low-power VLSI design industries and
ing 9.28 mW of power. With the use CG input, this LNA researchers for developing reliable radio-frequency inte-
attains an UWB input (S11) and output reflection coefficient grated circuits (RF-ICs) for these applications.
(S22) of less than -10.1 dB and - 11.3 dB, correspondingly LNA as a chief module of all RF receivers require more
with great reversion isolation (S12) of less than - 113.1 dB attention to pay for it. The designing of an LNA for such a
for 3.0–12.0 GHz frequency. high frequency i.e., 3.1–10.6 GHz UWB requires meeting
many challenges like (a) input impedance matching with
50 X antennas, (b) low overall NF, (c) flat gain, (d) high
& Nitin Kumar linearity, and (e) receiver’s stability with low power con-
[email protected]
sumption [2, 3]. CS [3–6] and CG [7–9] are the two most
1
School of Electronics and Communication Engineering, frequently used UWB LNA topologies. These LNA
SMVDU, Katra, Jammu & Kashmir, India topologies have been further modified in various existing
2
Department of Electronics and Communication Engineering, literatures as shown in Fig. 1 with improved performance
GITAM, Jhajjar, Haryana, India in one or other way.
3
University School of Information, Communication & Narrow and wideband LNAs with high S21 are suitably
Technology, GGSIPU, New Delhi, India designed using CS-topology. LNAs using CS-topology for
4
Department of Electronics and Communication Engineering, 2.4 GHz UWB ISM band are proposed in [5, 10] with a
GJUST, Hisar, Haryana, India high S21 of 10.5 dB and 31.53 dB, respectively. CS with

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small chip area. CS-CG inductorless LNA with active load

for UWB applications is presented in [28]; however it is
unable to provide flat S21 for claimed 3-dB bandwidth of
4.3–8.3 GHz, also survives with small value of S12 at the
higher side of BW claimed. In order to design wideband
LNAs at low power consumption, inductorless LNA based
on inverter cell and self-FBB is adopted in [29] whereas an
inductorless differential LNA with gm-enhancement tech-
nique is implemented in [30]. In order to save overall chip
area and low power consumption CG with cross-coupled
differential LNA topology with passive feedback network
Fig. 1 Existing LNA topologies: a CG, b CS, c CS with feedback, has been utilized in [31], however its main disadvantage
d distributed LNA, and e active inductor based LNA
was its small bandwidth. CG gm-boosted LNA with FBB
noise and distortion canceling technique in differential
inductive degeneration (CSID) is proposed in [2, 11, 12]
topology is exploited in [32] to operate at lower supply
for 3.1–10.6 GHz UWB. In order to operate at low power
voltage and to get low NF with small power consumption;
levels, CSID technique with forward body bias (FBB) is
however, its bandwidth limited to 3–5 GHz and power
used in [13, 14]. CSID with self cascode current reuse
consumption is 13.8 mW.
architecture have been implemented in [15] and the
Ability to achieve UWB input matching, flat power gain
respective NF and S21, at 11.52 mw are 1.2 dB and
over the entire band of interest and low power consumption
20.10 dB. Resistive feedback CS topology is also famous
are few advantages of CG configuration which leads our
among some researchers. However NF of resistive feed-
attention towards the design of UWB CG LNA topologies.
back LNA is high as compared to CS topology. CSID with
This manuscript demonstrates the low power LNA design
RC feedback and FBB have been implemented in [16] has
using common-gate topology cascaded with self-biased CS
NF 3.04–3.48 dB. CS resistive shunt feedback is adopted
topology for ultra-wideband frequency range of
in [17] and CSID resistive shunt feedback with FBB is
3.1–10.6 GHz. The novelty of this circuit design is its self-
adopted in [18].
biased CS topology which is adopted as noise canceling
LNA with RC feedback has been implemented in [19]
stage at the second stage of LNA proposed. Starting from
for 2.4 GHz ISM-band. LNAs designed with CG configu-
the introduction in Sect. 1, the complete manuscript
rations are mostly chosen for its easy wideband input
structured in four sections. Section 2 portrayed the sug-
matching capability [7–9]. CG with resistive load topology
gested LNA design technique with input–output matching
implemented in [20] shows NF of 3.5 dB and consumes
and noise-figure analysis. Section 3 presents simulation
54.6 mW over 2.5–3.1 GHz, whereas CG-current reuse
results of the projected LNA and also presents the state-of-
technique is accepted in [21] for UWB applications. CG
art comparison of the projected LNA with the existing
distributed amplifier (DA) topologies are also preferen-
literature work and ends with conclusion of this paper in
tially used by some researchers to realize flat gain around
Sect. 4.
8–10 dB LNA for UWB [22, 23]. CS DA has been
implemented in [23] and has S21 of 8.6 ± 2 dB with
minimum NF of 5.6 dB while consuming 19.2 mW,
whereas DA implemented in [24] achieves a high S21 of
25 dB at the cost of high NF of 6.5–8 dB and high power
consumption of 176 mW. Input matching using active
inductors can also be used for wide and flat gain response
[25]. CG differential cross coupled feedforward LNA
design is implemented in [26] using active inductor (AI)
topology in order to reduce overall chip area; however it is
limited to a BW of 4.1 GHz. Not only this, the AI adds its
own noise which in turn increases NF as compared to
conventional CG-LNA. CG-CS noise canceling topology
with differential output is employed in [27] for
3.0–10.6 GHz UWB.
Inductorless LNA topology is also famous amongst few
researchers due to its low NF, low power consumption and
Fig. 2 Circuit diagram of the suggested UWB LNA

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2 Proposed LNA design For the proposed LNA designed, the calculated value of
1/gm1 is approximately equal to 31.25 X and the difference
The circuit diagram of the proposed UWB LNA shown in from the 50 X is contributed by the impedance of the
Fig. 2 is mainly consisting of four stages. At input side CG succeeding stages. Equation (1) provides a very low input
configuration is castoff for realizing a wideband LNA for quality-factor (Qin,CG), which is favourable to achieve
which S11 can easily be configured by choosing 1/gm1 wider bandwidth. For a given source resistance Rs can be
approximately equal to 50 X. CG stage is then followed at the quality-factor (Qin,CG) expressed as [2]
first by a self-biased CS cascode stage and then by another
xCgs1 Rs
CS cascode stage for further NF and S21 enhancement over Qin;CG  ð2Þ
the entire UWB. A common-drain (CD) buffer stage has 2
been casted at the output stage for flawless output impe- Maximum power transfer of the signal received at the
dance matching (S22) at the load end. Figure 3 shows the antenna to load end is also important in an LNA design.
expected frequency response of CG-CS-CS stages. The Implementation of network consisting of parallel-series LC
element values for the proposed LNA design are listed in tank between CG first stage and the following casoded CS
Table 1. stages fulfill requirement. In second stage, self-biased CS
The LNA is biased using a power supply of 1.0 V in configuration is employed using transistor M2 and M3. The
which at first stage the transistor M1 is configured as CG gate of M2 and M3 is biased using Vg2,3 through a biasing
for achieving wideband input matching. Vg1, the gate bias resistor R1 of 5 KX. The width of the transistor M2 and M3
voltage set to 0.34 V near to the threshold voltage of adjusted such that the unloaded voltage gain of this closely
transistor M1. The inductor Ls1 connected at the source of resembles to the transfer function of an all-pass filter with a
input CG stage with gate-to-source parasitic capacitance very small gain as shown in figure. In this circuit, common
(Cgs1) of M1 is primary deciding factor of the input reso- mode signal is applied to the gate terminal of both NMOS
nance frequency. transistor M2 and M3. The unloaded voltage of this stage is
The input impedance of the LNA can be matched to the given by
impedance of receiver antenna by setting transconductance sCgs3  gm2
(gm1) of CG transistor M1 equal to 20 mS. Ignoring the Av;unloaded ¼ 1
ð3Þ
sCgs3 þ ro2
effect of ro1 and the load impedance connected to the
output of CG-stage, the input impedance of the CG-stage where, Cgs3 is total parasitic capacitance between gate to
alone can be expressed as source terminal of transistor M3, gm2 is the transconduc-
  1 tance and ro2 is the drain to source channel resistance of
1
Zin;CG  gm1 þ j xCgs1  ð1Þ transistor M2. The difference in the signals applied at gate
xLs1 and source terminal of transistor M3 is then amplified by
NMOS transistor M3. This topology helps in cancelling the
gate noise added by the CS cascoded configuration.
The gain provided by the topology formed by transistor
pair M2 and M3 is very small. Therefore the output of M3 is
cascoded with CG stage transistor M4 to increase the
bandwidth and S21, the output of which is tuned by
inductor Ld4 and gate to drain parasitic, Cgd4 of M4. For
further improvement in the S21 and bandwidth, another CS
cascode configuration using transistors M5 and M6 is cas-
caded with it. The input to the buffer stage is fed through a
tuned parallel LC tank resonating at 1/H(Ld6 (Cgd6-
? Cgd7)), where Ld6 is inductor connecting at the drain of
M6, and (Cgd6 ? Cgd7) is total gate to drain parasitic
capacitances of the transistors M6 and M7, respectively.
The last stage is the buffer stage designed using transistor
M7 and M8. The output is taken from the voltage follower
designed using transistor M7, whereas M8 behaves as load
impedance.
Fig. 3 Bandwidth and gain enhancement technique exploited in
proposed LNA a reduced topology of each stage, b expected
frequency response of the design

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Table 1 Component values and

Resistors (KX) Inductors (nH) Capacitors (pF) Transistors W (lm)/L (lm)
aspect ratios of transistors used
in proposed LNA design R2 5.0 Ls1 6.0 C1 3.0 M1 60/0.09
R5 5.0 Ld1 8.5 C2 2.0 M2 95/0.09
R7 5.0 Ld4 6.5 C3 2.0 M3 30/0.09
R8 5.0 Ld6 2.0 C4 2.0 M4 38/0.09
M5 160/0.09
M6 60/0.09
M7, M8 10/0.09

2.1 Input and output impedance matching

In current section, proposed LNA design is investigated for

input and output impedance matching. Figure 4 shows the
small signal model of CG first stage.
Neglecting the influence of input coupling capacitor C1,
the net input impedance (Zin) can be approximated as
 
jxLs1 ro1 þ ðgmb1 ro1 þ 1ÞZload ðxÞ
Zin ðxÞ  jj
1  x2 Ls1 Cgs1 ðgm1 þ gmb1 Þro1 þ 1
ro1 þ ðgmb1 ro1 þ 1ÞZload ðxÞ Fig. 5 Small-signal ac equivalent of the self-bias CS stage

ðgm1 þ gmb1 Þro1 þ 1
1
ð4Þ ro2 þ jxCgs3t
Zin2 ðxÞ ¼ 2
ð6Þ
x Cgs2 Cgs3t þ jX
where, gmb1 is the back-gate transconductance of transistor  1   
M1 and Zload(x) is the overall impedance considered at the where X ¼ x ro2 Cgs2 þ Cgs3t þ gm2 Cgs3t and Cgs3t-
output of transistor M1. Practically, Zload(x) includes the = Cgd2 ? Cgs3 and gm2 is the transconductance of tran-
total input impedances of successive stages of the proposed sistor M2. For an efficient signal power flow from antenna
LNA design. The contribution of input-impedance of suc- to the successive stages over the entire UWB frequency
cessive stage plays an important role in deciding the overall range, S11 of B -10 dB is a harsh condition and can be
input matching performance of the projected LNA design. evaluated as
Therefore Zload(x) can be expressed as
S11 dB ¼ 20 log10
 1 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
Zload ðxÞ ¼ jxCgd1 jjðjxLd1 Þjj
 ðgmb1 ro1 þ 1Þ2 ðZin2 ðxÞÞ2 þðro1  Rs ððgm1 þ gmb1 Þro1 þ 1ÞÞ2
jxL12 þ ðjxC2 Þ1 þR1 jjZin2 ðxÞ ð5Þ ðgmb1 ro1 þ 1Þ2 ðZin2 ðxÞÞ2 þðro1 þ Rs ððgm1 þ gmb1 Þro1 þ 1ÞÞ2
 Zin2 ðxÞ   10dB
ð7Þ
where Zin2(x) can be evaluated from small signal equiva-
lent of self-biased CS-stage shown in Fig. 5 as The S22 of the proposed LNA can be estimated by cal-
culating output impedance eyeing into source terminal the
output buffer transistor M7 keeping its input of gate ter-
minal as zero and can be expressed as
1 þ jxZ6 ðxÞCgs7 1 þ jxZ6 ðxÞCgs7
Zout ðxÞ ¼ jjro7 jjro8 
gm7 þ jxCgs7 gm7 þ jxCgs7
ð8Þ
where, Z6(x) is considered as the impedance of the LC tank
arrangement of Ld6 with (Cgd6 ? Cgd7), whereas Cgd6, Cgs7
and gm7 are the respective gate-drain, gate-source parasitic
capacitances and the transconductance of M6 and M7.

Fig. 4 Small-signal ac equivalent circuit of the input CG stage

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2.2 Noise figure analysis small signal models as shown in Fig. 4 and Fig. 5,
respectively and can be expressed as
The CG configuration is suitable for wideband matching Zin1 ðxÞ  Zin ðxÞ ð11Þ
but inferior NF performance as compared to the CS
    1
topology however this can be improved by cascading gain- Zout1 ðxÞ ¼ ro1 jjg1
mb1 jj jxLd1 jj jxCgd1
boosting CS stages. Also the voltage-gain of the single CG 
stage is not sufficiently high to achieve acceptable S21. To þ jxL12 jjðjxC2 Þ1 ð12Þ
get low NF with high S21 from suggested LNA design,   1
cascoded CS stages are cascaded with the CG input stage. Zout2 ðxÞ ¼ ro3 þ ð1 þ gm3 ro3 Þ ro1 jj jxCgd3t
  1 ð13Þ
That’s why we cannot simply ignore the gain and noise
 gm3 ro3 ro1 jj jxCgd3t
performance of the CS cascode stage. For NF analysis, it is

supposed that each stage is acting as alone and each stage
½ðgm1 þ gmb1 Þro1 þ 1 jxLd1 jjðjxCgd1 Þ1
in the proposed LNA design, individually contributes to the AV 1 ¼  ð14Þ
total noise factor of the receiver circuit. The main contri- ro1 þ ðgmb1 ro1 þ 1Þ  jxLd1 jjðjxCgd1 Þ1
bution of noise is due the initial CG-CS stage and suc-
cessive stages would contribute very little to the total noise and
factor (NF) of the complete LNA circuit. For this purpose, jxCgs3t  gm2
noise equivalent small signal model of the proposed LNA AV 2 ¼ 1
ð15Þ
jxCgs3t þ ro2
design is shown in Fig. 6. So, noise factor of the proposed
2
In Fig. 6, the term Vn;Rs ¼ 4kTRs Df represents thermal
LNA design is approximated here using ‘‘Friss’ equation’’
as noise due to antenna source resistance Rs. For all-purposes,
NF2  1 NF3  1 the terms i2n;d and i2n;g represents channel induced and gate
NF ffi NF1 þ þ ð9Þ
AP1 AP1 AP2 induced thermal noise of the respective NMOS transistor
where, NF1, NF2, and NF3 are the noise factors of the CG used and is given by i2n;g ¼ 4kTdgg Df and i2n;d ¼ 4kTcgd0 Df
stage, self-bias CS stage and the casoded transistor M4 with, k as Boltzmann constant, T as temperature in Kelvin,
stage of the proposed LNA respectively. AP1 and AP2 are d is the coefficient of induced gate noise, gg equivalent gate
.
the available power gain of CG stage and self-bias CS stage conductance whereas gg is given by gg ¼ x2 Cgs 2
5gd0 , Df
respectively. These can be expressed as follows:
as noise-bandwidth, c is the coefficient of channel-induced
jZin1 ðxÞj2 Rs thermal noise and gd0 is the zero-bias drain conductance of
AP1 ¼ 2
 A2V1  and AP2 the device.. In Eq. 9, NF1, NF2 and NF3 can be expressed
jRs þ Zin1 ðxÞj jZout1 ðxÞj
jZin2 ðxÞj2 Zout1 ðxÞ as
¼ 2
 A2V2  ð10Þ
jZout1 ðxÞ þ Zin2 ðxÞj Zout2 ðxÞ

where Zin1 ðxÞ, Zout1 ðxÞ,Zin2 ðxÞ and Zout2 ðxÞ are the input
and output impedances and Av1 and Av2 unloaded voltage
gains of CG stage and self-bias CS stage, respectively.
Available power gains are calculated using their respective

Fig. 6 Noise equivalent circuit

of the presented CG cascaded
self-biased CS LNA

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2
i2n;out;g1 þ i2n;out;d1 c g2m3 þ jxðCgs3t þ ðCgs2 þ gm2 Cgs3t ÞZout1 ðxÞ
NF1 ¼ 1 þ ; NF2 i2n;out;d2 ¼
i2n;out;Rs ag2m2 gm3 jZout1 ðxÞj
2
i2n;out;g2 þ i2n;out;d2 þ i2n;out;g3 þ i2n;out;d3 ðgm2 gm3  x2 Cgs2 Cgs3t ÞZout1 ðxÞ þ jxCgs3t ð1 þ gm2 Zout1 ðxÞÞ
¼1þ ; and NF3   2 2
i2n;out;Zout1 gm3  x2 Cgs2 Cgs3t þ jxCgs3t ð1 þ gm2 Zout1 ðxÞÞ

i2n;out;g4 þ i2n;out;d4  i2n;out;Zout1

¼1þ ð24Þ
i2n;out;Zout2
ð16Þ adx2 Cgs4
2
jZout2 ðxÞj 2
i2n;out;g4 ¼  in;out;Zout2 ð25Þ
5gm4
where, i2n;out;Rs ,i2n;out;gx
and i2n;out;dx
are the output short circuit 2
root-mean-square currents due to source resistance Rs, gate c 1 þ jxCgs4 Zout2 ðxÞ
i2n;out;g4 ¼  i2n;out;Zout2 ð26Þ
induce noise of Mx and channel induced thermal noise of agm4 jZout2 ðxÞj3
Mx, respectively, for x = 1,2,3, and 4. The terms i2n;out;Zout1 and
and i2n;out;Zout2 is the output short circuit root-mean-square
g2m4 jZout2 ðxÞj2
current due to output impedances Zout1 and Zout2, respec- i2n;out;Zout2 ¼   2
2
 Vn;out;Zout2
tively. These can be articulated as 1 þ gm4 þ jxCgs4 Zout2 ðxÞ
ð27Þ
i2n;out;Rs ¼
ðgm1 þ gmb1 Þ2 2
   2
 Vn;Rs
Z ðxÞ 1 1 1 1
R2s 1 þ Zd1P
d1s
ðxÞ Rs þ Zs1 ðxÞ þ g m1 þ g mb1 þ Rs þ Zs1 ðxÞ g mb1 Z d1s ðxÞ

ð17Þ 3 Results and discussions

adx2 Cgs1
2
Rs The proposed LNA is designed in 90 nm CMOS process
i2n;out;g1 ¼  i2n;out;Rs ð18Þ
5gm1 and simulated for 3–12 GHz UWB frequency range. The
" # NF and S-parameter performance is shown in Fig. 7. It is
cgm1 R2s observed that, NF can be reduced by selecting large sized
i2n;out;d1 ¼ 1þ  i2n;out;Rs
aRs ðgm1 þ gmb1 Þ2 jZs1 ðxÞj2 CG transistor, and the amount of difference from 50 X
ð19Þ input matching can compensated by the input impedance of
subsequent stage in the receiver chain. A further decrease
g2m2 g2m3 in NF is observed here due to addition of source-bulk
i2n;out;Zout1 ¼ 2
g2m2 þ jxðCgs2 þ gm2 Cgs3t ÞZout1 ðxÞ transconductance gmb1 in the denominator of Eqs. (17–19).
2
 Vn;Zout1 ð20Þ It is observed that a minimum NF of 2.4 dB is achieved
throughout the UWB with a maximum of 3.9 dB at
adx2 Cgs2
2
jZout ðxÞj 2 12.0 GHz. It achieved a flat S21 response of 20.5 ± 0.5 dB
i2n;out;g2 ¼  in;out;Zout1 ð21Þ
5gm2

c 1 þ x2 Cgs2
2
jZout1 ðxÞj2
i2n;out;d2 ¼
agm2 jZout1 ðxÞj
ðg2m3 þ x ðCgs3t þ ðCgs2 þ Cgs3t gm2 ÞjZout1 ðxÞj2 ÞÞ 2
2
  in;out;Zout1
gm3 ð1 þ ðCgs3t gm2 þ jxCgs2 ÞZout1 ðxÞ
ð22Þ
2
adx2 Cgs3 1 þ ðgm2 jxCgs2 ÞZout1 ðxÞ
i2n;out;g3 ¼
5gm3 g2m2

g2m3 þ x2 ðCgs3t þ ðCgs2 þ Cgs3t gm2 ÞjZout1 ðxÞj2
 2
 i2n;out;Zout1
g2m3 þ jxCgs3t þ jxðCgs2 þ jxCgs3t þ Cgs3t gm2 ÞZout1 ðxÞ
ð23Þ

Fig. 7 NF and S-parameter frequency response

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Fig. 8 Effect of process variation on a NF, b S11, c S21

Fig. 9 Effect of power supply variation on a NF, b S11, c S21

Fig. 10 Effect of temperature variation on a NF, b S11, c S21

for a frequency range of 3.6–11.6 GHz, with S11 of less varying from 2.1 to 4.8 dB, S11 is varying from - 20.1 to
than -10.1 dB and S22 of less than -11.3 dB throughout the - 8.7 dB, and S21 is varying from 12.6 to 24.5 dB for a
complete UWB. range 3–12.0 GHz. Figure 10 shows the effect of temper-
The proposed LNA is also analysed to confirm the sta- ature variation on NF, S11 and S21. It has been observed
bility against process variation at slow-slow (SS), fast–fast that with a temperature variation from - 25 °C to 50 °C,
(FF) and nominal (NN) corners with, supply voltage and NF is varying from 2.1 to 4.7 dB, S11 is varying from
temperature variation. The threshold voltages considered - 19.8 to - 9.5 dB, and S21 is varying from 13.4 to
are 377 mV, 437 mV and 408 mV for FF, SS, and NN 24.5 dB for a range 3–12.0 GHz.
corners respectively. It is observed from the Fig. 8, that for Linear amplification of the input signal received from
4.0–10.6 GHz UWB, noise-figure, S11, S21 has minimum the antenna is another important condition for good quality
value of 1.9 dB, - 20.1 dB, and 9.9 dB and achieved a LNA design. At low voltage, linearity of the proposed
maximum value of 5.9 dB, - 7.1 dB and 27.4 dB, LNA survives due to transconductance (gm) nonlinearity
respectively. Further, stability against supply voltage and drain-conductance (gds) nonlinearity present in MOS
variation is analysed by varying supply voltage by ± 20%. devices. The input power at which output signal power
The effect of Vdd supply variation on NF, S11 and S21 decreases by one dB is known as 1-dB compression (P1dB)
performance is shown in Fig. 9. It is observed that, NF is point. The 1-dB compression point of proposed LNA

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Fig. 11 a P1-dB point, b third order intercept (IIP3), and c stability factor

circuit is - 25 dBm as shown in Fig. 11a. The third order 1  jS11 j2 jS22 j2 þjS11 S22  S12 S21 j2
linearity becomes more important when the designed LNA K¼ [1 ð28Þ
2jS12 S21 j
is required to amplify two nearby frequency signals
because the mix of the these two nearby frequency com- jDj ¼ jS11 S22  S12 S21 j\1 ð29Þ
ponents may fall in the pass band and can disrupt the Figure 11c confirms the unconditional stability of the
desired output. The third order intercept point (IIP3) is proposed LNA with a minimum value of approximately
explored using two-tone (f1 and f2) test at 10 MHz apart equal to 2000 at 12.0 GHz which is extremely larger than 1
from the centre frequency (fo) of 6.0 GHz. Extrapolation of with the delta (|D|) value of less than 0.084. The results of
the output of fundamental frequency and third order output the proposed UWB LNA are compared with the previously
signal (ie. 2f2–f1), the IIP3 of the proposed LNA is published literatures in Table 2.
approximated to -18.0 dBm as shown in Fig. 11b.
The unconditional stability is another critical condition
for the designed LNA and this can be expressed in terms of
S-parameters as stability factor (K) and delta (D) as [3, 7]

Table 2 State-of-art and comparison with other existing LNA designs

Ref CMOS Node Vdd Freq (GHz) S11 (dB) S21 (dB) S12 (dB) S22 (dB) IIP3 NF (dB) Power
(nm) (V) (dBm) (mW)

This 90 1.0 3.1–12.0, \ - 10.1 17.3–21.0, - 113.0 \ - 11.3 - 18@ 2.4–3.9 9.3
Work 3.6–11.6 20.5 ± 0.5*,
[4] 90 1.2 3.1–10.6 \ - 14.1 10.48 ± 0.2*, – – ?4 3.075 ± 0.155 21.6
10.68#
[11] 90 1.2 2.6–10.2 \- 9 12.5# \ - 45 – – 3–7 7.2
[33] 90 2.7 0.5–8.0 \- 7 22-25.v – – - 16b 1.9–2.6 42
[37] 90 1.5 3.1–10.6 \ - 10 11–12.4 \ - 20 \ - 10 – 1.62–2.1 11.72
[28] 90 1.1 4.3–8.93dB \ - 18.2 13.87# \ - 8& \ - 14 9.8 1.15b 0.92
&

[34] 110 1.2 3–10 \ - 10.7 17.5–18.7 \ - 50 \ - 10 - 0.6 2.4–2.9 8.3

[12] 130 1.4 3.1 – 10.6 \- 8 10.24 \ - 31.7 \- 7 6.8 0.9–4.1 17.92
[38] 180 1.5 3.1 – 10.6 \ - 10 15.6 \ - 45 \ - 10.5 - 7.5@ 2.8–4.7 14.1
[35] 180 0.7 3.1 – 10.3 \- 9 9.6–12.7 \ -45 – - 3 to 2.5–3.9 13.4
1
[36] 180 1.8 3 – 12 \ - 10 19.24–20.24 – – - 5.5 1.72–1.99 23.23
*Average value
3dB
3-dB BW
&
Estimated from graph
#
Max value
b
Minimum
v
Voltage gain
@
at 6 GHz

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4 Conclusion 8. Arshad S, Ramzan R, Muhammad K, Wahab QU (2015) A sub-

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