APPLICATION NOTES

A V A I L A B L E
X25040 AN9 • AN18 • AN31 • AN37 • AN40

4K X25040 512 x 8 Bit

SPI Serial E2PROM with Block LockTM Protection
FEATURES DESCRIPTION
• 1MHz Clock Rate The X25040 is a CMOS 4096-bit serial E2PROM, inter-
• SPI Modes (0,0 & 1,1) nally organized as 512 x 8. The X25040 features a Serial
• 512 X 8 Bits Peripheral Interface (SPI) and software protocol allow-
—4 Byte Page Mode ing operation on a simple three-wire bus. The bus
• Low Power CMOS signals are a clock input (SCK) plus separate data in (SI)
—150µA Standby Current and data out (SO) lines. Access to the device is con-
—3mA Active Current trolled through a chip select (CS) input, allowing any
• 2.7V To 5.5V Power Supply number of devices to share the same bus.
• Block Lock Protection The X25040 also features two additional inputs that
—Protect 1/4, 1/2 or all of E2PROM Array provide the end user with added flexibility. By asserting
• Built-in Inadvertent Write Protection the HOLD input, the X25040 will ignore transitions on its
—Power-Up/Power-Down protection circuitry inputs, thus allowing the host to service higher priority
—Write Latch interrupts. The WP input can be used as a hardwire input
—Write Protect Pin to the X25040 disabling all write attempts, thus providing
• Self-Timed Write Cycle a mechanism for limiting end user capability of altering
—5ms Write Cycle Time (Typical) the memory.
• High Reliability
—Endurance: 100,000 cycles per byte The X25040 utilizes Xicor’s proprietary Direct Write™
—Data Retention: 100 Years cell, providing a minimum endurance of 100,000 cycles
—ESD protection: 2000V on all pins per byte and a minimum data retention of 100 years.
• 8-Lead PDlP Package
• 8-Lead SOIC Package

FUNCTIONAL DIAGRAM
WRITE
STATUS
PROTECT X DECODE 512 BYTE
REGISTER
LOGIC LOGIC ARRAY

32
32 X 32
SO
SI COMMAND
DECODE
SCK AND 32
32 X 32
CS CONTROL
LOGIC
HOLD

64
64 X 32

WRITE
CONTROL
AND
TIMING
WP
LOGIC
4 8

Y DECODE

DATA REGISTER
6451 FHD F01
Direct Write™ and Block Lock™ Protection is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending Characteristics subject to change without notice
6451-3.6 6/10/96 T5/C1/D0 NS 1
X25040

PIN DESCRIPTIONS Hold (HOLD)

Serial Output (SO) HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
SO is a push/pull serial data output pin. During a read
underway, HOLD may be used to pause the serial
cycle, data is shifted out on this pin. Data is clocked out
communication with the controller without resetting the
by the falling edge of the serial clock.
serial sequence. To pause, HOLD must be brought LOW
Serial Input (SI) while SCK is LOW. To resume communication, HOLD is
brought HIGH, again while SCK is LOW. If the pause
SI is the serial data input pin. All opcodes, byte ad-
feature is not used, HOLD should be held HIGH at all
dresses, and data to be written to the memory are input
times.
on this pin. Data is latched by the rising edge of the serial
clock.
PIN CONFIGURATION
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data DIP/SOIC
input and output. Opcodes, addresses, or data present
on the SI pin are latched on the rising edge of the clock CS 1 8 VCC
input, while data on the SO pin change after the falling SO 2 7 HOLD
X25040
edge of the clock input. WP 3 6 SCK
VSS 4 5 SI
Chip Select (CS)
When CS is HIGH, the X25040 is deselected and the SO 6451 FHD F02.1
output pin is at high impedance and unless an internal
write operation is underway, the X25040 will be in the
standby power mode. CS LOW enables the X25040,
placing it in the active power mode. It should be noted PIN NAMES
that after power-up, a HIGH to LOW transition on CS is Symbol Description
required prior to the start of any operation. CS Chip Select Input
Write Protect (WP) SO Serial Output
When WP is LOW, nonvolatile writes to the X25040 are SI Serial Input
disabled, but the part otherwise functions normally. SCK Serial Clock Input
When WP is held HIGH, all functions, including nonvola- WP Write Protect Input
tile writes operate normally. WP going LOW while CS is VSS Ground
still LOW will interrupt a write to the X25040. If the VCC Supply Voltage
internal write cycle has already been initiated, WP going
HOLD Hold Input
LOW will have no affect on a write.
6451 PGM T01

2
X25040

PRINCIPLES OF OPERATION Status Register

The X25040 is a 512 x 8 E2PROM designed to interface The RDSR instruction provides access to the status
directly with the synchronous serial peripheral interface register. The status register may be read at any time,
(SPI) of many popular microcontroller families. even during a write cycle. The status register is format-
ted as follows:
The X25040 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on 7 6 5 4 3 2 1 0
the rising SCK. CS must be LOW and the HOLD and WP X X X X BP1 BP0 WEL WIP
inputs must be HIGH during the entire operation. 6451 PGM T02

BP0 and BP1 are set by the WRSR instruction. WEL

Table 1 contains a list of the instructions and their
and WIP are read-only and automatically set by other
opcodes. All instructions, addresses and data are trans-
operations.
ferred MSB first.
The Write-In-Process (WIP) bit indicates whether the
Data input is sampled on the first rising edge of SCK after
X25040 is busy with a write operation. When set to a “1”,
CS goes LOW. SCK is static, allowing the user to stop
a write is in progress, when set to a “0”, no write is in
the clock and then resume operations. If the clock line is
progress. During a write, all other bits are set to “1”.
shared with other peripheral devices on the SPI bus, the
user can assert the HOLD input to place the X25040 into The Write Enable Latch (WEL) bit indicates the status of
a “PAUSE” condition. After releasing HOLD, the X25040 the “write enable” latch. When set to a “1”, the latch is set,
will resume operation from the point when HOLD was when set to a “0”, the latch is reset.
first asserted.
The Block Protect (BP0 and BP1) bits are nonvolatile
Write Enable Latch and allow the user to select one of four levels of protec-
The X25040 contains a “write enable” latch. This latch tion. The X25040 is divided into four 1024-bit segments.
must be SET before a write operation will be completed One, two, or all four of the segments may be protected.
internally. The WREN instruction will set the latch and That is, the user may read the segments but will be
the WRDI instruction will reset the latch. This latch is unable to alter (write) data within the selected segments.
automatically reset upon a power-up condition and after The partitioning is controlled as illustrated below.
the completion of a byte, page, or status register write
Status Register Bits Array Addresses
cycle.
BP1 BP0 Protected
0 0 None
0 1 $180–$1FF
1 0 $100–$1FF
1 1 $000–$1FF
6451 PGM T03

Table 1. Instruction Set

Instruction Name Instruction Format* Operation
WREN 0000 0110 Set the Write Enable Latch (Enable Write Operations)
WRDI 0000 0100 Reset the Write Enable Latch (Disable Write Operations)
RDSR 0000 0101 Read Status Register
WRSR 0000 0001 Write Status Register
READ 0000 A8011 Read Data from Memory Array beginning at selected address
Write Data to Memory Array beginning at Selected Address
WRITE 0000 A8010
(1 to 32 Bytes)
6451 PGM T04.2
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.

3
X25040

Clock and Data Timing To write data to the E2PROM memory array, the user
issues the WRITE instruction, followed by the address
Data input on the SI line is latched on the rising edge of and then the data to be written. This is minimally a
SCK. Data is output on the SO line by the falling edge of twenty-four clock operation. CS must go LOW and
SCK. remain LOW for the duration of the operation. The host
Read Sequence may continue to write up to 4 bytes of data to the X25040.
The only restriction is the 4 bytes must reside on the
When reading from the E2PROM memory array, CS is same page. If the address counter reaches the end of
first pulled LOW to select the device. The 8-bit READ the page and the clock continues, the counter will “roll
instruction is transmitted to the X25040, followed by the over” to the first address of the page and overwrite any
8-bit address. Bit 3 of the Read Data instruction con- data that may have been written.
tains address A8. This bit is used to select the upper or
lower half of the address. After the READ opcode and For the write operation (byte or page write) to be
address are sent, the data stored in the memory at the completed, CS can only be brought HIGH after bit 0 of
selected address is shifted out on the SO line. The data data byte N is clocked in. If it is brought HIGH at any other
stored in memory at the next address can be read time the write operation will not be completed. Refer to
sequentially by continuing to provide clock pulses. The Figures 4 and 5 below for a detailed illustration of the
address is automatically incremented to the next higher write sequences and time frames in which CS going
address after each byte of data is shifted out. When the HIGH are valid.
highest address is reached ($1FF) the address counter
rolls over to address $000 allowing the read cycle to be To write to the status register, the WRSR instruction is
continued indefinitely. The read operation is termi- followed by the data to be written. Data bits 0, 1, 4, 5, 6
nated by taking CS HIGH. Refer to the read E2PROM and 7 must be “0”. Figure 6 illustrates this sequence.
array operation sequence illustrated in Figure 1. While the write is in progress following a status register
To read the status register, the CS line is first pulled or E2PROM write sequence, the status register may be
LOW to select the device followed by the 8-bit RDSR read to check the WIP bit. During this time the WIP bit will
instruction. After the read status register opcode is be HIGH.
sent, the contents of the status register are shifted out Hold Operation
on the SO line. Figure 2 illustrates the read status
register sequence. The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
Write Sequence can be pulled LOW to suspend the transfer until it can be
Prior to any attempt to write data into the X25040, the resumed. The only restriction is the SCK input must be
“write enable” latch must first be set by issuing the LOW when HOLD is first pulled LOW and SCK must also
WREN instruction (See Figure 3). CS is first taken LOW, be LOW when HOLD is released.
then the WREN instruction is clocked into the X25040. The HOLD input may be tied HIGH either directly to VCC
After all eight bits of the instruction are transmitted, CS or tied to VCC through a resistor.
must then be taken HIGH. If the user continues the write
operation without taking CS HIGH after issuing the
WREN instruction, the write operation will be ignored.

4
X25040

Operational Notes Data Protection

The X25040 powers-up in the following state: The following circuitry has been included to prevent
• The device is in the low power standby state. inadvertent writes:
• A HIGH to LOW transition on CS is required to • The “write enable” latch is reset upon power-up.
enter an active state and receive an instruction. • A WREN instruction must be issued to set the “write
• SO pin is high impedance. enable” latch.
• The “write enable” latch is reset. • CS must come HIGH at the proper clock count in
order to start a write cycle.

Figure 1. Read E2PROM Array Operation Sequence

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
SCK

INSTRUCTION BYTE ADDRESS

SI 8 7 6 5 4 3 2 1 0

9TH BIT OF ADDRESS

DATA OUT
HIGH IMPEDANCE
SO 7 6 5 4 3 2 1 0
MSB

6451 FHD F14

Figure 2. Read Status Register Operation Sequence

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SCK

INSTRUCTION
SI

DATA OUT
HIGH IMPEDANCE
SO 7 6 5 4 3 2 1 0
MSB
6451 ILL F13

5
X25040

Figure 3. Write Enable Latch Sequence

CS

0 1 2 3 4 5 6 7

SCK

SI

HIGH IMPEDANCE
SO
6451 ILL F05

Figure 4. Byte Write Operation Sequence

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK

INSTRUCTION BYTE ADDRESS DATA BYTE

SI 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

9TH BIT OF ADDRESS

HIGH IMPEDANCE
SO

6451 FHD F06.1

6
X25040

Figure 5. Page Write Operation Sequence

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK

INSTRUCTION BYTE ADDRESS DATA BYTE 1

SI 8 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

9TH BIT OF ADDRESS

CS

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK

DATA BYTE 2 DATA BYTE 3 DATA BYTE 4

SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

6451 FHD F07

Figure 6. Write Status Register Operation Sequence

CS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SCK

INSTRUCTION DATA BYTE

SI 7 6 5 4 3 2 1 0

HIGH IMPEDANCE
SO
6451 ILL F08

7
X25040

ABSOLUTE MAXIMUM RATINGS* *COMMENT

Temperature under Bias .................. –65°C to +135°C Stresses above those listed under “Absolute Maximum
Storage Temperature ....................... –65°C to +150°C Ratings” may cause permanent damage to the device.
Voltage on any Pin with Respect to VSS ......... –1V to +7V This is a stress rating only and the functional operation of
D.C. Output Current ............................................. 5mA the device at these or any other conditions above those
Lead Temperature listed in the operational sections of this specification is
(Soldering, 10 seconds) .............................. 300°C not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

Temp Min. Max. Supply Voltage Limits
Commercial 0°C +70°C X25040 5V ±10%
Industrial –40°C +85°C X25040-3 3V to 5.5V
Military –55°C +125°C X25040-2.7 2.7 to 5.5V
6451 PGM T05.1 6451 PGM T06.1

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol Parameter Min. Max. Units Test Conditions
ICC VCC Supply Current (Active) 3 mA SCK = VCC x 0.1/VCC x 0.9 @ 1MHz,
SO = Open
ISB VCC Supply Current (Standby) 150 µA CS = VCC, VIN = VSS or VCC – 0.3V
ILI Input Leakage Current 10 µA VIN = VSS to VCC
ILO Output Leakage Current 10 µA VOUT = VSS to VCC
VIL(1) Input LOW Voltage –1 VCC x 0.3 V
VIH(1) Input HIGH Voltage VCC x 0.7 VCC + 0.5 V
VOL Output LOW Voltage 0.4 V IOL = 2mA
VOH Output HIGH Voltage VCC–0.8 V IOH = –1mA
6451 PGM T07.3

POWER-UP TIMING
Symbol Parameter Min. Max. Units
tPUR(2) Power-up to Read Operation 1 ms
tPUW(2) Power-up to Write Operation 5 ms
6451 PGM T08

CAPACITANCE TA = +25°C, f = 1MHz, VCC = 5V.

Symbol Test Max. Units Conditions
COUT(2) Output Capacitance (SO) 8 pF VOUT = 0V
CIN(2) Input Capacitance (SCK, SI, CS, WP, HOLD) 6 pF VIN = 0V
6451 PGM T09.1

Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.

8
X25040

EQUIVALENT A.C. LOAD CIRCUIT AT 5V VCC A.C. TEST CONDITIONS

Input Pulse Levels VCC x 0.1 to VCC x 0.9
5V
Input Rise and Fall Times 10ns
2.16KΩ
Input and Output Timing Level VCC x 0.5
6451 PGM T10

OUTPUT

3.07KΩ 100pF

6451 FHD F12.1

A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)

Data Input Timing
Symbol Parameter Min. Max. Units
fSCK Clock Frequency 0 1 MHz
tCYC Cycle Time 1000 ns
tLEAD CS Lead Time 500 ns
tLAG CS Lag Time 500 ns
tWH Clock HIGH Time 400 ns
tWL Clock LOW Time 400 ns
tSU Data Setup Time 100 ns
tH Data Hold Time 100 ns
tRI Data In Rise Time 2 µs
tFI Data In Fall Time 2 µs
tHD HOLD Setup Time 200 ns
tCD HOLD Hold Time 200 ns
tCS CS Deselect Time 500 ns
tWC(4) Write Cycle Time 10 ms
6451 PGM T11.1

Data Output Timing

Symbol Parameter Min. Max. Units
fSCK Clock Frequency 0 1 MHz
tDIS Output Disable Time 500 ns
tV Output Valid from Clock LOW 400 ns
tHO Output Hold Time 0 ns
tRO(3) Output Rise Time 300 ns
tFO(3) Output Fall Time 300 ns
tLZ HOLD HIGH to Output in Low Z 100 ns
tHZ HOLD LOW to Output in High Z 100 ns
6451 PGM T12.1
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
nonvolatile write cycle.

9
X25040

Serial Output Timing

CS

tCYC tWH tLAG

SCK

tV tHO tWL tDIS

SO MSB OUT MSB–1 OUT LSB OUT

ADDR
SI LSB IN

6451 FHD F09.1

Serial Input Timing

tCS

CS

tLEAD tLAG

SCK

tSU tH tRI tFI

SI MSB IN LSB IN

HIGH IMPEDANCE
SO
6451 FHD F10

10
X25040

Hold Timing

CS

tHD tCD tCD

tHD
SCK

tHZ tLZ

SO

SI

HOLD
6451 FHD F11

11
X25040

PACKAGING INFORMATION

8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

0.430 (10.92)
0.360 (9.14)

0.260 (6.60)
0.240 (6.10)

PIN 1 INDEX

PIN 1

0.300 0.060 (1.52)

(7.62) REF. 0.020 (0.51)

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL 0.145 (3.68)
SEATING 0.128 (3.25)
PLANE

0.150 (3.81) 0.025 (0.64)

0.125 (3.18) 0.015 (0.38)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79) 0.020 (0.51)
0.090 (2.29) 0.016 (0.41)

0.325 (8.25)
0.015 (0.38)
0.300 (7.62)
MAX.

0°
TYP. 0.010 (0.25) 15°

NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

3926 FHD F01

12
X25040

PACKAGING INFORMATION

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

0.150 (3.80) 0.228 (5.80)

0.158 (4.00) 0.244 (6.20)

PIN 1 INDEX

PIN 1

0.014 (0.35)
0.019 (0.49)

0.188 (4.78)
0.197 (5.00)

(4X) 7°

0.053 (1.35)
0.069 (1.75)

0.004 (0.19)
0.050 (1.27)
0.010 (0.25)

0.010 (0.25) 0.050" TYPICAL

X 45°
0.020 (0.50)

0.050"
0° – 8° TYPICAL
0.0075 (0.19)
0.010 (0.25) 0.250"

0.016 (0.410)
0.037 (0.937)

0.030"
TYPICAL
FOOTPRINT 8 PLACES

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FHD F22.1

13
X25040

ORDERING INFORMATION

X25040 P T -V

Device VCC Limits

Blank = 5V ±10%
3 = 3V to 5.5V
2.7V = 2.7V to 5.5V

Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C

Package
P = 8-Lead Plastic DIP
S = 8-Lead SOIC

Part Mark Convention

X25040 X Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP
X

Blank = 5V ±10%, 0°C to +70°C

I = 5V ±10%, –40°C to +85°C
D = 3V to 5.5V, 0°C to +70°C
E = 3V to 5.5V, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C

LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.

14