SI UD1 Part2.en
SI UD1 Part2.en
SI UD1 Part2.en
In a very general way, there are three types of buses, according to the function they perform.
Address Bus: It is a unidirectional bus because the information flows in a single direction, from the
CPU to the memory or to the input and output elements. The CPU alone can place logic levels in
the n address lines, with which 2n possible different addresses are generated. Each of these
addresses corresponds to a memory location or I / O device.
Data Bus: it is a bidirectional bus, as data can flow to or from the CPU. They can be inputs or
outputs, depending on the operation being carried out (reading or writing).
Control Bus: Set of signals is used to synchronize activities and transactions with system
peripherals. Some of these signals, like R / W, are signals that the CPU sends to indicate what type
of operation is expected at that moment. Peripherals can also send control signals to the CPU,
such as INT, RESET, BUS RQ.
We have seen in the introduction the types of buses by technology, in the types that we
are going to see now, both data and addresses will circulate that will be processed by
the devices and the processor:
Memory bus
As its name suggests, this bus is in charge of communicating the memory controller,
currently inserted in the processor, with the system's RAM. This bus has taken
different names depending on the manufacturer of the processor, since
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Everything that goes in and out of the processor goes through the FSB. You can
see it in the diagram that is below a typical Core 2 Duo processor and the FSB
communication channels.
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The PCIe bus was designed to be the substitute for AGP and PCI buses ( we just talked
about) with an interface that was modular in design. This means that there is no single slot size
for expansion cards, but they can be longer or shorter, depending on the amount of traffic to be
sent through them. Thus, we have PCIe x1, x4, x8 and x16 slots. Generally, it is the processor
in charge of managing the system's PCIe bus. Although in certain motherboards high-end,
there are usually PLX that allow you to give more data paths to the PCIe bus.
Currently, most components connect to the system's PCIe bus, be it the graphics card, sound
card, network card (wired or wireless), or USB. Therefore, it is, together with the memory bus,
the most important of all computer buses.
The PCI Express standard is the responsibility of the “ PCI Special Interest Group
”( PCI-SIG) and the goal of its development was for it to completely replace as single
standard to older buses such as ISA, AGP or the same PCI on which it is based. PCIe
offers a fundamental advantage over PCI by being structured as point-to-point, full-
duplex lanes, working in series. Basically, each individual PCIe port and its installed
cards can get the most out of the bus, versus slower and crowded PCI when the
computer mounts multiple connectors.
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Recently, the PCI-SIG consortium announced the final specifications of the next generation PCI
Express Gen 4.0. A version that will offer higher performance than the current PCIe 3.0, increasing
the number of channels through which the signal passes to double the bandwidth up to 16
Gigatransfers per second. Will also offer lower latency, higher RAS capabilities, improved I / O
virtualization, to tackle the increasing needs of the industry, especially in the graphics market with
truly photorealistic video games, but also in professional applications with high workloads and
bandwidth such as technologies related to artificial intelligence. Another improvement will come from
the smaller physical size of the bus, which will allow smaller cards and not in the monstrous sizes
that we can find -for example- in current high-end dedicated graphics.
Different physical sizes allow different amounts of connections and data to be moved
simultaneously to the motherboard. The larger the port, the greater its maximum capacity. These
connections are known colloquially as "lines" or "lanes", where each PCI-E lane is made up of two
signaling pairs, one for sending data and the other for receiving. In practice, the greater number of
lanes allows to gain in performance and capacity and the data will be able to flow faster between
the peripheral and the rest of the computer system.
In version 3.0 of PCI Express (the most used currently), the theoretical maximum throughput per
line is 8 GT / s, which in practice translates to slightly less than 1 Gbyte per second per lane. Not
all devices need the same capacity and although there are no established guidelines on what type
of slot to use, we can point out some practical examples of its use.
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For a common sound card or a Wi-Fi, a PCI-E x1 is enough, while a high-end
network card, RAID controllers or USB 3 expanders, use x4 or x8. Graphics cards
typically use x16 for maximum transfer capacity. SSDs in M.2 format for PCIe are
usually connected to x4 ports, but everything indicates that it will be small in future
generations.
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USB bus
This data bus is responsible for transmitting or receiving data from the devices
connected to it. Generally, this
bus is used to connect peripherals to the computer, such as keyboard, mouse,
external storage drives, etc. The most modern specification of USB (USB 3.1 2nd
Generation) allows data transmission up to 10 GB / s.
Old buses