Module 6

Flynn’s Classification
 Parallel processing
Definition
It is using multiple processors simultaneously to solve a problem.

Purpose
Improve performance (shorter run time - reduced time needed
to solve a problem)

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Flynn’s Classification

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 Flynn’s Taxonomy (Classification)

• Mike Flynn, “Very High-Speed ComputingSystems,”

Proceedings of IEEE, 1966

• SISD

• SIMD

• MISD

• MI MD

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Flynn’s Classification

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 Flynn’s Taxonomy (continued)
Mike Flynn, “Very High-Speed Computing Systems,”
Proceedings of IEEE, 1966

• SISD • Single instruction operates on

single data element
• SIMD
 Corresponds to the Von Neumann
architecture
• MISD
 Includes ILP techniques such as
superscalar and speculative execution
• M IM D
 Uniprocessor

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 Flynn’s Taxonomy (continued)
Mike Flynn, “Very High-Speed Computing Systems,”
Proceedings of IEEE, 1966

• SISD

• SIMD

• MISD

• M IM D

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Flynn’s Classification

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 Flynn’s Taxonomy (continued)
Mike Flynn, “Very High-Speed Computing Systems,”
Proceedings of IEEE, 1966

• SISD • Single instruction operates on

multiple data elements
• SIMD
 Vector processors

• MISD  GPU (SIMT)

• M IM D

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 Flynn’s Taxonomy (continued)
Mike Flynn, “Very High-Speed Computing Systems,”
Proceedings of IEEE, 1966

• SISD

• SIMD

• MISD

• M IM D

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Flynn’s Classification

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Flynn’s Classification

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 Flynn’s Taxonomy (continued)
Mike Flynn, “Very High-Speed Computing Systems,”
Proceedings of IEEE, 1966

• SISD • Multiple instructions operate on

single data element
• SIMD
 Systolic arrays

• MISD

• M IM D

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 Flynn’s Taxonomy (continued)
Mike Flynn, “Very High-Speed Computing Systems,”
Proceedings of IEEE, 1966

• SISD

• SIMD

• MISD

• M IM D

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Flynn’s Classification

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 Flynn’s Taxonomy (continued)
Mike Flynn, “Very High-Speed Computing Systems,”
Proceedings of IEEE, 1966

• SISD • Multiple instructions operate on

multiple data element
• SIMD
 Multiprocessor

• MISD  Multithreaded processor

• M IM D

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 Flynn’s Taxonomy (continued)
Mike Flynn, “Very High-Speed Computing Systems,”
Proceedings of IEEE, 1966

• SISD

• SIMD

• MISD

• M IM D

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Flynn’s Classification

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 Multicore Architecture
• A multicore computer, also known as a chip
multiprocessor, combines two or more processors
(called cores) on a single piece of silicon (called a
die).
• Typically, each core consists of all of the
components of an independent processor, such as
registers, ALU, pipeline hardware, and control
unit, plus L1 instruction and data caches.
• In addition to the multiple cores, contemporary
multicore chips also include L2 cache and,
increasingly, L3 cache.
Single-core computer

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0
Single-core CPU chip
the single core

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 Multi-core architectures
• This lecture is about a new trend in
computer architecture:
Replicate multiple processor cores on a
single die.
Core 1 Core 2 Core 3 Core 4

Multi-core CPU chip 2

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 Multi-core CPU chip
• The cores fit on a single processor socket
• Also called CMP (Chip Multi-Processor)

c c c c
o o o o
r r r r
e e e e

1 2 3 4

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 The cores run in parallel
thread 1 thread 2 thread 3 thread 4

c c c c
o o o o
r r r r
e e e e

1 2 3 4

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Within each core, threads are time-sliced (just
like on a uniprocessor)
several several several several
threads threads threads threads

c c c c
o o o o
r r r r
e e e e

1 2 3 4

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 Interaction with the
Operating System
• OS perceives each core as a separate processor

• OS scheduler maps threads/processes

to different cores

• Most major OS support multi-core today:

Windows, Linux, Mac OS X, …

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 Instruction-level parallelism
• Parallelism at the machine-instruction
level
• The processor can re-order, pipeline
instructions, split them into
microinstructions, do aggressive branch
prediction, etc.
• Instruction-level parallelism enabled rapid
increases in processor speeds over the
last 15 years
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 Thread-level parallelism (TLP)
• This is parallelism on a more coarser scale
• Server can serve each client in a separate
thread (Web server, database server)
• A computer game can do AI, graphics, and
physics in three separate threads
• Single-core superscalar processors cannot
fully exploit TLP
• Multi-core architectures are the next step in
processor evolution: explicitly exploiting TLP
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* Pipelining: Individual instructions are executed through a pipeline of
stages so that while one instruction is executing in one stage of the pipeline,
another instruction is executing in another stage of the pipeline.

* Superscalar: Multiple pipelines are constructed by replicating execution

resources. This enables parallel execution of instructions in parallel pipelines,
so long as hazards are avoided.

* Simultaneous multithreading (SMT): Register banks are replicated so

that multiple threads can share the use of pipeline resources.
• Multi-threaded native applications
– Characterized by having a small number of highly threaded
processes
– Lotus Domino, Siebel CRM (Customer Relationship Manager)
• Multi-process applications
– Characterized by the presence of many single-threaded processes
– Oracle, SAP, PeopleSoft
• Java applications
– Java Virtual Machine is a multi-threaded process that provides scheduling
and memory management for Java applications
– Sun’s Java Application Server, BEA’s Weblogic, IBM Websphere, Tomcat
• Multi-instance applications
– One application running multiple times
– If multiple application instances require some degree of isolation,
virtualization technology can be used to provide each of them with its own
separate and secure environment