EEE 4233: VLSI I

Lecture #5
CMOS Fabrication and Layout Design Rules
Chapter 1 [1.5]: Weste and Harris,
Chap 3 [3.3-3,4]: Uyemura

Dr. Sharnali Islam

Department of Electrical and Electronic Engineering

University of Dhaka
[email protected]
 CMOS Fabrication
 CMOS transistors are fabricated on silicon wafer
 Lithography process similar to printing press
 On each step, different materials are deposited or
etched
 Easiest to understand by viewing both top and cross-
section of wafer in a simplified manufacturing process

2
 Inverter Cross-section

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

3
 Well and Substrate Taps
 What are substrate contacts/taps?

A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

4
 Inverter Mask Set
 Transistors and wires are defined by masks
 Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

5
 Detailed Mask Views
 Six masks n well

» n-well
» Polysilicon Polysilicon

» n+ diffusion
» p+ diffusion n+ Diffusion

» Contact p+ Diffusion

» Metal Contact

Metal

6
 Fabrication
 Chips are built in huge factories called fabs
 Contain clean rooms as large as football fields

Courtesy of International
Business Machines Corporation.
Unauthorized use not permitted.

7
 Fabrication Steps
 Start with blank wafer
 Build inverter from the bottom up
 First step will be to form the n-well
» Cover wafer with protective layer of SiO2 (oxide)
» Remove layer where n-well should be built
» Implant or diffuse n dopants into exposed wafer
» Strip off SiO2

p substrate

8
 Oxidation
 Grow SiO2 on top of Si wafer
» 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

9
 Photoresist
 Spin on photoresist
» Photoresist is a light-sensitive organic polymer
» Softens where exposed to light

Photoresist
SiO2

p substrate

10
 Lithography
 Expose photoresist through n-well mask
 Strip off exposed photoresist

Photoresist
SiO2

p substrate

11
 Etch
 Etch oxide with hydrofluoric acid (HF)
» Seeps through skin and eats bone; nasty stuff!!!
 Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

12
 Strip Photoresist
 Strip off remaining photoresist
» Use mixture of acids called piranah etch
 Necessary so resist doesn’t melt in next step

SiO2

p substrate

13
 Types of Eching/Lithography
 Positive Etching/Lithography
 Negative Etching/Lithography
Positive of Etching/Lithography
Negative of Etching/Lithography
 n-well
 n-well is formed with diffusion or ion implantation
 Diffusion
» Place wafer in furnace with arsenic gas
» Heat until As atoms diffuse into exposed Si
 Ion Implanatation
» Blast wafer with beam of As ions
» Ions blocked by SiO2, only enter exposed Si

SiO2

n well

17
Why the well is wider than the hole in the oxide?
 Strip Oxide
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well
 Subsequent steps involve similar series of steps

n well
p substrate

18
 Polysilicon
 Deposit very thin layer of gate oxide
» < 20 Å (6-7 atomic layers)
 Chemical Vapor Deposition (CVD) of silicon layer
» Place wafer in furnace with Silane gas (SiH4)
» Forms many small crystals called polysilicon
» Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

19
 Polysilicon Patterning
 Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

20
 Self-Aligned Process
 Use oxide and masking to expose where n+ dopants should be diffused or
implanted
 N-diffusion forms nMOS source, drain, and n-well contact

n well
p substrate

21
 N-diffusion
 Pattern oxide and form n+ regions
 Self-aligned process where gate blocks diffusion
 Polysilicon is better than metal for self-aligned gates because it doesn’t melt
during later processing

n+ Diffusion

n well
p substrate

22
 N-diffusion cont.
 Historically dopants were diffused
 Usually ion implantation today
 But regions are still called diffusion

n+ n+ n+

n well
p substrate

23
 N-diffusion cont.
 Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

24
 P-Diffusion
 Similar set of steps form p+ diffusion regions for pMOS source and drain
and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

25
 Contacts
 Now we need to wire together the devices
 Cover chip with thick field oxide
 Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

26
 Metalization
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

27
 Layout
 Chips are specified with set of masks

 Minimum dimensions of masks determine transistor size (and

hence speed, cost, and power)

 Feature size f = distance between source and drain

» Set by minimum width of polysilicon

 Feature size improves 30% every 3 years or so

 Normalize for feature size when describing design rules

 Express rules in terms of  = f/2

» E.g. l = 0.09 mm in 0.18 mm process 28
 Design Rules
• Allow translation of circuits (usually in stick diagram or
symbolic form) into actual geometry in silicon

• Interface between circuit designer and fabrication engineer

• Compromise
– designer - tighter, smaller
– fabricator - controllable, reproducible

• Conservative vs aggressive design rules

 Design Rules
• Design rules define ranges for features. Examples:
✓ min. wire widths to avoid breaks
✓ min. spacing to avoid shorts
✓ minimum overlaps to ensure complete overlaps
• Required for resolution/tolerances of masks
• Two major approaches:
– “Micron” rules: stated at micron resolution.
– λ rules: simplified micron rules with limited scaling attributes.
Proposed by Mead and Conway in 1980.
• Design rules represents a tolerance which insures very high
probability of correct fabrication
– scalable design rules: lambda parameter
– absolute dimensions (micron rules)
 Problems in Manufacturing

Manufacturing processes have their inherent limitations

in accuracy
➢ Photo resist shrinkage, tearing.
➢ Variations in material deposition, temperature and oxide
thickness.
➢ Impurities.
➢ Variations between lots and across a wafer.
 Problems in Manufacturing
• Transistor problems:
Variations in threshold voltage: This may occur due to
variations in oxide thickness, ion implantation and poly
layer. Changes in source/drain diffusion overlap. Variations in
substrate.

• Wiring problems:
Diffusion: There is variation in doping which results in
variations in resistance, capacitance.
Poly, metal: Variations in height, width resulting in variations
in resistance, capacitance. Shorts and opens.
 Problems in Manufacturing

• Oxide problems:
Variations in height.
Lack of planarity.

• Via problems:
Via may not be cut all the way through.
Undersize via has too much resistance.
Via may be too large and create short.
 Geometric Design Rules
• Resolution
– Width and spacing of lines on one layer
• Alignment
– make sure interacting layers overlap (or don’t)
– Contact surround
– Poly overlap of diffusion
– Well surround of diffusion
 Design Rules
❑Metal and diffusion have minimum width and spacing of 4λ.
❑Polysilicon uses a width of 2λ.
❑Polysilicon overlaps diffusion by 2λ where a transistor is desired
and has a spacing of 1λ away where no transistor is desired.
❑Polysilicon and contacts have a spacing of 3λ from other
polysilicon or contacts.

Why?
 Design Rules
❑Contacts are 2λ × 2 λ and must be surrounded by 1λ on the layers
above and below.
❑N-well surrounds pMOS transistors by 6λ and avoids nMOS
transistors by 6λ.
 Example: Inverter
• Transistor dimensions specified as Width/Length
– Minimum size is 4λ/2λ, sometimes called 1 unit
– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long
Wiring Tracks

W-H:1.5.5
Well Spacing
 Stick Diagrams
 One approach to layout is based on the concept of simple stick diagram
» It often used to perform quick layouts or
» To study large complex routing problems
 Stick diagrams help plan layout quickly
» Need not be to scale
» Draw with color pencils or dry-erase markers
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact

GND GND
INV NAND3
 Stick Diagrams (Cont.)
A stick diagram is a cartoon of a layout.
 Does show all components/vias.
 It shows relative placement of components.
 Goes one step closer to the layout
V DD
A B C
 Helps plan the layout and routing metal1
poly
ndiff
pdiff
 Does not show Y contact

» Exact placement of components

GND
» Transistor sizes NAND3

» Wire lengths, wire widths, tub boundaries.

» Any other low level details such as parasitic.
 Stick Diagrams (Cont.)
 Rule 1: When two or more ‘sticks’ of the same type cross or touch each
other that represents electrical contact.

 Rule 2: When two or more ‘sticks’ of different type cross or touch each other
there is no electrical contact.
(If electrical contact is needed we have to show the connection explicitly).
 Stick Diagrams (Cont.)
 Rule 3: When a poly crosses diffusion it represents a transistor.

N+ N+

Note: If a contact is shown then it is not a transistor.

 Rule 4: Avoid touching of p-diff with n-diff.

» All pMOS must lie on one side and all nMOS will have to be on the other
side.
 Practice Problem: Stick Diagram
NOR pmos series
nmos parallel Y = A+B

NAND pmos parallel

nmos series
VDD

pDiff
Y

nDiff
B A
GND
 Stick Diagrams (Cont.)
 It is relatively easy to transfer a stick diagram to layout
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact

GND GND
INV NAND3
 Stick Diagrams (Cont.)
 Draw the layout from the stick diagram
 Height of cell determined by metal width and spacing
 Practice problems
 Practice problems:
» W-H: 1.16- 1.19
» Uyemura: For problems 3.14, 3.15, and 3.16, draw stick
diagrams instead of layouts
 Area Estimation
Example: NAND3
Area Estimation

Area = 32λ × 40λ

Example: O3AI

Area = 40λ × 48λ A3OI = ?

Practice Problem
Practice Problem
3-D View of a Design