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VLSI 1 - Lec1 - Introduction

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9 views17 pages

VLSI 1 - Lec1 - Introduction

Uploaded by

am0163117
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EEE 4233: VLSI I

Lecture #1: Introduction

Dr. Sharnali Islam


Department of Electrical and Electronic Engineering
University of Dhaka
[email protected]

Some slides used resources from:


Dr. Hasan U Zaman, North South University
Md. Ismail Hossain neural semiconductor
Web resources
Course Outline

Class Schedule: Monday: 8:30 AM - 10:00 AM


Tuesday: 11:30 AM - 1:00 PM

Total Credits: 3 credits

Text Book:
1. John P. Uyemura, "Introduction to VLSI Circuits and Systems", John
Wiley & Sons, Inc.
2. Neil H. E. Weste and David Harris, “CMOS VLSI Design, A Circuits and
Systems Perspective”, 4th Edition, Pearson Addison Wesley.

pdf copies of the books will be available in the Google-classroom drive. 2


Course Outline

Google Classroom:
Class Attendance: 5%
Course Name: EEE 4233 VLSI I
2021
In-course Exam: 25% Code: 35cu7e2
https://classroom.google.com/c/NTM2OTk3
Final Exam: 70% NDY5NTkw

Class materials will be uploaded in Google Classroom


Course Content
DU EEE Syllabus:
VLSI technology: Top down design approach, technology trends and design
styles.

Review of MOS transistor theory: Threshold voltage, body effect, I-V equations
and characteristics, latch-up problems, NMOS inverter, CMOS inverter, pass-
transistor and transmission gates.

CMOS circuit characteristics and performance estimation: Resistance,


capacitance, rise and fall times, delay, gate transistor sizing and power
consumption.

CMOS circuit and logic design: Layout design rules and physical design of simple
logic gates.

CMOS subsystem design: Adders, multiplier and memory system, arithmetic


logic unit.
Programmable logic arrays. I/O systems. VLSI testing.
History of Electronic Devices

Lectures by Prof. Lundstrom at Purdue University from nanohub.org


• Moore's law is the observation that the number of transistors in a
dense integrated circuit doubles about every two years.
• The observation is named after Gordon Moore, the co-founder
of Fairchild Semiconductor and was the CEO of Intel
A Typical Chip
A Typical Chip Inside
Dimension = 37.5 mm x
37.5 mm x 4.4 mm

1.736 Billion Transistors


THERE ARE 18 CORES IN THIS CHIP. INTEL'S 2017 SERVER
PROCESSORS WILL HAVE UP TO 28. IMAGE SOURCE: INTEL.
VLSI Design Ecosystem

Fabless
Design
Companies

TSMC CAD Synopsys


GlobalFoundries
Samsung
Foundry
Companies VLSI Tool
Vendors
Cadence
Mentor Graphics

Fabrication
Companies
Bangladesh Industry Insights
VLSI Companies at
Total 8
Dhaka
VLSI Design Engineers
450+
at Dhaka
GlobalFoundries, TSMC, Apple, Mythic,
Client Base
Samsung, Qualcomm etc.
Cadence in
Total 12
Universities
Complete Setup LAB 1 – BUET
Full Time Salary Structure

15–20K
Trainee Period

35–45K 45–60K 55–80K 70–100K 90–150K 120–200K


Till 2 years, it’s
a learning time

3
0 1 year 2 years 3 years 4 years 5 years
months

Job Engineers become capable of being


Permanent SENIOR ENGINEER after 2.5 years
Confirmation after 3
months training
period

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