TRIBHUVAN UNIVERSITY

INSTITUTE OF ENGINEERING
THAPATHALI CAMPUS

Digital Logic-EX 152

Unit 8 : Digital Integrated Circuits
Presented By
Er. Ganesh Kumal
Department of Electronics & Computer Engineering
IOE ,Thapathali Campus

22 June, 2024
Prepared By: Er. Ganesh Kumal 1
8. Digital Integrated Circuits
8.1. BJT and MOSFET Switching Circuits
8.2. 7400 TTL Parameters
8.4. TTL Logic Circuits: NAND, NOR, NOT
8.5. CMOS Parameters
8.6. CMOS Logic Circuits: NAND, NOR, NOT
8.7. Digital Devices Application
8.7.1 Multiplexing Displays
8.7.2 Frequency Counter
8.7.3 Time Measurements
Integrated Circuit
• An integrated circuit is electronic circuit or device that has electronic components on a small
semiconductor chip. It has functionality of logic gates or amplifying of a signal.

Types of Integrated Circuits

• There are different types of integrated circuits based on various criteria. Based on intended
application, the Integrated Circuit (IC) can be classified as following:
• Digital Integrated Circuits
 handle discrete signals such as binary values (0 and 1). These circuits use digital logic gates, multiplexers, flip
flops etc. These circuits are easier to design and economical.
 Logic gates are the building blocks of Digital ICs which operate either at 0 or 1.
• Analog Integrated Circuits
 handle continuous signals. These are two types: linear integrated circuits (Linear ICs) and Radio frequency
integrated circuits (RF ICs).
 Examples: Op-amp (operational amplifier) is one of the types of linear ICs which are used in amplifiers, timers
and counters, oscillators etc.
• Mixed Integrated Circuits
 are obtained by the combination of analog and digital integrated circuits.
 Analog to digital (A/D) converter, digital to analog (D/A) converter circuit.
Integration level
• During 1959 two different scientists invented IC’s. Jack Kilby
from Texas Instruments made his first germanium IC during
1959 and Robert Noyce made his first silicon IC during the
same year. But ICs were not the same since the day of their
invention; they have evolved a long way. Integrated circuits are
often classified by the number of transistors and other
electronic components they contain:
• SSI (small-scale integration): Up to 100 electronic components per
chip
• MSI (medium-scale integration): From 100 to 3,000 electronic
components per chip
• LSI (large-scale integration): From 3,000 to 100,000 electronic
components per chip
• VLSI (very large-scale integration): From 100,000 to 1,000,000
electronic components per chip
• ULSI (ultra large-scale integration): More than 1 million electronic
components per chip

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Advantages of ICs
• Size of IC package is very small.
• The cost of IC’s is very low.
• Reduced power consumption.
• Suitable for high speed operations.
• The use of IC’s reduces the number of external wiring
connections because many of the connections are
internal to the package .

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Characteristics of Digital Logic Families
The main characteristics of logic families:
1. Fan-in
2. Propagation delay
3. Fan-out
4. Power dissipation
5. Noise margin
Fan-in
• It determines the number of inputs the logic gate
handle.
• For high-speed technologies, fan-in is often restricted
on gate primitives to no more than four or five.
• To build gates with larger fan-in, interconnected gates
with lower fan-in are used during
technology mapping. A mapping for a 7-input NAND
gate is made up of two 4- input NANDs and an
inverter as shown in figure:
Propagation Delay
• The propagation delay tp of a gate defines how quickly
it responds to a change at its input(s).
• It is measured between the 50% transition points of
the input and output waveforms.
Fan-out
• Fan-out specifies the number of standard loads driven by a gate
output i.e. Fan-out is a measure of the ability of a logic gate output to
drive a number of inputs of other logic gates of the same type.
• Gate with large fan-out are slower.

Fan-out = 4
Power Dissipation
• Power consumed by gate to change the state.
• this parameter does not include the power delivered
from another gate; rather, it represents the power
delivered to the gate from the power supply.
Power dissipation(Pd) = Vcc x Icc
where Vcc is supply voltage
and Icc is current drawn by circuit.
1 W = 1J/S ; means 1
Joule energy required
per second.
Noise Margin
• Maximum noise that a circuit can withstand without
affecting the output.
• Noise margin is the maximum noise voltage added to
an input signal of a digital circuit that does not cause an
undesirable change in the circuit output.
• The ability of circuits to operate reliably in a noise
environment is important in many applications. Noise
margin is expressed in volts and represents the
maximum noise signal that can be tolerated by the
gate.
Noise Margin
Switching Circuit
• A switching circuit is a type of electronic circuit that is designed to change its output
state based on the input conditions. It is a fundamental building block used in digital
electronics, where signals are represented as binary values (0s and 1s), and various
logical operations are performed.
• The most common types of switching circuits are based on logic gates. Logic gates are
digital building blocks that take one or more binary inputs and produce a single binary
output based on predefined logical rules. Some of the basic logic gates include:
 AND Gate: The output is 1 only if all inputs are 1.
 OR Gate: The output is 1 if at least one input is 1.
 NOT Gate: It has only one input and produces the opposite value of that input (i.e., if the input is
1, the output is 0, and vice versa).
 NAND Gate: The output is the complement of an AND gate (i.e., output is 0 if all inputs are 1,
otherwise, the output is 1).
 NOR Gate: The output is the complement of an OR gate (i.e., output is 0 if at least one input is 1,
otherwise, the output is 1).
• Switching circuits are made by Transistor, MOSFET and CMOS.
 Case I:
Transistor as Switch When Vin = 0V
 Base-Emitter voltage vI < 0.7V
 EBJ is considered reverse biased and CBJ also is reverse
biased
 Transistor is “fully-OFF” ( Cut-off region )
 Since iB=0, No Collector current flows ( iC = 0 )
 VOUT = vCE = VCC = ”1″ so, Transistor operates as an
“open switch”
Case II:
When Vin = +5V
 Base-Emitter voltage vI > 0.7V, i.e. EBJ is forward biased
 Base-Collector junction is forward biased
 Transistor is “fully-ON” ( saturation region )
 vCE=VCC - iCRC
 vCE = 0.1 to 0.3 ( ideal saturation )
 VOUT = VCE = ”0″
 iC(max )=iC(sat)=VCC/RC
 Transistor operates as a “closed switch”
 normally , vCE(sat)=0.1V
1
Digital Logic Families
• Digital logic family refers to the specific circuit
technology to which digital integrated circuits belong.
Different logic families have been introduced
commercially. Some of most popular are:
1. RTL ( Resistor Transistor Logic)
2. DTL (Diode Transistor logic)
3. TTL ( Transistor- Transistor Logic)
4. MOS ( Metal-Oxide Semiconductor, PMOS, NMOS)
5. CMOS ( Complementary MOS )
6. IIL (Integrated Injection Logic)
RTL (Resistor Transistor Logic)
• The resistor-transistor Logic(RTL) circuit is one of the basic logic
circuits in digital logic families. It is a bipolar saturated device. The RTL
logic is popular because of its simplicity.
• Performs AND, OR
and NOT operation.
Limitations:
• Propagation delay high
• Fan-in low,
• low noise immunity
• power dissipation high.
Figure: 2 Input NOR Gate
DTL (Diode Transistor Logic)
• This logic circuit has diodes at the input side and transistor at the
output side and so the name diode transistor logic. It has more
advantages than Resistor Transistor Logic.
• Speed higher than RTL

• When any one input is Low, diode is forward

biased and current flowing through diode
D1 or D2. Voltage drop at R1.
• So no sufficient voltage to drive transistor
ON and output voltage is high,
 7400 TTL (Transistor-Transistor Logic 2 Input NAND GATE)
• It is popular logic family due to low
power consumption and high speed.
• TTL NAND Gate operation
a) Low input in either A or B , or both
input low, base-emitter junction of Q1
is forward biased and reverse bias of
collector-base junction i.e. Q1 is
saturated. This causes Q2 turn OFF,
thereby causing Q4 to turn OFF.
A B Y Meanwhile, Q3 is turned ON and the
output is HIGH.
0 0 1
b) High input in both A and B, base-
0 1 1 emitter of Q1 is reversed biased and
1 0 1 base-collector junction is forward
1 1 0 biased. This causes Q2 to turn ON and
Q4 also turn ON and output is LOW.
 A Y
TTL NOT Gate 0 1
1 0
0 1
1 0

Operation: Explain yourself

A Case 1:
Case 2
MOS Logic
• The metal-oxide semiconductor (MOS) is a unipolar transistor that
depends upon the flow of only one type of carrier, which may be
electrons (n-channel) or holes (p-channel).
• P-MOS: ON by negative voltage at gate terminal
• N-MOS: ON by positive voltage at gate terminal
CMOS (Complementary MOS)
• Complementary MOS (CMOS) technology
uses one PMOS and one NMOS transistor connected in a
complementary fashion in all circuits.
• High packaging density.
• Very low power consumption.
Integrated Injection Logic (IIL)
• Integrated injection logic (IIL or I2L) is a class of digital
circuit technology built with multiple collector bipolar
junction transistors (BJT).
• Although the logic voltage levels are very close (High:
0.7V, Low: 0.2V), I2L has high noise immunity because
it operates by current instead of voltage. Sometimes
also known as Merged Transistor Logic.
• Low power as CMOS and high speed as TTL (used in
VLSI)
MOSFET Logic Circuit

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Complementary MOSFET (CMOS)
• CMOS referred to as complementary metal oxide semi-conductor.
Complementary refers to the complementary and symmetrical pairs
of N-type and P-type MOSFETs in its design.
• Main advantage of this is low static power consumption and noise
immunity.
• Since one transistor of the pair is always off, the series combination
draws significant power only momentarily during switching between
ON and OFF states.
• CMOS circuits use to implement logic gates.

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CMOS Construction

Figure: Construction details of CMOS

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CMOS Logic Gates
• CMOS Inverter

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 CMOS as Switch (Inverter)
+5V
Case I: Input A = low voltage
When low voltage is applied at input A,
Q1 (PMOS) is ON and Q2 (NMOS) is
OFF. So voltage across Q2 is equals to Q1(PMOS)
Vdd i.e. 5V (logic high).

Case II: Input A = high voltage

When high voltage is applied at input
A, Q1 (PMOS) is OFF and Q2 (NMOS) is
ON. So voltage across Q2 is equals to Q2 (NMOS)
low voltage.

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CMOS as NAND and AND Gate

CMOS NAND (74C00) CMOS AND

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CMOS as OR and NOR Gate

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8.7 Digital Devices Applications
• Digital electronics is crucial in this current world. Because, without
digital electronics it is not possible to speed up our work.
• The basic idea of digital electronics is mandatory for microprocessor
and micro-controller and also for computer architecture.
• Any application which involves microprocessor or a computer have
digital electronics in it.
• It can be security applications, error correcting and error detecting,
power saving circuits etc

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8.7.1 Multiplexing Displays
• A large number of embedded systems offer some form of display
device to convey information to the user.
Interfacing Seven-Segment Display:
• Seven segment displays commonly contain LED segments arranged as
a figure of eight pattern, with one common lead (anode or cathode)
and seven individual leads for each segment. When the common lead
is the cathode it is referred to as the common cathode (CC).

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Figure: (a) shows one of the possible configurations of interfacing a CC display
with the microcontroller.
The IC CD4511 is a BCD to seven-segment decoder/driver. The microcontroller
feeds the BCD equivalent of the digit to be displayed to the 4511 IC,

Figure:(a)- Interfacing a common cathode display with a microcontroller

Prepared By: Er. Ganesh Kumal 32

Seven segment displays can be connected directly without the use of a BCD to seven
segment decoder/driver.
In this case the seven-segment code of the digit is generated by the microcontroller
program itself.
Figure (b) shows the direct circuit connection for common anode display.

Figure: (b) Direct circuit connection for common anode display.

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If more than one display is to be used, the displays are time multiplexed.
The human eye cannot detect the blinking display if each display is relit every 10 ms.
The 10 ms time is divided by the number of display used to find the interval between
updating each display.
Figure (c) shows the multiplexed circuit for two CC displays. The IC 74138 is a 3-to-8
line decoder used for selecting the display.

Figure: (c)- Multiplexed circuit for CC display

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8.7.2 Frequency Counter
• A frequency counter is a circuit that can measure and display the frequency
of a signal.
• The basic block diagram for frequency counter is shown in figure below.
• It consists of a counter with its associated decoder/display circuitry and an
AND gate.
• The AND gate inputs include the pulses with unknown frequency, fx, and a
sample pulse with a known duration which controls how long the pulses
with unknown frequency are allowed to pass through the AND gate into
the counter.
• The sample pulse duration is fixed, thus, count after sampling interval is
directly proportional to the input unknown frequency.
• To get exact frequency sampling pulse width is kept 1 second, as shown in
figure.
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Prepared By: Er. Ganesh Kumal 36
8.7.3 Time Measurement

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Digital Clock

Prepared By: Er. Ganesh Kumal 38

Operation
• Figure in slide no. 11 shows the block diagram of
digital clock that displays seconds, minutes and hours.
• The ripple carry is applied to the enable(E) input of
another pair of divide by 60 (10 X 6) counter. This
counter counts minutes.
• The hour counter is implemented with a decade
counter and a flip-flop.
• Initially both decade counter and flip-flop are RESET, and
output of NAND gate is high.
• The decade counter advances from 0 to 9, the flip-flop is
toggled to the SET state by High-to-Low transition of QA.

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CONT…
• At this moment count is 10 in decimal ( the decade
counter is in the 0 state and the flip-flop is set).
• After next two pulses, the total count advances to 11
and 12 in decimal.
• In state 13, QB and QA outputs are high and the flip-
flop is SET, so the output of NAND gate is low.
• This activates the asynchronous load input of the
decade counter, presetting the decade counter to
state 1 by the data inputs (0001). As the output of
NAND gate is also connected to J input, flip-flop
Reset. This logic makes counter to recycle from 12
back to 1 rather than back to 0.

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 QD QC QB QA DECIMAL
COUNT
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
Negative
edge, flip- 1 0 0 1 9
flop set Recycle
1 0 0 0 0 10
1 0 0 0 1 11
1 0 0 1 0 12
0 0 0 0 1 1
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Thank You!
Any Queries??
5/6 TH
• 5,8,34,44,