PANIMALAR ENGINEERING COLLEGE

(An Autonomous Institution, Affiliated to Anna University Chennai)

QUESTION BANK
Details of the Course
Name of the Department : Artificial Intelligence & Data Science
Name of the Course : Internals of Computer Systems
Course Code : 23AD1301
Semester : III
Common To Programme(s) :
Instructions
Blooms Level:Blooms Level 1 & 2 is Lower Order (LO) Cognitive type, Blooms Level 3 & 4 is Intermediate Order
Cognitive Type (IO) and Blooms Level 5 & 6 is Higher Order (HO) cognitive type.

2 Marks:Foreach unit five questions should be of lower order (LO) cognitive type and five Questions should be of
Intermediate order (IO) cognitive type.

13 /15 /16 Marks:For each Unit four questions should be of lower order (LO) cognitive type i.e. remembrance type
questions, five should be of intermediate order (IO) cognitive type i.e. understanding type questions and One Question
should be on Higher Order (HO)Application / Design / Analysis / Evaluation / Creativity / Case study questions.
* HO Order is not applicable if the Question Pattern does not have Part C. In Such cases consider HO as IO.
** If the Mark for Part B &C is less than the maximum mark of the Question, Sub Divisions shall be added.
Course Outcome: (List the Course Outcomes of the Course)
CO1:Simplify complex Boolean functions using K-Map
Co2:Design and Analyze Combinational Circuits
CO3:Analyze the design of Sequential Circuits
CO4:Discuss and point out the various Memory management schemes
CO5:Point out the hazards present in a pipeline and suggest remedies
CO6:Critically analyze the various characteristics of I/O devices and their interfaces
Bloom’s Level: BL1 - Remembering, BL2 - Understanding, BL3 - Applying, BL4 - Analyzing, BL5– Evaluating,BL6 - Creating.

Diagrams, Table Values, Equations must be legible and clear.

UNIT- I - DIGITAL FUNDAMENTALS
Marks
Course
PART A ( 2 Marks) Bloom’s Level
Outcome
Allotte
d
1. What is binary logic? [BL1] [CO1] [2]

2. What is a Karnaugh map? [BL1] [CO1] [2]

3. What are basic properties of Boolean algebra? [BL1] [CO1] [2]

4. Explain why some gates are called universal gates in Boolean logic. [BL2] [CO1] [2]

5. Convert (101011)2 into its decimal equivalent. [BL2] [CO1] [2]

6. Implement the techniques for simplifying Boolean functions. [BL3] [CO1] [2]

7. Assess what "don't care" conditions represent in Karnaugh maps (K- [BL4] [CO1] [2]
maps).
8. Analyze how to convert the octal number (125) 8 into its decimal [BL4] [CO1] [2]
equivalent.
9. Examine the procedure for converting the binary number [BL4] [CO1] [2]
(1011100111011)2 into both its octal and hexadecimal equivalents.
10. Analyze the function and role of an inverter in logic gates. [BL4] [CO1] [2]

Couse Instructor Course Coordinator Head of the Department

Name & Designation Name & Designation
 Descriptive Questions ( 13 /15/16 Marks)
1. Identify and list the canonical Sum-of-Products (SOP) and Product-of- [BL1] [CO1] [13]
Sums (POS) forms of a given Boolean expression AC′ + B′D + A′CD +
ABCD
2. Explain how the basic logic gates (AND, OR, NOT) can be [BL1] [CO1] [13]
represented using only NAND and NOR gates, providing suitable logic
diagrams and truth tables.
3. Explain the conversion methods between different the following [BL1] [CO1] [13]
number systems with suitable examples.
i) Decimal to binary and vice versa
ii) Octal to decimal and vice versa
iii) Hexadecimal to decimal and vice versa
4. Outline the methods to perform the following mathematical operations. [BL2] [CO1] [13]
i) Convert (4562)10 to Hexadecimal Number
ii) Convert (213)8 to Binary Number.
iii)Convert the decimal number (0.39)10 to octal number in radix
format.
iv) Find 9’s complement for 456
5. Analyze the foundational theorem and essential properties of Boolean [BL3] [CO1] [13]
algebra.
6. Apply Karnaugh Map (K-map) techniques to obtain the minimal Sum- [BL3] [CO1] [13]
of-Products (SOP) expression for the given minterms
Σm (0, 1, 2, 4, 6, 9, 11, 12, 13).
7. For the following expressions, determine the maxterms and minterms, [BL3] [CO1] [13]
and then express the terms using Karnaugh Maps (K-Maps):
i) F = AC' + ABC' + A'BC
ii) Y = AC + AB + BC
8. Examine the processes of addition and subtraction using 1’s and 2’s [BL4] [CO1] [13]
complement methods, including detailed examples to demonstrate each
step.
9. Analyze and design a logic circuit based on the following Boolean [BL4] [CO1] [13]
expression:

10. Evaluate and simplify the function using Karnaugh Map (K-map) and [BL5] [CO1] [15]
implement it using the minimum number of logic gates.
F = (2, 9, 10,12, 13) + D (1, 5, 14)
Also list the limitations of Karnaugh map.

Couse Instructor Course Coordinator Head of the Department

Name & Designation Name & Designation
 UNIT- II - COMBINATIONAL AND SEQUENTIAL CIRCUITS
Marks
Course
PART A ( 2 Marks) Bloom’s Level
Outcome
Allotte
d
1. Define combinational logic. [BL1] [CO2] [2]
2. Define seven segment decoder. [BL1] [CO2] [2]
3. Define encoder and decoder. List its types. [BL1] [CO2] [2]
4. Differentiate half adder and full adder [BL3] [CO2] [2]
5. Compare and contrast multiplexers and demultiplexers, and give their
[BL3] [CO2] [2]
different types and applications.
6. Discuss the use of BCD adder? [BL3] [CO2] [2]
7. Discuss the working of flip flop. List its types. [BL3] [CO3] [2]
8. Analyze the purpose of sequential circuit? [BL4] [CO3] [2]
9. Analyze the functionality of an edge-triggered flip-flop. [BL4] [CO3] [2]
10. Examine the design and operation of a master-slave flip-flop. [BL4] [CO3] [2]
Descriptive Questions ( 13 /15/16 Marks)
1. What are the logic diagrams and truth tables for a half adder, full
[BL1] [CO2] [13]
adder, half subtractor, and full subtractor?
2. How do you construct a BCD adder using two 4-bit parallel binary
[BL1] [CO2] [13]
adders and additional logic?
3. How can you analyze an 8 x 1 multiplexer to implement the following
logic functions?
[BL2] [CO2] [13]
i) F(w,x,y,z)=∑m (0,1,2,3,4,10,11,14,15)
ii) F(A,B,C,D)= ∑m(1,3,4,11,12,13,14,15)
4. How can you explain a BCD to Seven-Segment Decoder using a truth
[BL2] [CO2] [13]
table, Karnaugh Map (K-Map), and Boolean expressions?
5. How can you analyze an 8 x 1 and 4x1 multiplexers to implement the
following logic functions?
[BL2] [CO2] [13]
i) F=Σm (0,1,2,4,5,10,11,12,14)
ii) F (A, B, C, D) = ∑m (0, 2, 6, 10, 11, 12, 13) + ∑d (3, 8, 14)
6. In what ways can program counters be utilized to manage instruction
[BL3] [CO3] [13]
sequencing and branching in CPU operations? Explain.
7. Analyze how edge-triggered flip-flops affect timing and data storage in
digital circuits, and design a basic system to improve their [BL4] [CO3] [13]
performance.
8. Evaluate the functionality of universal shift registers [BL4] [CO2] [13]
9. Evaluate the effectiveness and potential issues of converting a T flip-
[BL4] [CO2] [13]
flop to a D flip-flop using additional logic gates.
10. Design a 4-bit synchronous counter, ensuring all flip-flops are [BL6] [CO2] [15]
synchronized, and evaluate its performance and reliability.

Couse Instructor Course Coordinator Head of the Department

Name & Designation Name & Designation
 UNIT- III -COMPUTER FUNDAMENTALS
Marks
Course
PART A ( 2 Marks) Bloom’s Level
Outcome
Allotte
d
1. What are the functional units of a computer? [BL1] [CO4] [2]

2. Define instruction set. [BL1] [CO4] [2]

3. What are the key differences between basic instruction types? [BL2] [CO4] [2]

4. What is the structure and purpose of the instruction format used in [BL2] [CO4] [2]
computer architecture?
5. Explain the purpose of the control unit in a computer system. [BL2] [CO4] [2]

6. Discuss the terms response time and throughput [BL3] [CO4] [2]

7. Analyzse the purpose of Operands in computer hardware [BL4] [CO4] [2]

instructions.
8. Evaluate the impact of instruction sequencing on program execution in [BL4] [CO4] [2]
a computer system
9. Analyze the various types of addressing modes and their impact on [BL4] [CO4] [2]
instruction execution.
10. Analyze the impact of Instruction Set Architecture (ISA) on the [BL4] [CO4] [2]
performance and functionality of a computer system.
Descriptive Questions ( 13 /15/16 Marks)
1. Describe the Von Neumann Architecture and explain the purpose of [BL1] [CO4] [13]
its components.
2. Identify and describe the operation and operands of computer [BL1] [CO4] [13]
hardware instructions.
3. Explain instructions and their notations in computer systems. [BL2] [CO4] [13]

4. Describe the basic types of computer instructions and their functions. [BL2] [CO4] [13]

5. Outline the types of addressing modes used in computer architecture. [BL2] [CO4] [13]

6. Illustrate how ISA, addressing modes, and machine instructions are [BL3] [CO4] [13]
used in computer systems to facilitate efficient processing.
7. Demonstrate instruction formats with examples and explain how they [BL3] [CO4] [13]
are used in computer systems.
8. Analyze the process of encoding machine instructions and its impact [BL4] [CO4] [13]
on instruction execution and system performance.
9. Evaluate the method in which machine instructions and assembly [BL4] [CO4] [13]
language interact.
10. Design the instruction formats with suitable example. [BL5] [CO4] [15]

UNIT- IV -PROCESSORS
Marks
Course
PART A ( 2 Marks) Bloom’s Level
Outcome
Allotte
d
1. When does a race condition occur in digital circuits? [BL1] [CO5] [2]

2. What is a merger graph? [BL1] [CO5] [2]

3. What is the major limitation of the pipelining technique? [BL1] [CO5] [2]

Couse Instructor Course Coordinator Head of the Department

Name & Designation Name & Designation
 4. How can data hazards be prevented in pipelining? [BL2] [CO5] [2]

5. Explain shared row state assignment in digital circuit design with a [BL2] [CO5] [2]
short note.
6. How would you define a data hazard and describe its impact on the [BL3] [CO5] [2]
execution of instructions in a pipeline?
7. Analyze the two steps involved in executing an instruction. [BL4] [CO5] [2]

8. Analyze the five stages involved in the execution of an instruction in a [BL4] [CO5] [2]
typical processor.
9. Analyze the concept of pipelining and its impact on processor [BL4] [CO5] [2]
performance.
10. Examine the effects of instruction and control hazards on the [BL4] [CO5] [2]
efficiency of a pipelined processor
Descriptive Questions ( 13 /15/16 Marks)
1. What are the steps to create a single or combined data path, and can [BL1] [CO5] [13]
you provide a suitable diagram?
2. Illustrate the MIPS data path for: [BL1] [CO5] [13]
i) Fetching the instruction and incrementing the PC
ii) Executing arithmetic and logic instructions
iii) Executing a memory-reference instruction
3. Explain how to design the Control Unit for a MIPS data path. [BL2] [CO5] [13]

4. Describe the methods of pipelined execution. [BL2] [CO5] [13]

5. Discuss the methods employed to manage data hazards. [BL2] [CO5] [13]

6. Write a detailed note on Control hazards [BL3] [CO5] [13]

7. Illustrate with a detailed example how instruction execution works. [BL3] [CO5] [13]

8. Analyze the concept of microprogrammed control and its components [BL4] [CO5] [13]
in detail.
9. Examine how the design of a data path and control unit influences the [BL4] [CO5] [13]
efficiency of instruction execution.
10. Evaluate how integrating data path design, control units, and [BL5] [CO5] [15]
pipelining optimizes processor performance and addresses data and
control hazards.

UNIT- V -MEMORY AND I/O

Marks
Course
PART A ( 2 Marks) Bloom’s Level
Outcome
Allotte
d
1. What is ROM (Read-Only Memory), and what are its different types? [BL1] [CO6] [2]

2. Define address and word. [BL1] [CO6] [2]

3. What are the major differences between PLA (Programmable Logic [BL1] [CO6] [2]
Array) and PAL (Programmable Array Logic)?
4. Calculate the total number of words a 16x8 memory can store, and [BL2] [CO6] [2]
explain the significance of the dimensions in digital memory systems.
5. Discuss the term "volatile" as applied to RAM (Random Access [BL2] [CO6] [2]
Memory).
6. How would you define memory access time, and what factors [BL3] [CO6] [2]
influence it in a digital memory system?
7. Explain the concept of memory cycle time and its significance in the [BL3] [CO6] [2]
performance of a memory system.

Couse Instructor Course Coordinator Head of the Department

Name & Designation Name & Designation
 8. Analyze the functions of a Memory Management Unit (MMU) and how [BL4] [CO6] [2]
it enhances the efficiency of a computer system.
9. Evaluate the concepts of memory latency and bandwidth, and discuss [BL4] [CO6] [2]
their impact on system performance.
10. Analyze the definition of Direct Memory Access (DMA) and its role in [BL4] [CO6] [2]
optimizing data transfer within computer systems.
Descriptive Questions ( 13 /15/16 Marks)
1. What is the memory hierarchy? Explain in detail. [BL1] [CO6] [13]

2. What are the types of cache memory? [BL1] [CO6] [13]

3. Explain the different cache replacement strategies. [BL2] [CO6] [13]

4. Describe the process of virtual to physical address translation. [BL2] [CO6] [13]

5. Write a detailed note on interrupts and describe the steps involved in [BL2] [CO6] [13]
handling them.
6. Illustrate and explain the DMA controller with a block diagram, and [BL3] [CO6] [13]
describe its role in data transfer between memory and I/O devices.
7. Analyze the concepts and techniques involved in memory [BL4] [CO6] [13]
management, including memory allocation, paging, and segmentation,
and their impact on system performance.
8. Discuss how mapping and replacement techniques in cache memory [BL4] [CO6] [13]
contribute to efficient memory management.
9. Discuss the interaction between DMA and memory management [BL4] [CO6] [13]
techniques.
10. Evaluate how interrupt-driven I/O enhances data transfer efficiency [BL5] [CO6] [15]
and its integration with memory management and I/O systems

Couse Instructor Course Coordinator Head of the Department

Name & Designation Name & Designation