TI

TMS320C28x™ DSP Workshop

Student Guide

C28xmdw
Revision 6.22
February 2007
Technical Training
Organization
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Revision History
October 2001 – Revision 1.0 February 2004 – Revision 5.0
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May 2002 – Revision 3.0 January 2005 – Revision 5.2
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ii TMS320C28x DSP Workshop - Introduction

 TMS320C28x™ DSP Workshop

TMS320C28x™ DSP Workshop

TMS320C28x™ DSP Workshop

eZdsp™ F2808 Starter Kit

Texas Instruments
Technical Training
T TO
Technical Training
Organization eZdsp is a trademark of Spectrum Digital, Inc. Copyright © 2007 Texas Instruments. All rights reserved.

Introductions
Introductions
‹ Name
‹ Company
‹ Project Responsibilities
‹ DSP / Microcontroller Experience
‹ TMS320 DSP Experience
‹ Hardware / Software - Assembly / C
‹ Interests

TMS320C28x DSP Workshop - Introduction iii

TMS320C28x™ DSP Workshop

TMS320C28x™ DSP Workshop Outline

TMS320C28x™ DSP Workshop Outline
1. Architecture Overview
2. Programming Development Environment
Lab: “User" linker command file
Lab: DSP/BIOS configuration tool
3. Peripheral Register Header Files
4. Reset and Interrupts
5. System Initialization
Lab: Watchdog and interrupts
6. Analog-to-Digital Converter
Lab: Build a data acquisition system
7. Control Peripherals
Lab: Generate and graph a PWM waveform
8. Numerical Concepts and IQ Math
Lab: Low-pass filter the PWM waveform
9. Using DSP/BIOS
Lab: Change the code to use DSP/BIOS
10. System Design
Lab: Run the code from flash memory
11. Communications
12. Support Resources

eZdsp™ F2808 Hardware

eZdsp™ F2808 Hardware
SCI-A SCI-B eCAN-A eCAN-B
(P10) (J10) (P11) (J11)
JTAG Interface (P1) TMS320F2808
DSP
USB JTAG 100 MIPS
Controller
Interface
(J201)

LED On-Chip:
(DS1) 18K RAM
+5V 64K Flash
1K OTP
Power
Connector
(P6) +5V ANALOG
Interface
(P5/P9)

I/O Interface Bootloader 256K Bit 20 MHz LED

(P8) GPIO Pins Serial Clock (DS2)
EEPROM GPIO34

iv TMS320C28x DSP Workshop - Introduction

 Architecture Overview

Introduction
This architecture overview introduces the basic architecture of the TMS320C28x (C28x) series of
Digital Signal Processors from Texas Instruments. The C28x series adds a new level of general
purpose processing ability unseen in any previous DSP chips. The C28x is ideal for applications
combining DSP, standard microcontroller processing, efficient C code execution, or operating
system tasks.

Unless otherwise noted, the terms C28x and C280x refer to TMS320C280x and TMS320F280x
devices throughout the remainder of these notes. For specific details and differences please refer
to the device data sheet and user’s guide.

Learning Objectives
When this module is complete, you should have a basic understanding of the C28x architecture
and how all of its components work together to create a high-end, uniprocessor control system.

Learning Objectives

‹ Identify the three main components

of the C28x
‹ List the key features of the C28x
CPU
‹ Identify the memory capabilities of
the C28x
‹ Identify the peripherals available on
the C28x

TMS320C28x DSP Workshop - Architecture Overview 1-1

Module Topics

Module Topics
Architecture Overview.............................................................................................................................. 1-1

Module Topics......................................................................................................................................... 1-2

What is the TMS320C28x?...................................................................................................................... 1-3
TMS320C28x Internal Bussing .......................................................................................................... 1-4
C28x CPU ............................................................................................................................................... 1-5
Multiplier, ALU, and Shifters............................................................................................................. 1-6
Special Instructions............................................................................................................................. 1-7
Pipeline Advantage............................................................................................................................. 1-8
Memory ................................................................................................................................................... 1-9
Memory Map ...................................................................................................................................... 1-9
Code Security Module (CSM) ...........................................................................................................1-10
Peripherals .........................................................................................................................................1-10
Fast Interrupt Response .........................................................................................................................1-11
C28x Mode.............................................................................................................................................1-12
Reset.......................................................................................................................................................1-13
Summary ................................................................................................................................................1-14

1-2 TMS320C28x DSP Workshop - Architecture Overview

 What is the TMS320C28x?

What is the TMS320C28x?

The TMS320C28x is a 32-bit fixed point DSP that specializes in high performance control
applications such as, robotics, industrial automation, mass storage devices, lighting, optical
networking, power supplies, and other control applications needing a single processor to solve a
high performance application.

C28x Block Diagram

Program Bus
ePWM

Boot eCAP
Sectored ROM
RAM eQEP
Flash

12-bit ADC

Watchdog

PIE
32-bit R-M-W Interrupt
32x32 bit Manager CAN 2.0B
Auxiliary Atomic
Multiplier
Registers ALU I2C
3
32 bit SCI
Realtime Register Bus Timers SPI
JTAG
CPU

Data Bus GPIO

The C28x architecture can be divided into 3 functional blocks:

• CPU and busing

• Memory

• Peripherals

TMS320C28x DSP Workshop - Architecture Overview 1-3

What is the TMS320C28x?

TMS320C28x Internal Bussing

As with many DSP type devices, multiple busses are used to move data between the memories
and peripherals and the CPU. The C28x memory bus architecture contains:

• A program read bus (22 bit address line and 32 bit data line)

• A data read bus (32 bit address line and 32 bit data line)

• A data write bus (32 bit address line and 32 bit data line)

C28x Internal Bus Structure

Program Program Address Bus (22)
PC Program
Program-read Data Bus (32)
Decoder (4M* 16)
Data-read Address Bus (32)

Data-read Data Bus (32) Data

(4G * 16)
Registers Execution Debug
ARAU MPY32x32 Memory
Real-Time
SP R-M-W Emulation
ALU
DP @X Atomic &
XT JTAG
XAR0 ALU Test Standard
to P
ACC Engine Peripherals
XAR7

Register Bus / Result Bus External

Interfaces
Data/Program-write Data Bus (32)
Data-write Address Bus (32)

The 32-bit-wide data busses enable single cycle 32-bit operations. This multiple bus architecture,
known as a Harvard Bus Architecture enables the C28x to fetch an instruction, read a data value
and write a data value in a single cycle. All peripherals and memories are attached to the memory
bus and will prioritize memory accesses.

1-4 TMS320C28x DSP Workshop - Architecture Overview

 C28x CPU

C28x CPU
The C28x is a highly integrated, high performance solution for demanding control applications.
The C28x is a cross between a general microcontroller and a digital signal processor, balancing
the code density of a RISC chip and the execution speed of a DSP with the architecture,
firmware, and development tools of a microcontroller.

The DSP features include a modified Harvard architecture and circular addressing. The RISC
features are single-cycle instruction execution, register-to-register operations, and modified
Harvard architecture. The microcontroller features include ease of use through an intuitive
instruction set, byte packing and unpacking, and bit manipulation.

C28x CPU
‹ MCU/DSP balancing code density
& execution time.
‹ Supports 32-bit instructions
Program Bus for improved execution time;
‹Supports 16-bit instructions
for improved code efficiency
‹ 32-bit fixed-point DSP
PIE
32-bit 32x32 bit R-M-W
32-bit R-M-W Interrupt ‹ 32 x 32 bit fixed-point MAC
32x32 bit Manager
Auxiliary Multiplier Atomic
Auxiliary Atomic ‹ Dual 16 x 16 single-cycle fixed-
Registers Multiplier ALU
Registers ALU 33 point MAC (DMAC)
32 ‹ 32-/64-bit saturation
32bit
bit
Register Bus Timers
Realtime
Realtime Timers ‹ 64/32 and 32/32 modulus division
CPU
JTAG
JTAG ‹ Fast interrupt service time
Data Bus ‹ Single cycle read-modify-write
instructions
‹ Unique real-time debugging
capabilities
‹ Upward code compatibility

The C28x design supports an efficient C engine with hardware that allows the C compiler to
generate compact code. Multiple busses and an internal register bus allow an efficient and
flexible way to operate on the data. The architecture is also supported by powerful addressing
modes, which allow the compiler as well as the assembly programmer to generate compact code
that is almost one to one corresponded to the C code.

The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are
handled by microcontroller devices. This efficiency removes the need for a second processor in
many systems.

The C28x is one of several members of the fixed-point generations of digital signal processors
(DSPs) in the TMS320 family. The C28x is source-code and object-code compatible with the
C27x. In addition, the C28x is source code compatible with the 24x/240x DSP and previously
written code can be reassembled to run on a C28x device. This allows for migration of existing
code onto the C28x.

TMS320C28x DSP Workshop - Architecture Overview 1-5

C28x CPU

Multiplier, ALU, and Shifters

C28x Multiplier and ALU / Shifters
Program Bus
32
Data Bus
XT (32) or T/TL 16/32
16
MULTIPLIER
32 32 x 32 or 8/16/32
Shift R/L (0-16) Dual 16 x 16
32
P (32) or PH/PL
32
32

32 Shift R/L (0-16)

32

ALU (32)
32
ACC (32)
AH (16) AL (16)
AH.MSB AH.LSB AL.MSB AL.LSB

• 32
Shift R/L (0-16)
32
Data Bus

The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the
C28x to efficiently handle higher numerical resolution problems that would otherwise demand a
more expensive floating-point processor solution. Along with this is the capability to perform
two 16 x 16-bit multiply accumulate instructions simultaneously or Dual MACs (DMAC).

C28x XARn, DP and Memory

Data Bus
Program Bus

6 LSB
XAR0 DP (16) from IR
XAR1
XAR2
32 22
XAR3
XAR4 MUX
XAR5
XAR6
XAR7
MUX

ARAU

Data Memory
XARn → 32-bits
ARn → 16-bits

1-6 TMS320C28x DSP Workshop - Architecture Overview

 C28x CPU

Special Instructions
C28x Atomic Read/Modify/Write
‹ Atomic Instructions Benefits:
LOAD ¾ Simpler programming
READ

¾ Smaller, faster code

Registers CPU ALU / MPY Mem
¾ Uninterruptible (Atomic)
WRITE

STORE ¾ More efficient compiler

Standard Load/Store Atomic Read/Modify/Write

DINT
AND *XAR2,#1234h
MOV AL,*XAR2
AND AL,#1234h 2 words / 1 cycles
MOV *XAR2,AL
EINT
6 words / 6 cycles

Atomics are small common instructions that are non-interuptable. The atomic ALU capability
supports instructions and code that manages tasks and processes. These instructions usually
execute several cycles faster than traditional coding.

TMS320C28x DSP Workshop - Architecture Overview 1-7

C28x CPU

Pipeline Advantage
C28x Pipeline
A F1 F2 D1 D2 R1 R2 X W 8-stage pipeline
B F1 F2 D1 D2 R1 R2 X W
C F1 F2 D1 D2 R1 R2 X W

D F1 F2 D1 D2 R1 R2 X W
E & G Access
E F1 F2 D1 D2 R1 R2 X W same address
F F1 F2 D1 D2 R1 R2 X W

G F1 F2 D1 D2 R11 R2 RX2 W
X W

H F1 F2 D1 D2 R1 R X2 W
R21 R X W

F1: Instruction Address

F2: Instruction Content Protected Pipeline
D1: Decode Instruction
D2: Resolve Operand Addr ¾ Order of results are as written in
R1: Operand Address source code
R2: Get Operand
X: CPU doing “real” work
¾ Programmer need not worry about
W: store content to memory the pipeline

The C28x uses a special 8-stage protected pipeline to maximize the throughput. This protected
pipeline prevents a write to and a read from the same location from occurring out of order.

This pipelining also enables the C28x to execute at high speeds without resorting to expensive
high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional
discontinuities. Special store conditional operations further improve performance.

1-8 TMS320C28x DSP Workshop - Architecture Overview

 Memory

Memory
The memory space on the C28x is divided into program and data space. There are several
different types of memory available that can be used as both program or data space. They include
the flash memory, single access RAM (SARAM), expanded SARAM, and Boot ROM which is
factory programmed with boot software routines or standard tables used in math related
algorithms.

Memory Map
The C28x CPU contains no memory, but can access memory both on and off the chip. The C28x
uses 32-bit data addresses and 22-bit program addresses. This allows for a total address reach of
4G words (1 word = 16 bits) in data space and 4M words in program space. Memory blocks on
all C28x designs are uniformly mapped to both program and data space.

This memory map shows the different blocks of memory available to the program and data space.

TMS320F2808 Memory Map

Data | Program
0x00 0000 MO SARAM (1Kw)
0x00 0400 M1 SARAM (1Kw)
0x00 0800 PF 0 (2Kw) reserved
0x00 0D00 PIE vector
(256w) reserved
ENPIE=1
0x00 0E00 reserved
0x00 6000 PF 1 (4Kw) reserved
0x00 7000 PF 2 (4Kw) reserved
0x00 8000 LO SARAM (4Kw)
0x00 9000 L1 SARAM (4Kw)
0x00 A000 HO SARAM (8Kw)
0x00 C000 reserved
0x3D 7800 OTP (1Kw)
0x3D 7C00 reserved Dual
0x3E 8000 FLASH (64Kw) Mapped
0x3F 7FF8 128-Bit Password
0x3F 8000 LO SARAM (4Kw)
0x3F 9000 L1 SARAM (4Kw)
0x3F A000 HO SARAM (8Kw)
0x3F C000 reserved
0x3F F000 Boot ROM (4Kw) CSM: LO, L1
0x3F FFC0 BROM vector (32w)
VMAP=1 ENPIE=0 OTP, FLASH

TMS320C28x DSP Workshop - Architecture Overview 1-9

Memory

Code Security Module (CSM)

Code Security Module
‹ Prevents reverse engineering and
protects valuable intellectual property
0x00 8000 LO SARAM (4Kw)
0x00 9000 L1 SARAM (4Kw)
0x00 A000
0x00 C000 reserved
0x3D 7800 OTP (1Kw) Dual
0x3D 7C00 reserved Mapped
0x3E 8000 FLASH (64Kw)
0x3F 7FF8 128-Bit Password
0x3F 8000 LO SARAM (4Kw)
0x3F 9000 L1 SARAM (4Kw)

‹ 128-bit user defined password is stored in Flash

‹ 128-bits = 2128 = 3.4 x 1038 possible passwords
‹ To try 1 password every 8 cycles at 100 MHz, it
would take at least 8.8 x 1023 years to try all
possible combinations!

Peripherals
The C28x comes with many built in peripherals optimized to support control applications. These
peripherals vary depending on which C28x device you choose.

• ePWM • SPI

• eCAP • SCI

• eQEP • I2C

• Analog-to-Digital Converter • CAN

• Watchdog Timer • GPIO

1 - 10 TMS320C28x DSP Workshop - Architecture Overview

 Fast Interrupt Response

Fast Interrupt Response

The fast interrupt response, with automatic context save of critical registers, resulting in a device
that is capable of servicing many asynchronous events with minimal latency. C28x implements a
zero cycle penalty to do 14 registers context saved and restored during an interrupt. This feature
helps reduces the interrupt service routine overheads.

C28x Fast Interrupt Response Manager

¾ 96 dedicated PIE
vectors
¾ No software decision
making required PIE module 28x CPU Interrupt logic

Peripheral Interrupts 12x8 = 96

For 96
¾ Direct access to RAM interrupts

vectors INT1 to
INT12 28x
¾ Auto flags update 96
IFR IER INTM CPU
12 interrupts
¾ Concurrent auto PIE
Register
context save
Map

Auto Context Save

T ST0
AH AL
PH PL
AR1 (L) AR0 (L)
DP ST1
DBSTAT IER
PC(msw) PC(lsw)

TMS320C28x DSP Workshop - Architecture Overview 1 - 11

C28x Mode

C28x Mode
The C28x is one of several members of the fixed-point generations of digital signal processors
(DSPs) in the TMS320 family. The C28x is source-code and object-code compatible with the
C27x. In addition, the C28x is source code compatable with the 24x/240x DSP and previously
written code can be reassembled to run on a C28x device. This allows for migration of existing
code onto the C28x.

C28x / C24x Modes

Mode Type Mode Bits Compiler

OBJMODE AMODE Option

C24x Mode 1 1 -v28 -m20

C28x Mode 1 0 -v28 (workshop)

Test Mode (default) 0 0 -v27

Reserved 0 1

¾ C24x source-compatible mode:

¾ Allows you to run C24x source code which has been reassembled

using the C28x code generation tools (need new vectors)

¾ C28x mode:
¾ Can take advantage of all the C28x native features

1 - 12 TMS320C28x DSP Workshop - Architecture Overview

 Reset

Reset
Reset – Bootloader

Reset
OBJMODE=0 AMODE=0
ENPIE=0 VMAP=1

Bootloader sets
OBJMODE = 1
AMODE = 0
Reset vector fetched
from boot ROM Boot determined by
state of GPIO pins
0x3F FFC0

Execution
Entry Point
Note: M0 SARAM
Details of the various boot options will be
discussed in the Reset and Interrupts module

TMS320C28x DSP Workshop - Architecture Overview 1 - 13

Summary

Summary
Summary
‹ High performance 32-bit DSP
‹ 32 x 32 bit or dual 16 x 16 bit MAC
‹ Atomic read-modify-write instructions
‹ 8-stage fully protected pipeline
‹ Fast interrupt response manager
‹ 64Kw on-chip flash memory
‹ Code security module (CSM)
‹ Control peripherals
‹ 12-bit ADC module
‹ 35 shared GPIO pins
‹ Watchdog timer
‹ Communications peripherals

1 - 14 TMS320C28x DSP Workshop - Architecture Overview

 Programming Development Environment

Introduction
This module will explain how to use Code Composer Studio (CCS) integrated development
environment (IDE) tools to develop a program. Creating projects and setting building options
will be covered. Use and the purpose of the linker command file will be described. Additionally,
the DSP/BIOS Configuration Tool will be used to handle system memory and system setup.

Learning Objectives
Learning Objectives

‹ Use Code Composer Studio to:

Š Create a Project
Š Set Build Options
‹ Create a user linker command file which:
Š Describes a system’s available memory
Š Indicates where sections will be placed
in memory
‹ Use DSP/BIOS Configuration Tool to:
Š Handle system memory and system setup
Š Create a .cdb and .cmd file

TMS320C28x DSP Workshop - Programming Development Environment 2-1

Module Topics

Module Topics
Programming Development Environment .............................................................................................. 2-1

Module Topics......................................................................................................................................... 2-2

Code Composer Studio ........................................................................................................................... 2-3
Software Development and COFF Concepts...................................................................................... 2-3
Projects ............................................................................................................................................... 2-5
Build Options...................................................................................................................................... 2-6
Creating a Linker Command File ........................................................................................................... 2-9
Sections .............................................................................................................................................. 2-9
Linker Command Files (.cmd) .........................................................................................................2-12
Memory-Map Description .................................................................................................................2-12
Section Placement..............................................................................................................................2-14
Exercise 2a.............................................................................................................................................2-15
Summary: Linker Command File ......................................................................................................2-16
Lab 2a: Linker Command File...............................................................................................................2-17
DSP/BIOS Configuration Tool...............................................................................................................2-21
Lab 2b: DSP/BIOS Configuration Tool .................................................................................................2-26
Solutions.................................................................................................................................................2-30

2-2 TMS320C28x DSP Workshop - Programming Development Environment

 Code Composer Studio

Code Composer Studio

Software Development and COFF Concepts
In an effort to standardize the software development process, TI uses the Common Object File
Format (COFF). COFF has several features which make it a powerful software development
system. It is most useful when the development task is split between several programmers.

Each file of code, called a module, may be written independently, including the specification of
all resources necessary for the proper operation of the module. Modules can be written using
Code Composer Studio (CCS) or any text editor capable of providing a simple ASCII file output.
The expected extension of a source file is .ASM for assembly and .C for C programs.

Code Composer Studio

Build SIM
Compile lnk.cmd Probe In

eZdsp™
Asm Link Debug
EVM
DSP/BIOS
DSP/BIOS Probe Out
Edit Config Third
Libraries Graphs
Tool Party
Profiling

XDS
‹ Code Composer Studio includes:
Š Integrated Edit/Debug GUI DSP
Š Code Generation Tools Board
Š DSP/BIOS

Code Composer Studio includes a built-in editor, compiler, assembler, linker, and an automatic
build process. Additionally, tools to connect file input and output, as well as built-in graph
displays for output are available. Other features can be added using the plug-ins capability

Numerous modules are joined to form a complete program by using the linker. The linker
efficiently allocates the resources available on the device to each module in the system. The
linker uses a command (.CMD) file to identify the memory resources and placement of where the
various sections within each module are to go. Outputs of the linking process includes the linked
object file (.OUT), which runs on the DSP, and can include a .MAP file which identifies where
each linked section is located.

The high level of modularity and portability resulting from this system simplifies the processes of
verification, debug and maintenance. The process of COFF development is presented in greater
detail in the following paragraphs.

TMS320C28x DSP Workshop - Programming Development Environment 2-3

Code Composer Studio

The concept of COFF tools is to allow modular development of software independent of

hardware concerns. An individual assembly language file is written to perform a single task and
may be linked with several other tasks to achieve a more complex total system.

Writing code in modular form permits code to be developed by several people working in parallel
so the development cycle is shortened. Debugging and upgrading code is faster, since
components of the system, rather than the entire system, is being operated upon. Also, new
systems may be developed more rapidly if previously developed modules can be used in them.

Code developed independently of hardware concerns increases the benefits of modularity by

allowing the programmer to focus on the code and not waste time managing memory and moving
code as other code components grow or shrink. A linker is invoked to allocate systems hardware
to the modules desired to build a system. Changes in any or all modules, when re-linked, create a
new hardware allocation, avoiding the possibility of memory resource conflicts.

Code Composer Studio: IDE

‹ Integrates: edit, code generation,

and debug

‹ Single-click access using buttons

‹ Powerful graphing/profiling tools

‹ Automated tasks using GEL scripts

‹ Built-in access to BIOS functions

‹ Support TI or 3rd party plug-ins

2-4 TMS320C28x DSP Workshop - Programming Development Environment

 Code Composer Studio

Projects
Code Composer works with a project paradigm. Essentially, within CCS you create a project for
each executable program you wish to create. Projects store all the information required to build
the executable. For example, it lists things like: the source files, the header files, the target
system’s memory-map, and program build options.

The CCS Project

Project (.pjt) files contain:

‹ Source files (by reference)

Š Source (C, assembly)
Š Libraries
Š DSP/BIOS configuration
Š Linker command files
‹ Project settings:
Š Build Options (compiler and
assembler)
Š Build configurations
Š DSP/BIOS
Š Linker

The project information is stored in a .PJT file, which is created and maintained by CCS. To
create a new project, you need to select the Project:New… menu item.

Along with the main Project menu, you can also manage open projects using the right-click
popup menu. Either of these menus allows you to Add Files… to a project. Of course, you can
also drag-n-drop files onto the project from Windows Explorer.

TMS320C28x DSP Workshop - Programming Development Environment 2-5

Code Composer Studio

Build Options
Project options direct the code generation tools (i.e. compiler, assembler, linker) to create code
according to your system’s needs. When you create a new project, CCS creates two sets of build
options – called Configurations: one called Debug, the other Release (you might think of as
Optimize).

To make it easier to choose build options, CCS provides a graphical user interface (GUI) for the
various compiler options. Here’s a sample of the Debug configuration options.

Build Options GUI - Compiler

‹ GUI has 8 pages of categories for code

generation tools
‹ Controls many aspects of the build process,
such as:
Š Optimization level
Š Target device
Š Compiler/assembly/link options

There is a one-to-one relationship between the items in the text box and the GUI check and drop-
down box selections. Once you have mastered the various options, you can probably find
yourself just typing in the options.

2-6 TMS320C28x DSP Workshop - Programming Development Environment

 Code Composer Studio

Build Options GUI - Linker

‹ GUI has 2 categories

for linking
‹ Specifies various link
options
‹ “.\Debug\” indicates
on subfolder level
below project (.pjt)
location

There are many linker options but these four handle all of the basic needs.
• -o <filename> specifies the output (executable) filename.
• -m <filename> creates a map file. This file reports the linker’s results.
• -c tells the compiler to autoinitialize your global and static variables.

• -x tells the compiler to exhaustively read the libraries. Without this option libraries are
searched only once, and therefore backwards references may not be resolved.

TMS320C28x DSP Workshop - Programming Development Environment 2-7

Code Composer Studio

Default Build Configurations

‹ For new projects, CCS automatically

creates two build configurations:
Š Debug (unoptimized)
Š Release (optimized)
‹ Use the drop-down menu to quickly
select the build configuration

‹ Add/Remove your own custom

build configurations using
Project Configurations
‹ Edit a configuration:
1. Set it active
2. Modify build options
3. Save project

To help make sense of the many compiler options, TI provides two default sets of options
(configurations) in each new project you create. The Release (optimized) configuration invokes
the optimizer with –o3 and disables source-level, symbolic debugging by omitting –g (which
disables some optimizations to enable debug).

2-8 TMS320C28x DSP Workshop - Programming Development Environment

 Creating a Linker Command File

Creating a Linker Command File

Sections
Looking at a C program, you'll notice it contains both code and different kinds of data (global,
local, etc.).

Sections
Global Vars (.ebss) Init vals (.cinit)

‹ Every C program
int x = 2; consists of different
int y = 7; parts called sections
‹ All default sections
names begin with “.”
void main(void) ‹ The compiler has
{ default sections
names for initialized
long z; and uninitialized
z = x + y; sections

Local vars (.stack) Code (.text)

In the TI code-generation tools (as with any toolset based on the COFF – Common Object File
Format), these various parts of a program are called Sections. Breaking the program code and
data into various sections provides flexibility since it allows you to place code sections in ROM
and variables in RAM. The preceding diagram illustrated five sections:
• Global Variables
• Initial Values for global variables
• Local Variables (i.e. the stack)
• Code (the actual instructions)

TMS320C28x DSP Workshop - Programming Development Environment 2-9

Creating a Linker Command File

Following is a list of the sections that are created by the compiler. Along with their description,
we provide the Section Name defined by the compiler.

Compiler Section Names

Initialized Sections
Name Description Link Location
.text code FLASH
.cinit initialized global and static variables FLASH
.econst constant data (e.g. const int k = 3;) FLASH
.switch tables for switch statements FLASH
.pinit tables for global constructors (C++) FLASH

Uninitialized Sections
Name Description Link Location
.ebss global & static variables RAM
.stack stack space low 64Kw RAM
.esysmem memory for far malloc functions RAM

Note: During development initialized sections could be linked to RAM since

the emulator can be used to load the RAM

Sections of a C program must be located in different memories in your target system. This is the
big advantage of creating the separate sections for code, constants, and variables. In this way,
they can all be linked (located) into their proper memory locations in your target embedded
system. Generally, they’re located as follows:

Program Code (.text)

Program code consists of the sequence of instructions used to manipulate data, initialize system
settings, etc. Program code must be defined upon system reset (power turn-on). Due to this basic
system constraint it is usually necessary to place program code into non-volatile memory, such as
FLASH or EPROM.

Constants (.cinit – initialized data)

Initialized data are those data memory locations defined at reset.It contains constants or initial
values for variables. Similar to program code, constant data is expected to be valid upon reset of
the system. It is often found in FLASH or EPROM (non-volatile memory).

Variables (.ebss – uninitialized data)

Uninitialized data memory locations can be changed and manipulated by the program code during
runtime execution. Unlike program code or constants, uninitialized data or variables must reside
in volatile memory, such as RAM. These memories can be modified and updated, supporting the
way variables are used in math formulas, high-level languages, etc. Each variable must be
declared with a directive to reserve memory to contain its value. By their nature, no value is
assigned, instead they are loaded at runtime by the program

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 Creating a Linker Command File

Placing Sections in Memory

Memory
Sections
0x00 0000 M0SARAM
(0x400)
.ebss
0x00 0400 M1SARAM
(0x400)
.stack

0x3E 8000 FLASH .cinit

(0x10000)

.text

Linking code is a three step process:

1. Defining the various regions of memory (on-chip SARAM vs. FLASH vs. External Memory).
2. Describing what sections go into which memory regions
3. Running the linker with “build” or “rebuild”

TMS320C28x DSP Workshop - Programming Development Environment 2 - 11

Creating a Linker Command File

Linker Command Files (.cmd)

The linker concatenates each section from all input files, allocating memory to each section based
on its length and location as specified by the MEMORY and SECTIONS commands in the linker
command file.

Linking

zz Memory
Memorydescription
description
zz How
How to
toplace
places/w
s/winto
into h/w
h/w

Link.cmd

.obj Linker .out

.map

Memory-Map Description
The MEMORY section describes the memory configuration of the target system to the linker.

The format is: Name: origin = 0x????, length = 0x????

For example, if you placed a 64K FLASH starting at memory location 0x3E8000, it would read:

MEMORY
{
FLASH: origin = 0x3E8000 , length = 0x010000
}

Each memory segment is defined using the above format. If you added M0SARAM and
M1SARAM, it would look like:

MEMORY
{
M0SARAM: origin = 0x000000 , length = 0x0400
M1SARAM: origin = 0x000400 , length = 0x0400
}

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 Creating a Linker Command File

Remember that the DSP has two memory maps: Program, and Data. Therefore, the MEMORY
description must describe each of these separately. The loader uses the following syntax to
delineate each of these:

Linker Page TI Definition

Page 0 Program
Page 1 Data

Linker Command File

MEMORY
{
PAGE 0: /* Program Space */
FLASH: org = 0x3E8000, len = 0x10000

PAGE 1: /* Data Space */

M0SARAM: org = 0x000000, len = 0x400
M1SARAM: org = 0x000400, len = 0x400
}

TMS320C28x DSP Workshop - Programming Development Environment 2 - 13

Creating a Linker Command File

Section Placement
The SECTIONS section will specify how you want the sections to be distributed through
memory. The following code is used to link the sections into the memory specified in the
previous example:

SECTIONS
{
.text:> FLASH PAGE 0
.ebss:> M0SARAM PAGE 1
.cinit:> FLASH PAGE 0
.stack:> M1SARAM PAGE 1
}

The linker will gather all the code sections from all the files being linked together. Similarly, it
will combine all ‘like’ sections.

Beginning with the first section listed, the linker will place it into the specified memory segment.

Linker Command File

MEMORY
{
PAGE 0: /* Program Space */
FLASH: org = 0x3E8000, len = 0x10000

PAGE 1: /* Data Space */

M0SARAM: org = 0x000000, len = 0x400
M1SARAM: org = 0x000400, len = 0x400
}
SECTIONS
{
.text:> FLASH PAGE 0
.ebss:> M0SARAM PAGE 1
.cinit:> FLASH PAGE 0
.stack:> M1SARAM PAGE 1
}

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 Exercise 2a

Exercise 2a
Looking at the following block diagram, and create a linker command file.

Exercise 2a

0x00 0000 0x00 0400

M0SARAM M1SARAM
(0x400) (0x400)

0x00 8000 0x00 9000

L0SARAM L1SARAM
(0x1000) (0x1000)

0x3E 8000 0x00 A000

FLASH H0SARAM
(0x10000) (0x2000)

F2808

Create the linker command file for the given memory

map by filling in the blanks on the following slide

Fill in the blanks:

Exercise 2a - Command File

MEMORY
{
PAGE__: /* Program Space */
_____: org = ____ ___, len = ___ ___
______: /* Data Space */
_______: org = ___ ____, len = _____
_______: org = ____ ___, len = _____
_______: org = ___ ____, len = __ ___
_______: org = ___ ____, len = _ ____
_______: org = ___ ____, len = _ ____
}
SECTIONS
{
.text: > FLASH PAGE 0
.ebss: > M0SARAM PAGE 1
.cinit: > FLASH PAGE 0
.stack: > M1SARAM PAGE 1
}

TMS320C28x DSP Workshop - Programming Development Environment 2 - 15

Exercise 2a

Summary: Linker Command File

The linker command file (.cmd) contains the inputs — commands — for the linker. This
information is summarized below:

Linker Command File Summary

‹ Memory Map Description

Š Name
Š Location
Š Size
‹ Sections Description
Š Directs software sections into named
memory regions
Š Allows per-file discrimination
Š Allows separate load/run locations

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 Lab 2a: Linker Command File

Lab 2a: Linker Command File

¾ Objective

Create a linker command file and link the C program file (LAB2.C) into the system described
below.

Lab 2a: Linker Command File

M0SARAM 0x00 0000 L0SARAM 0x00 8000
M0SARAM L0SARAM
Memory
(0x400)
(0x400) (0x1000)
(0x1000)
M1SARAM 0x00 0400 L1SARAM 0x00 9000
on-chip
on-chip M1SARAM L1SARAM
memory
memory (0x400)
(0x400) (0x1000)
(0x1000)

H0SARAM 0x00 A000

H0SARAM
F2808 (0x2000)
(0x2000)

System Description:
• TMS320F2808
• All internal RAM blocks allocated
Placement of Sections:
• .text into RAM Block H0SARAM on PAGE 0 (code space)
• .cinit into RAM Block H0SARAM on PAGE 0 (code space)
• .ebss into RAM Block M0SARAM on PAGE 1 (data space)
• .stack into RAM Block M1SARAM on PAGE 1 (data space)

System Description
• TMS320F2808
• All internal RAM blocks allocated

Placement of Sections:
• .text into RAM Block H0SARAM on PAGE 0 (code space)
• .cinit into RAM Block H0SARAM on PAGE 0 (code space)
• .ebss into RAM Block M0SARAM on PAGE 1 (data space)
• .stack into RAM Block M1SARAM on PAGE 1 (data space)

¾ Procedure

Create a New Project

1. Double click on the Code Composer Studio icon on the desktop. Maximize Code
Composer Studio to fill your screen. Code Composer Studio has a Connect/Disconnect
feature which allows the target to be dynamically connected and disconnected. This will
reset the JTAG link and also enable “hot swapping” a target board. Connect to the target.

TMS320C28x DSP Workshop - Programming Development Environment 2 - 17

Lab 2a: Linker Command File

Click: Debug Æ Connect

The menu bar (at the top) lists File ... Help. Note the horizontal tool bar below the menu
bar and the vertical tool bar on the left-hand side. The window on the left is the project
window and the large right hand window is your workspace.

2. A project is all the files you will need to develop an executable output file (.out) which
can be run on the DSP hardware. Let’s create a new project for this lab. On the menu bar
click:
Project Æ New
type Lab2 in the project name field and make sure the save in location is:
C:\C28x\Labs\Lab2. This will create a .pjt file which will invoke all the necessary
tools (compiler, assembler, linker) to build your project. It will also create a debug
folder that will hold immediate output files.

3. Add the C file to the new project. Click:

Project Æ Add Files to Project…
and make sure you’re looking in C:\C28x\Labs\Lab2. Change the “files of type” to
view C source files (*.c) and select Lab2.c and click OPEN. This will add the file
Lab2.c to your newly created project.
4. Add Lab2a.cmd to the project using the same procedure. This file will be edited
during the lab exercise.
5. Next, add the compiler run-time support library to the project
(C:\CCStudio_v3.1\c2000\cgtools\lib\rts2800_ml.lib).

6. In the project window on the left click the plus sign (+) to the left of Project. Now,
click on the plus sign next to Lab2.pjt. Notice that the Lab2a.cmd file is listed.
Click on Source to see the current source file list (i.e. Lab2.c).

Project Build Options

7. There are numerous build options in the project. The default option settings are sufficient
for getting started. We will inspect a couple of the default linker options at this time.

Click: Project Æ Build Options…

8. Select the Linker tab. Notice that .out and .map files are being created. The .out file is
the executable code that will be loaded into the DSP. The .map file will contain a linker
report showing memory useage and section addresses in memory.

9. Set the Stack Size to 0x200. Select OK and then close the Build Options window.

Edit the Linker Command File - Lab2a.cmd

10. To open and edit Lab2a.cmd, double click on the filename in the project window.

11. Edit the Memory{} declaration by describing the system memory shown on the “Lab2a:
Linker Command File” slide.

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 Lab 2a: Linker Command File

12. In the Sections{} area, notice that a section called .reset has already been allocated.
The .reset section is part of the rts2800_ml.lib, and is not needed. By putting the TYPE =
DSECT modifier after its allocation, the linker will ignore this section and not allocate it.
13. Place the sections defined on the slide into the appropriate memories via the
Sections{} area. Save your work.

Build and Load the Project

14. The top four buttons on the horizontal toolbar control code generation. Hover your
mouse over each button as you read the following descriptions:
Button Name Description
1 Compile File Compile, assemble the current open file
2 Incremental Build Compile, assemble only changed files, then link
3 Rebuild All Compile, assemble all files, then link
4 Stop Build Stop code generation

15. Code Composer Studio can automatically load the output file after a successful build. On
the menu bar click: Option Æ Customize… and select the “Program/Project
Load” tab, check “Load Program After Build”.
Also, Code Composer Studio can automatically connect to the target when started. Select
the “Debug Properties” tab, check “Connect to the target when a
control window is opened”, then click OK.
16. Click the “Build” button and watch the tools run in the build window. Check for
errors (we have deliberately put an error in Lab2.c). When you get an error, scroll the
build window at the bottom of the Code Composer Studio screen until you see the error
message (in red), and simply double-click the error message. The editor will
automatically open the source file containing the error, and position the mouse cursor at
the correct code line.
17. Fix the error by adding a semicolon at the end of the "z = x + y" statement. For
future knowlege, realize that a single code error can sometimes generate multiple error
messages at build time. This was not the case here.
18. Rebuild the project (there should be no errors this time). The output file should
automatically load. The Program Counter should be pointing to _c_int00 in the
Disassembly Window.

19. Under Debug on the menu bar click “Go Main”. This will run through the C-
environment initialization routine in the rts2800_ml.lib and stop at main() in
Lab2.c.

Debug Enviroment Windows

It is standard debug practice to watch local and global variables while debugging code. There
are various methods for doing this in Code Composer Studio. We will examine two of them
here: memory windows, and watch windows.

TMS320C28x DSP Workshop - Programming Development Environment 2 - 19

Lab 2a: Linker Command File

20. Open a memory window to view the global variable “z”.

Click: View Æ Memory on the menu bar.

Type “&z” into the address field. Note that you must use the ampersand (meaning
"address of") when using a symbol in a memory window address box. Also note that
Code Composer Studio is case sensitive.

Set the properties format to “Hex – TI style.” This will give you more viewable data in
the window.

Click OK to close the window property selection screen. The memory window will now
open. You can change the contents of any address in the memory window by double-
clicking on its value. This is useful during debug.

21. Open the watch window to view the local variables x and y.

Click: View Æ Watch Window on the menu bar.

Click the “Watch Locals” tab and notice that the local variables x and y are already
present. The watch window will always contain the local variables for the code function
currently being executed.

(Note that local variables actually live on the stack. You can also view local variables in
a memory window by setting the address to “SP” after the code function has been
entered).

22. We can also add global variables to the watch window if desired. Let's add the global
variable “z”.

Click the “Watch 1" tab at the bottom of the watch window. In the empty box in the
"Name" column, type “z”. Note that you do not use an ampersand here. The watch
window knows you are specifying a symbol.

Check that the watch window and memory window both report the same value for “z”.
Trying changing the value in one window, and notice that the value also changes in the
other window.

Single-stepping the Code

23. Single-step through main() by using the <F11> key (or you can use the Single
Step button on the vertical toolbar). Check to see if the program is working as
expected. What is the value for “z” when you get to the end of the program?

End of Exercise

2 - 20 TMS320C28x DSP Workshop - Programming Development Environment

 DSP/BIOS Configuration Tool

DSP/BIOS Configuration Tool

The DSP/BIOS Configuration Tool (often called Config Tool or GUI Tool or GUI) creates and
modifies a system file called the Configuration DataBase (.cdb). If we talk about using .cdb files,
we’re also talking about using the Config Tool.

DSP/BIOS Configuration Tool (file .cdb)

‹ MEM handles system

memory configuration
(builds .cmd file)
‹ Configures BIOS
scheduling, RTA and
other BIOS functions
‹ Automatically
handles: run-time
support libraries,
interrupt vectors,
system reset, etc.

The GUI (graphical user interface) simplifies system design by:

• Automatically including the appropriate runtime support libraries
• Automatically handles interrupt vectors and system reset
• Handles system memory configuration (builds .cmd file)
• When a .cdb file is saved, the Config Tool generates 5 additional files:
Filename.cdb Configuration Database
Filenamecfg_c.c C code created by Config Tool
Filenamecfg.s28 ASM code created by Config Tool
Filenamecfg.cmd Linker command file
Filenamecfg.h header file for *cfg_c.c
Filenamecfg.h28 header file for *cfg.s28

When you add a .cdb file to your project, CCS automatically adds the C and assembly
(.s28) files and the linker command file (.cmd) to the project under the Generated Files
folder.

TMS320C28x DSP Workshop - Programming Development Environment 2 - 21

DSP/BIOS Configuration Tool

1. Creating a New Memory Region (Using MEM)

First, to create a specific memory area, open up the .cdb file, right-click on the Memory Section
Manager and select “Insert MEM”. Give this area a unique name and then specify its base and
length. Once created, you can place sections into it (shown in the next step).

Memory Section Manager

‹ Mem manager allows

you to create
memory area and
place sections
‹ To create a new
memory area:
Š Right-click on MEM
and select Insert
memory
Š Fill in base, length,
space

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 DSP/BIOS Configuration Tool

2. Placing Sections – MEM Manager Properties

The configuration tool makes it easy to place sections. The predefined compiler sections that
were described earlier each have their own drop-down menu to select one of the memory regions
you defined (in step 1).

Memory Section Manager Properties

‹ To place a section
into a memory area:
Š Right-click on MEM
and select
Properties
Š Select the
appropriate tab (e.g.
Compiler)
Š Select the memory
for each section

TMS320C28x DSP Workshop - Programming Development Environment 2 - 23

DSP/BIOS Configuration Tool

3. Running the Linker

Creating the Linker Command File (via .cdb)

When you have finished creating memory regions and allocating sections into these memory
areas (i.e. when you save the .cdb file), the CCS configuration tool creates five files. One of the
files is BIOS’s cfg.cmd file — a linker command file.

Files Created by Config Tool

‹ Config tool generates five
different files
‹ Notice, one of them is the
linker command file
‹ CMD file is generated from
your MEM settings

MEMORY{
MEMORY{
FLASH:
FLASH: org org == 0x3E8000,
0x3E8000, len
len == 0x10000
0x10000 *cfg_c.c
H0SARAM:
H0SARAM: org = 0x00A000, len == 0x2000
org = 0x00A000, len 0x2000
…… }} *cfg.s28
SECTIONS{
SECTIONS{ *cfg.cmd
.text:
.text: >> FLASH
FLASH
.bss:
.bss: >> M0SARAM
M0SARAM *cfg.h
…… }}
*cfg.h28

This file contains two main parts, MEMORY and SECTIONS. (Though, if you open and
examine it, it’s not quite as nicely laid out as shown above.)

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 DSP/BIOS Configuration Tool

Running the Linker

The linker’s main purpose is to link together various object files. It combines like-named input
sections from the various object files and places each new output section at specific locations in
memory. In the process, it resolves (provides actual addresses for) all of the symbols described in
your code.

Config Tool Linker Command File

“Build”
app.cdb

appcfg.cmd Linker
Linker

.obj files
.map
libraries
(.lib) myApp.out

‹ Do not modify appcfg.cmd – your changes will

be overwritten during “Build” (or “Rebuild”)

The linker can create two outputs, the executable (.out) file and a report which describes the
results of linking (.map).

Note: If the graphic above wasn’t clear enough, the linker gets run automatically when you
BUILD or REBUILD your project.

TMS320C28x DSP Workshop - Programming Development Environment 2 - 25

Lab 2b: DSP/BIOS Configuration Tool

Lab 2b: DSP/BIOS Configuration Tool

¾ Objective

Use Code Composer Studio and DSP/BIOS configuration tool to create a configuration database
files (*.cdb). The generated linker command file Labcfg.cmd will be then be used with Lab2.c to
verify its operation. The memory and sections of a “user” linker command file will be deleted,
however, the “user” linker command file will be needed and modified in future labs.

Lab 2b: Configuration Tool

M0SARAM 0x00 0000 L0SARAM 0x00 8000
M0SARAM L0SARAM
Memory
(0x400)
(0x400) (0x1000)
(0x1000)
M1SARAM 0x00 0400 L1SARAM 0x00 9000
on-chip
on-chip M1SARAM L1SARAM
memory
memory (0x400)
(0x400) (0x1000)
(0x1000)

H0SARAM 0x00 A000

H0SARAM
F2808 (0x2000)
(0x2000)

System Description:
• TMS320F2808
• All internal RAM blocks allocated
Placement of Sections:
• .text into RAM Block H0SARAM in code space (PAGE 0)
• .cinit into RAM Block H0SARAM in code space (PAGE 0)
• .ebss into RAM Block M0SARAM in data space (PAGE 1)
• .stack into RAM Block M1SARAM in data space (PAGE 1)

System Description
• TMS320F2808
• All internal RAM blocks allocated

Placement of Sections:
• .text into RAM Block H0SARAM in code space (PAGE 0)
• .cinit into RAM Block H0SARAM in code space (PAGE 0)
• .ebss into RAM Block M0SARAM in data space (PAGE 1)
• .stack into RAM Block M1SARAM in data space (PAGE 1)

¾ Procedure

Project Lab2.pjt
1. If Code Composer Studio is not running from the previous lab exercise, double click on
the CCS icon on the desktop. Maximize CCS to fill your screen. Then select Lab2.pjt

2 - 26 TMS320C28x DSP Workshop - Programming Development Environment

 Lab 2b: DSP/BIOS Configuration Tool

from the Project Æ Recent Project Files list. This will put you at the
proper starting point for this lab exercise.

2. If needed, verify that the project is open in CCS by left clicking the plus sign (+) to the
left of Project. Then, click on the plus sign next to Lab2.pjt ,as well as the other
plus signs to verify all the previous files have been included.

Remove “rts2800_ml.lib” and “Lab2a.cmd” from the Project

3. Highlight the rts2800_ml.lib in the project window and right click, then select
“Remove from Project”. The DSP/BIOS Config Tool supplies its own rts library.

4. Remove Lab2a.cmd using the same procedure. We will be using the DSP/BIOS
configuration tool to create a linker command file.

Using the DSP/BIOS Configuration Tool

5. The configuration database files (*.cdb), created by the Config Tool, controls a wide
range of CCS capabilities. In this lab exercise, the CDB file will be used to automatically
create and perform memory management. Create a new CDB file for this lab. On the
menu bar click:
File Æ New Æ DSP/BIOS Configuration…
A dialog box appears. The CDB files shown in the aforementioned dialog box are called
“seed” CDB files. CDB files are used to configure many objects specific to the
processor. Select the c28xx.cdb template and click OK. A configuration window will
open.

6. Save the configuration file by selecting:

File Æ Save As…
and name it Lab.cdb in C:\C28x\Labs\Lab2 then click Save. Close the
configuration window and select YES to save changes to Lab.cdb.

7. Add the configuration file to the project. Click:

Project Æ Add Files to Project…

Make sure you’re looking in C:\C28x\Labs\Lab2. Change the “files of type” to

view All Files (*.*) and select Lab.cdb. Click OPEN to add the file to the project.

8. In the project window left click the plus sign (+) to the left of DSP/BIOS Config.
Notice that the Lab.cdb file is listed. Then left click the plus sign (+) to the left of
Generated Files. The generated linker command file, Labcfg.cmd, is listed and
has been automatically added with the configuration file.

Create New Memory Sections Using the CDB File

9. Open the Lab.cdb file by double clicking on Lab.cdb. In the configuration window,
left click the plus sign next to System and the plus sign next to MEM.

TMS320C28x DSP Workshop - Programming Development Environment 2 - 27

Lab 2b: DSP/BIOS Configuration Tool

10. By default, the Memory Section Manager has combined the memory space for
L0SARAM and L1SARAM into a single memory block called L0SARAM. It has also
combined M0SARAM and M1SARAM into a single memory block called M0SARAM.
We want to split these memory sections as shown in the slide for this lab exercise.
Right click on MEM – Memory Section Manager and select Insert MEM.
Rename the newly added memory section to L1SARAM. Create a second new memory
section, and rename it to M1SARAM.
11. Modify the length and base addresses of each of the memory sections L0SARAM,
L1SARAM, M0SARAM, and M1SARAM to correspond to the memory mapping shown
in the figure at the beginning of this lab. To modify the length and base address of a
memory section, right click on the memory in configuration tool, and select “Properties.”
While modifying the length and base address of each section, make sure the
“create a heap in memory” box is checked ONLY for L0SARAM. Uncheck
this box in the other three memory sections.
12. Check the memory section properties for H0SARAM and make sure that it corresponds
to the memory mapping shown in the figure at the beginning of this lab. Modify, if
needed.
13. Check the memory section properties for FLASH and make sure that it has the following
settings – base: 0x3E8000, len: 0xFFF6, space: code. Modify, if needed.

14. Right click on MEM – Memory Section Manager and select Properties.
Select the Compiler Sections tab and place the .text, .cinit, and .ebss sections
defined on the lab introduction slide into the appropriate memories via the pull-down
boxes. Similarly, place the .stack section into memory using the BIOS Data tab.
Click OK to save your work.

Set the Stack Size in the CDB File

15. Recall in the previous lab exercise that the stack size was set using the CCS project Build
Options. When using the DSP/BIOS configuration tool, the stack size is instead specified
in the CDB file. First we need to remove the stack size setting from the project Build
Options.

16. Click: Project Æ Build Options… and select the Linker tab. Delete the entry
for setting the Stack Size to 0x200. Select OK to close the Build Options window.

17. Right click on MEM – Memory Section Manager and select Properties.
Select the General tab. Notice that the Stack Size has been set to 0x200 by default, so
there is no need to modify this. Click OK to close the window. Close the configuration
window and select YES to save changes to Lab.cdb.

Build and Load the Project

18. Click the “Build” button and watch the tools run in the build window. The output file
should automatically load. The Program Counter should be pointing to _c_int00 in
the Disassembly Window.

2 - 28 TMS320C28x DSP Workshop - Programming Development Environment

 Lab 2b: DSP/BIOS Configuration Tool

19. Under Debug on the menu bar click “Go Main”. This will run through the DSP/BIOS
C-environment initialization routine and stop at main() in Lab2.c.

Run the Code

20. We will verify the operation of the code using the same procedure used in Lab2a. Open
the watch window and add the global variable z.

21. Next, single-step the routine through to the end. Check to see if the program is working
as expected. You should get the same value for “z” as in Lab2a.

End of Exercise

TMS320C28x DSP Workshop - Programming Development Environment 2 - 29

Solutions

Solutions
Exercise 2a - Solution
MEMORY
{
PAGE 0: /* Program Space */
FLASH: org = 0x3E8000, len = 0x10000
PAGE 1: /* Data Space */
M0SARAM: org = 0x000000, len = 0x400
M1SARAM: org = 0x000400, len = 0x400
L0SARAM: org = 0x008000, len = 0x1000
L1SARAM: org = 0x009000, len = 0x1000
H0SARAM: org = 0x00A000, len = 0x2000
}
SECTIONS
{
.text: > FLASH PAGE 0
.ebss: > M0SARAM PAGE 1
.cinit: > FLASH PAGE 0
.stack: > M1SARAM PAGE 1
}

Lab 2a: Solution - lab2.cmd

MEMORY
{
PAGE 0: /* Program Space */
H0SARAM: org = 0x00A000, len = 0x2000
PAGE 1: /* Data Space */
M0SARAM: org = 0x000000, len = 0x400
M1SARAM: org = 0x000400, len = 0x400
L0SARAM: org = 0x008000, len = 0x1000
L1SARAM: org = 0x009000, len = 0x1000
}

SECTIONS
{
.text: > H0SARAM PAGE 0
.ebss: > M0SARAM PAGE 1
.cinit: > H0SARAM PAGE 0
.stack: > M1SARAM PAGE 1
.reset: > H0SARAM PAGE 0, TYPE = DSECT
}

2 - 30 TMS320C28x DSP Workshop - Programming Development Environment

 Peripherial Registers Header Files

Introduction
The purpose of the F280x C-code header files is to simplify the programming of the many
peripherals on the C28x device. Typically, to program a peripheral the programmer needs to
write the appropriate values to the different fields within a control register. In it’s simplest form,
the process consists of writing a hex value (or masking a bit field) to the correct address in
memory. But, since this can be a burdensome and repetitive task, the C-code header files were
created to make this a less complicated task.

The F280x C-code header files are part of a library consisting of C functions, macros, peripheral
structures, and variable definitions. Together, this set of files is known as the ‘header files.’

Registers and the bit-fields are represented by structures. C functions and macros are used to
initialize or modify the structures (registers).

In this module, you will learn how to use the header files and C programs to facilitate
programming the peripherals.

Learning Objectives
Learning Objectives

‹ Understand the usage of the F280x

C-Code Header Files
‹ Be able to program peripheral
registers
‹ Understand how peripherals are
mapped with linker command file

TMS320C28x DSP Workshop - Peripheral Registers Header Files 3-1

Module Topics

Module Topics
Peripherial Registers Header Files .......................................................................................................... 3-1

Module Topics......................................................................................................................................... 3-2

Traditional and Structure Approach to C Coding .................................................................................. 3-3
Naming Conventions............................................................................................................................... 3-6
Example of Peripheral Structure .h file .................................................................................................. 3-7
Mapping Structures to Memory .............................................................................................................. 3-8
Linker Command File......................................................................................................................... 3-8
F280x C-Code Header Files ................................................................................................................... 3-9
.h Definition Files ..............................................................................................................................3-10
Global Variable Definition File .........................................................................................................3-11
Peripheral Specific Routines..................................................................................................................3-12
Summary ................................................................................................................................................3-13

3-2 TMS320C28x DSP Workshop - Peripheral Registers Header Files

 Traditional and Structure Approach to C Coding

Traditional and Structure Approach to C Coding

Traditional Approach to C Coding
#define ADCTRL1 (volatile unsigned int *)0x00007100
#define ADCTRL2 (volatile unsigned int *)0x00007101
...
void main(void)
{
*ADCTRL1 = 0x1234; //write entire register
*ADCTRL2 |= 0x4000; //reset sequencer #1
}

Advantages - Simple, fast and easy to type

- Variable names exactly match register names (easy
to remember)
Disadvantages - Requires individual masks to be generated to
manipulate individual bits
- Cannot easily display bit fields in Watch window
- Will generate less efficient code in many cases

Structure Approach to C Coding

void main(void)
{
AdcRegs.ADCTRL1.all = 0x1234; //write entire register
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1; //reset sequencer #1
}

Advantages - Easy to manipulate individual bits.

- Watch window is amazing! (next slide)
- Generates most efficient code (on C28x)

Disadvantages - Can be difficult to remember the structure names

(Editor Auto Complete feature to the rescue!)
- More to type (again, Editor Auto Complete feature
to the rescue)

TMS320C28x DSP Workshop - Peripheral Registers Header Files 3-3

Traditional and Structure Approach to C Coding

The CCS Watch Window using #define

The CCS Watch Window using Structures

3-4 TMS320C28x DSP Workshop - Peripheral Registers Header Files

 Traditional and Structure Approach to C Coding

Is the Structure Approach Efficient?

The structure approach enables efficient compiler use of
DP addressing mode and C28x Atomic operations

C Source Code Generated Assembly Code

// Stop CPU Timer0 MOVW DP, #0030
CpuTimer0Regs.TCR.bit.TSS = 1; OR @4, #0x0010

// Load new 32-bit period value MOVL XAR4, #0x010000

CpuTimer0Regs.PRD.all = 0x00010000; MOVL @2, XAR4

// Start CPU Timer0 AND @4, #0xffef

CpuTimer0Regs.TCR.bit.TSS = 0;

- Easy to read the code w/o comments

5 Words, 5 cycles
- Bit mask built-in to structure

(This example could not have been coded any more efficiently with hand assembly)

Compare with the #define Approach

The #define approach relies heavily on less-efficient
pointers for random memory access, and often does not
take advantage of C28x atomic operations

C Source Code Generated Assembly Code

// Stop CPU Timer0 MOV AL,*(0:0x0c04)
*TIMER0TCR |= 0x0010; ORB AL, #0x10
MOV *(0:0x0c04), AL

// Load new 32-bit period value MOVL XAR4, #3078

*TIMER0TPR32 = 0x00010000; MOVL XAR5, #65536
MOVL *+XAR4[0], XAR5
// Start CPU Timer0
*TIMER0TCR &= 0xFFEF; MOV AL, *(0:0x0c04)
AND AL, #0xffef
MOV *(0:0x0c04), AL

- Hard to read the code w/o comments 9 Words, 9 cycles

- User had to determine the bit mask

TMS320C28x DSP Workshop - Peripheral Registers Header Files 3-5

Naming Conventions

Naming Conventions
The header files use a familiar set of naming conventions. They are consistent with the Code
Composer Studio configuration tool, and generated file naming conventions

Structure Naming Conventions

‹ The DSP280x header files define:
Š All of the peripheral structures
Š All of the register names
Š All of the bit field names
Š All of the register addresses
PeripheralName.RegisterName.all // Access full 16 or 32-bit register
PeripheralName.RegisterName.half.LSW // Access low 16-bits of 32-bit register
PeripheralName.RegisterName.half.MSW // Access high 16-bits of 32-bit register
PeripheralName.RegisterName.bit.FieldName // Access specified bit fields of register
Notes: [1] “PeripheralName” are assigned by TI and found in the DSP280x header files.
They are a combination of capital and small letters (i.e. CpuTimer0Regs).
[2] “RegisterName” are the same names as used in the data sheet.
They are always in capital letters (i.e. TCR, TIM, TPR,..).
[3] “FieldName” are the same names as used in the data sheet.
They are always in capital letters (i.e. POL, TOG, TSS,..).

Editor Auto Complete to the Rescue!

3-6 TMS320C28x DSP Workshop - Peripheral Registers Header Files

 Example of Peripheral Structure .h file

Example of Peripheral Structure .h file

Example of Peripheral Structure .h file

Example Adc.h
/* ADC Individual Register Bit Definitions */
struct ADCTRL1_BITS { // bits description
Uint16 rsvd1:4; // 3:0 reserved
Example Adc.c or main.c Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode
#include “DSP280x_Device.h” Uint16 SEQ_OVRD:1 // 5 Sequencer override
Uint16 CONT_RUN:1; // 6 Continuous run
Void InitAdc(void) Uint16 CPS:1; // 7 ADC core clock prescaler
{ Uint16 ACQ_PS:4; // 11:8 Acquisition window size
/* Reset the ADC module */ Uint16 SUSMOD:2; // 13:12 Emulation suspend mode
AdcRegs.ADCTRL1.bit.RESET = 1; Uint16 RESET:1; // 14 ADC reset
Uint16 rsvd2:1; // 15 reserved
/* configure the ADC register */ };
AdcRegs.ADCTRL1.all = 0x0710;
}; /* Allow access to the bit fields or entire register */
union ADCTRL1_REG {
Uint16 all;
struct ADCTRL1_BITS bit;
};

// ADC External References & Function Declarations:

extern volatile struct ADC_REGS AdcRegs;

TMS320C28x DSP Workshop - Peripheral Registers Header Files 3-7

Mapping Structures to Memory

Mapping Structures to Memory

The data structures describe the register set in detail. And, each instance of the data type (i.e.,
register set) is unique. Each structure is associated with an address in memory. This is done by
(1) creating a new section name via a DATA_SECTION pragma, and (2) linking the new section
name to a specific memory in the linker command file.

Example Mapping Structure to Memory

‹ DATA_SECTION pragma used to assign a unique linker section
name to the peripheral structure
DSP280x_GlobalVariableDefs.C
#pragma DATA_SECTION(AdcRegs,“AdcRegsFile");

‹ Linker command file maps the unique peripheral section

name to the physical memory address
DSP280x_Headers_BIOS.CMD
MEMORY
{
PAGE1:
...
ADC: origin=0x007100, length=0x000020
...
}

SECTIONS
{
...
AdcRegsFile :> ADC PAGE = 1
...
}

Linker Command File

When using the header files, the user adds the MEMORY regions that correspond to the
CODE_SECTION and DATA_SECTION pragmas found in the .h and global-definitons.c file.

The user can modify their own linker command file, or use the pre-configured linker command
files such as EzDSP_RAM_lnk.cmd or F2808.cmd. These files have the peripheral memory
regions defined and tied to the individual peripheral.

3-8 TMS320C28x DSP Workshop - Peripheral Registers Header Files

 F280x C-Code Header Files

F280x C-Code Header Files

The C-code header files consists of .h, c source files, linker command files, and other useful
example programs, documentations and add-ins for Code Composer Studio.

DSP280x Header File Package

(http://www.ti.com/c2000, literature # SPRC191)

‹ Simplifies program of peripherals and

other functions
‹ Takes care of register definitions and
addresses
‹ Header file package consists of:
Š \DSP280x_headers\include Æ .h files
Š \DSP280x_common\src Æ .c source files
Š \DSP280x_headers\cmd Æ linker command files
Š \DSP280x_headers\gel Æ .gel files for CCS
Š \DSP280x_examples Æ example programs
Š \doc Æ documentation
‹ TI has done all of the work for you!

A peripheral is programmed by writing values to a set of registers. Sometimes, individual fields

are written to as bits, or as bytes, or as entire words. Unions are used to overlap memory
(register) so the contents can be accessed in different ways. The header files group all the
registers belonging to a specific peripheral.

A DSP280x_Peripheral.gel GEL file can provide a pull down menu to load peripheral data
structures into a watch window. Code Composer Studio can load a GEL file automatically. To
include fuctions to the standard F2808.gel that is part of Code Composer Studio, add:

GEL_LoadGel(“base_path/gel/DSP280x_Peripheral.gel”)

TMS320C28x DSP Workshop - Peripheral Registers Header Files 3-9

F280x C-Code Header Files

.h Definition Files
The DSP280x_Device.h header file is the main include file. By including this file in the .c source
code, all of the peripheral specific .h header files are automatically included. Of course, each
specific .h header file can included individually in an application that do not use all the header
files, or you can comment out the ones you do not need. (Also includes typedef statements).

.h Definition Files
‹ Files found in the
\DSP280x_headers\include directory
‹ Define structures and bit fields in
peripheral and system registers
‹ DSP280x_Device.h – main include file
will include all other .h files
Š #include “DSP280x_Device.h”

DSP280x_Device.h DSP280x_DevEmu.h DSP280x_SysCtrl.h

DSP280x_PieCtrl.h DSP280x_Adc.h DSP280x_CpuTimers.h
DSP280x_ECan.h DSP280x_ECap.h DSP280x_EPwm.h
DSP280x_EQep.h DSP280x_Gpio.h DSP280x_I2c.h
DSP280x_Sci.h DSP280x_Spi.h DSP280x_XIntrupt.h
DSP280x_PieVect.h DSP280x_DefaultIsr.h

3 - 10 TMS320C28x DSP Workshop - Peripheral Registers Header Files

 F280x C-Code Header Files

Global Variable Definition File

With DSP280x_GlobalVariableDefs.c included in the project all the needed variable definitions
are globally defined.

Global Variable Definition File

‹ DSP280x_GlobalVariableDefs.C
‹ Defines all variables to use .h files
‹ DATA_SECTION pragma used to
define data section for each
peripheral structure
‹ Linker will link each structure to the
physical address of the peripheral in
memory
‹ Add DSP280x_GlobalVariableDefs.C
to the Code Composer Studio project

TMS320C28x DSP Workshop - Peripheral Registers Header Files 3 - 11

Peripheral Specific Routines

Peripheral Specific Routines

Peripheral Specific C functions are used to initialize the peripherals. They are used by adding the
appropriate .c file to the project.

Peripheral Specific Routines

‹ Contains peripheral specific

initialization routines and other
support functions

DSP280x_SysCtrl.c DSP280x_Gpio.c
DSP280x_PieCtrl.c DSP280x_I2c.c
DSP280x_Adc.c DSP280x_Sci.c
DSP280x_CpuTimers.c DSP280x_Spi.c
DSP280x_ECan.c DSP280x_ECap.c
DSP280x_EPwm.c DSP280x_EQep.c
DSP280x_PieVect.c DSP280x_DefaultIsr.c

Workshop lab files based on above files with modifications

Other files included in the packet:

Other Files in Packet

‹ Linker.cmd files
Š DSP280x_Headers_BIOS.cmd
DSP280x_Headers_nonBIOS.cmd
Š Contains memory allocation for all
peripheral structure definitions
included in C-code header file package
‹ DSP280x_CodeStartBranch.asm
Š Used to redirect code execution when
booting
.ref _c_int00

.sect "codestart"

LB _c_int00 ;branch to start of boot.asm in RTS library

Workshop lab files based on above files with modifications

3 - 12 TMS320C28x DSP Workshop - Peripheral Registers Header Files

 Summary

Summary
Peripheral Register Header Files
Summary

‹ Easier code development

‹ Easy to use
‹ Generates most efficient Code
‹ Increases Effectiveness of CCS
Watch Window
‹ TI has already done all the work!
Š Download literature # SPRC191 from www.ti.com/c2000

TMS320C28x DSP Workshop - Peripheral Registers Header Files 3 - 13

Summary

3 - 14 TMS320C28x DSP Workshop - Peripheral Registers Header Files

 Reset and Interrupts

Introduction
This module describes the interrupt process and explains how the Peripheral Interrupt Expansion
(PIE) works.

Learning Objectives
Learning Objectives

‹ Describe the C28x reset process

and post-reset device state
‹ List the event sequence during an
interrupt
‹ Describe the C28x interrupt
structure

TMS320C28x DSP Workshop - Reset and Interrupts 4-1

Module Topics

Module Topics
Reset and Interrupts ................................................................................................................................. 4-1

Module Topics......................................................................................................................................... 4-2

Reset........................................................................................................................................................ 4-3
Reset - Bootloader .............................................................................................................................. 4-4
Interrupts ................................................................................................................................................ 4-6
Interrupt Processing............................................................................................................................ 4-6
Peripheral Interrupt Expansion (PIE) ................................................................................................. 4-8
PIE Interrupt Vector Table ................................................................................................................. 4-9
Interrupt Response and Latency ........................................................................................................4-12

4-2 TMS320C28x DSP Workshop - Reset and Interrupts

 Reset

Reset
Reset Sources

C28x Core
Watchdog Timer
RS
RS pin active

To RS pin

Register Bits Initialized at Reset

Register bits defined by reset

PC 0x3F FFC0 PC loaded with reset vector
ACC 0x0000 0000 Accumulator cleared
XAR0 - XAR7 0x0000 0000 Auxiliary Registers
DP 0x0000 Data Page pointer points to page 0
P 0x0000 0000 P register cleared
XT 0x0000 0000 XT register cleared
SP 0x0400 Stack Pointer to address 0400
RPC 0x00 0000 Return Program Counter cleared
IFR 0x0000 no pending interrupts
IER 0x0000 maskable interrupts disabled
DBGIER 0x0000 debug interrupts disabled

TMS320C28x DSP Workshop - Reset and Interrupts 4-3

Reset

Control Bits Initialized at Reset

Status Register 0 (ST0)
SXM = 0 Sign extension off
OVM = 0 Overflow mode off N=0 negative flag
TC = 0 test/control flag V=0 overflow bit
C=0 carry bit PM = 000 set to left-shift-by-1
Z=0 zero flag OVC = 00 0000 overflow counter
Status Register 1 (ST1)
INTM = 1 Disable all maskable interrupts - global
DBGM = 1 Emulation access/events disabled
PAGE0 = 0 Stack addressing mode enabled/Direct addressing disabled
VMAP = 1 Interrupt vectors mapped to PM 0x3F FFC0 – 0x3F FFFF
SPA = 0 stack pointer even address alignment status bit
LOOP = 0 Loop instruction status bit
EALLOW = 0 emulation access enable bit
IDLESTAT = 0 Idle instruction status bit
AMODE = 0 C27x/C28x addressing mode
OBJMODE = 0 C27x object mode
M0M1MAP = 1 mapping mode bit
XF = 0 XF status bit
ARP = 0 ARP points to AR0

Reset - Bootloader
Reset – Bootloader

Reset
OBJMODE=0 AMODE=0
ENPIE=0 VMAP=1

Bootloader sets
OBJMODE = 1
AMODE = 0
Reset vector fetched
from boot ROM Boot determined by
state of GPIO pins
0x3F FFC0

Execution Bootloading
Entry Point Routines
FLASH SCI-A
M0 SARAM SPI-A
OTP I2C
eCAN-A
Parallel load

4-4 TMS320C28x DSP Workshop - Reset and Interrupts

 Reset

Bootloader Options

GPIO pins
18 29 34
1 1 1 jump to FLASH address 0x3F 7FF6
0 1 0 jump to M0 SARAM address 0x00 0000
0 0 1 jump to OTP address 0x3D 7800
1 1 0 bootload code to on-chip memory via SCI-A
1 0 1 bootload external EEPROM to on-chip memory via SPI-A
1 0 0 bootload external EEPROM to on-chip memory via I2C
0 1 1 Call CAN_Boot to load from eCAN-A mailbox 1
0 0 0 bootload code to on-chip memory via GPIO port A (parallel)

Reset Code Flow - Summary

0x00 0000 M0 SARAM (1Kw)

0x3D 7800 OTP (1Kw)

0x3E 8000
FLASH (64Kw)
0x3F 7FF6

Execution Entry
0x3F F000 Boot ROM (4Kw) Point Determined
Boot Code By GPIO Pins
0x3F FB50
• •
• •

BROM vector (32w)

RESET 0x3F FFC0 0x3F FB50 Bootloading
Routines
(SCI-A, SPI-A, I2C,
eCAN-A, Parallel Load)

TMS320C28x DSP Workshop - Reset and Interrupts 4-5

Interrupts

Interrupts
Interrupt Sources
Internal Sources
TINT2
TINT1 C28x CORE
TINT0 RS

ePWM, eCAP, NMI

PIE INT1
eQEP, ADC, SCI,
(Peripheral
SPI, I2C, eCAN, INT2
Interrupt
Watchdog
Expansion) INT3
•
External Sources •
•
INT12
XINT1
INT13
XINT2
INT14
TZx
RS
XNMI_XINT13

Interrupt Processing
Maskable Interrupt Processing
Conceptual Core Overview

Core (IFR) (IER) (INTM)

Interrupt “Latch” “Switch” “Global Switch”

INT1 1

INT2 0 C28x
Core

INT14 1

‹ A valid signal on a specific interrupt line causes the latch

to display a “1” in the appropriate bit

‹ If the individual and global switches are turned “on” the

interrupt reaches the core

4-6 TMS320C28x DSP Workshop - Reset and Interrupts

 Interrupts

Interrupt Flag Register (IFR)

15 14 13 12 11 10 9 8
RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1

Pending : IFR Bit = 1

Absent : IFR Bit = 0

/*** Manual setting/clearing IFR ***/

extern cregister volatile unsigned int IFR;
IFR |= 0x0008; //set INT4 in IFR
IFR &= 0xFFF7; //clear INT4 in IFR

‹ Compiler generates atomic instructions (non-interruptible) for setting/clearing IFR

‹ If interrupt occurs when writing IFR, interrupt has priority
‹ IFR(bit) cleared when interrupt is acknowledged by CPU
‹ Register cleared on reset

Interrupt Enable Register (IER)

15 14 13 12 11 10 9 8
RTOSINT DLOGINT INT14 INT13 INT12 INT11 INT10 INT9

7 6 5 4 3 2 1 0
INT8 INT7 INT6 INT5 INT4 INT3 INT2 INT1

Enable: Set IER Bit = 1

Disable: Clear IER Bit = 0

/*** Interrupt Enable Register ***/

extern cregister volatile unsigned int IER;
IER |= 0x0008; //enable INT4 in IER
IER &= 0xFFF7; //disable INT4 in IER

‹ Compiler generates atomic instructions (non-interruptible)

for setting/clearing IER
‹ Register cleared on reset

TMS320C28x DSP Workshop - Reset and Interrupts 4-7

Interrupts

Interrupt Global Mask Bit

Bit 0
ST1 INTM

‹ INTM used to globally enable/disable interrupts:

Š Enable: INTM = 0
Š Disable: INTM = 1 (reset value)
‹ INTM modified from assembly code only:

/*** Global Interrupts ***/

asm(“ CLRC INTM”); //enable global interrupts
asm(“ SETC INTM”); //disable global interrupts

Peripheral Interrupt Expansion (PIE)

Peripheral Interrupt Expansion - PIE
Interrupt Group 1
PIE module for 96 Interrupts
PIEIFR1 PIEIER1
Peripheral Interrupts 12x8 = 96

INT1.x interrupt group INT1.1 1

INT2.x interrupt group
INT1.2 0
INT3.x interrupt group INT1
• •
INT4.x interrupt group • •
INT5.x interrupt group
• •
INT1.8 1
INT6.x interrupt group
96
INT7.x interrupt group
28x Core Interrupt logic
INT8.x interrupt group
INT9.x interrupt group INT1 – INT12
INTM

INT10.x interrupt group 28x

IER
IFR

12 Interrupts
INT11.x interrupt group Core

INT12.x interrupt group

INT13 (TINT1 / XINT13)

INT14 (TINT2)
NMI

4-8 TMS320C28x DSP Workshop - Reset and Interrupts

 Interrupts

PIE Registers
PIEIFRx register (x = 1 to 12)
15 - 8 7 6 5 4 3 2 1 0
reserved INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

PIEIERx register (x = 1 to 12)

15 - 8 7 6 5 4 3 2 1 0
reserved INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

PIE Interrupt Acknowledge Register (PIEACK)

15 - 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved PIEACKx

PIECTRL register 15 - 1 0
PIEVECT ENPIE

#include “DSP280x_Device.h”
PieCtrlRegs.PIEIFR1.bit.INTx4 = 1; //manually set IFR for XINT1 in PIE group 1
PieCtrlRegs.PIEIER3.bit.INTx5 = 1; //enable EPWM5_INT in PIE group 3
PieCtrlRegs.PIEACK.all = 0x0004; //acknowledge the PIE group 3
PieCtrlRegs.PIECTRL.bit.ENPIE = 1; //enable the PIE

PIE Interrupt Vector Table

Default Interrupt Vector Table at Reset
Prio Vector Offset
1 Reset 00 Default Vector Table
5 Int 1 02 Remapped when
6 Int 2 04 ENPIE = 1
7 Int 3 06 Memory
8 Int 4 08 0
9 Int 5 0A
10 Int 6 0C
11 Int 7 0E
12
13 Int 8 10
Int 9 0x00 0D00
14 12
Int 10 14
PIE Vectors
15 256w
16 Int 11 16
17 Int 12 18
18 Int 13 1A
19 Int 14 1C 0x3F FFC0
BROM Vectors
DlogInt 1E 64w
4 RtosInt 20 0x3F FFFF
2 EmuInt 22
3 NMI 24
PIE vector generated by config Tool
- Illegal 26
Used to initialize PIE vectors
- User 1-12 28-3E

TMS320C28x DSP Workshop - Reset and Interrupts 4-9

Interrupts

PIE Vector Mapping (ENPIE = 1)

Vector name PIE vector address PIE vector Description
Not used 0x00 0D00 Reset Vector Never Fetched Here
INT1 0x00 0D02 INT1 re-mapped below
…… …… …… re-mapped below
INT12 0x00 0D18 INT12 re-mapped below
INT13 0x00 0D1A XINT1 Interrupt Vector
INT14 0x00 0D1C Timer2 – RTOS Vector
Datalog 0x00 0D1D Data logging vector
…… …… ……
USER11 0x00 0D3E User defined TRAP
INT1.1 0x00 0D40 PIEINT1.1 interrupt vector
…… …… ……
INT1.8 0x00 0D4E PIEINT1.8 interrupt vector
…… …… ……
INT12.1 0x00 0DF0 PIEINT12.1 interrupt vector
…… …… ……
INT12.8 0x00 0DFE PIEINT12.8 interrupt vector
¾ PIE vector space - 0x00 0D00 – 256 Word memory in Data space

¾ RESET and INT1-INT12 vector locations are Re-mapped

¾ CPU vectors are remapped to 0x00 0D00 in Data space

F280x PIE Interrupt Assignment Table

INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1

INT1 WAKEINT TINT0 ADCINT XINT2 XINT1 SEQ2INT SEQ1INT

EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
INT2 _TZINT _TZINT _TZINT _TZINT _TZINT _TZINT
EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
INT3 _INT _INT _INT _INT _INT _INT
ECAP4 ECAP3 ECAP2 ECAP1
INT4 _INT _INT _INT _INT
EQEP2 EQEP1
INT5 _INT _INT

INT6 SPITXINTD SPIRXINTD SPITXINTC SPIRXINTC SPITXINTB SPIRXINTB SPITXINTA SPIRXINTA

INT7

INT8 I2CINT2A I2CINT1A

ECAN1 ECAN0 ECAN1 ECAN0
INT9 _INTB _INTB _INTA _INTA
SCITXINTB SCIRXINTB SCITXINTA SCIRXINTA

INT10

INT11

INT12

4 - 10 TMS320C28x DSP Workshop - Reset and Interrupts

 Interrupts

Hardware Interrupts

Device Vector Mapping - Summary

RESET
<0x3F FFC0>

Reset Vector <0x3F FB50> = Boot Code

Flash Entry Point <0x3F 7FF6 > = LB _c_int00
User Code Start < _c_int00 >

_c_int00:
. . .
CALL main()
Initialization ( )
{
EALLOW
main() Load PIE Vectors PIE Vector Table
{ initialization(); Enable the PIEIER
256 Word RAM
. . . Enable PIECTRL
} Enable Core IER 0x00 0D00 – 0DFF
Enable INTM
EDIS
}

TMS320C28x DSP Workshop - Reset and Interrupts 4 - 11

Interrupts

Interrupt Response and Latency

Interrupt Response - Hardware Sequence
CPU Action Description
Registers → stack 14 Register words auto saved
0 → IFR (bit) Clear corresponding IFR bit
0 → IER (bit) Clear corresponding IER bit
1 → INTM/DBGM Disable global ints/debug events
Vector → PC Loads PC with int vector address
Clear other status bits Clear LOOP, EALLOW, IDLESTAT

Note: some actions occur simultaneously, none are interruptible

T ST0
AH AL
PH PL
AR1 AR0
DP ST1
DBSTAT IER
PC(msw) PC(lsw)

Interrupt Latency
Latency
ext. Internal
interrupt interrupt Assumes ISR in
occurs occurs internal RAM
here here

cycles
2 4 3 3 1 3
Recognition Get vector ISR
Sync ext. F1/F2/D1 of Save D2/R1/R2 of instruction
signal delay (3), SP and place ISR return ISR
alignment (1), in PC executed
instruction address instruction on next
(ext. interrupt (3 reg. (3 reg. pairs
interrupt placed in pairs cycle
saved)
only) pipeline saved)

Above is for PIE enabled or disabled

‹ Minimum latency (to when real work occurs in the ISR):

¾ Internal interrupts: 14 cycles
¾ External interrupts: 16 cycles

‹ Maximum latency: Depends on wait states, INTM, etc.

4 - 12 TMS320C28x DSP Workshop - Reset and Interrupts

 System Initialization

Introduction
This module discusses the operation of the OSC/PLL-based clock module and watchdog timer.
Also, various low power modes, general-purpose digital I/O ports, and the EALLOW protected
registers will be covered.

Learning Objectives
Learning Objectives

‹ OSC/PLL Clock Module

‹ Watchdog Timer

‹ Low Power Modes

‹ General Purpose Digital I/O

‹ EALLOW Protected Registers

TMS320C28x DSP Workshop - System Initialization 5-1

Module Topics

Module Topics
System Initialization.................................................................................................................................. 5-1

Module Topics......................................................................................................................................... 5-2

Oscillator/PLL Clock Module................................................................................................................. 5-3
Watchdog Timer...................................................................................................................................... 5-5
Low Power Modes................................................................................................................................... 5-9
General-Purpose Digital I/O .................................................................................................................5-11
EALLOW Protected Registers................................................................................................................5-15
Lab 5: System Initialization ...................................................................................................................5-16

5-2 TMS320C28x DSP Workshop - System Initialization

 Oscillator/PLL Clock Module

Oscillator/PLL Clock Module

C280x Oscillator / PLL Clock Module
SysCtrlRegs.PLLCR.bit.DIV (lab file: SysCtrl.c)

X1 / XCLKIN
Watchdog
Module CLKIN C280x

XTAL OSC
Core
OSCCLK
crystal • • (PLL bypass)
0
/1 SYSCLKOUT

MUX
or • •
X2 VCOCLK /2
PLL 1 HISPCP LOSPCP
PLLCR.bit.DIV
default = 0000b
•
PLLSTS.bit.CLKINDIV HSPCLK LSPCLK
default = /2 (ADC) (SCI/SPI)
(All other peripherals
DIV Clock Frequency (CLKIN) clocked by SYSCLKOUT)
0000 OSCCLK / CLKINDIV (PLL bypass)
0001 OSCCLK x 1 / CLKINDIV
0010 OSCCLK x 2 / CLKINDIV Input Clock Fail Detection
0011 OSCCLK x 3 / CLKINDIV PLL will issue a “limp mode”
0100 OSCCLK x 4 / CLKINDIV clock (1-4 MHz) if input clock
0101 OSCCLK x 5 / CLKINDIV is removed after clock has
0110 OSCCLK x 6 / CLKINDIV been present initially
0111 OSCCLK x 7 / CLKINDIV
1000 OSCCLK x 8 / CLKINDIV
1001 OSCCLK x 9 / CLKINDIV
1010 OSCCLK x 10 / CLKINDIV

The OSC/PLL clock module provides all the necessary clocking signals for C28x devices. The
PLL has a 4-bit ratio control to select different CPU clock rates. Two modes of operation are
supported – crystal operation, and external clock source operation. Crystal operation allows the
use of an external crystal/resonator to provide the time base to the device. External clock source
operation allows the internal oscillator to be bypassed, and the device clocks are generated from
an external clock source input on the X1/CLKIN pin. The watchdog receives a clock signal from
OSCCLK. The C28x core provides a SYSCLKOUT clock signal. This signal is prescaled to
provide a clock source for some of the on-chip peripherals through the high-speed and low-speed
peripheral clock prescalers. Other peripherals are clocked by SYSCLKOUT and use their own
clock prescalers for operation.

TMS320C28x DSP Workshop - System Initialization 5-3

Oscillator/PLL Clock Module

Peripheral Clock Control Registers

(lab file: SysCtrl.c)

SysCtrlRegs.PCLKCR0.bit.name
15 14 13 - 12 11 10 9 8
ECANB ECANA reserved SCIB SCIA SPIB SPIA
ENCLK ENCLK ENCLK ENCLK ENCLK ENCLK
7 6 5 4 3 2 1-0
SPID SPIC reserved I2CA ADC TBCLK reserved
ENCLK ENCLK ENCLK ENCLK SYNC

SysCtrlRegs.PCLKCR1.bit.name
15 14 13 - 12 11 10 9 8
EQEP2 EQEP1 reserved ECAP4 ECAP3 ECAP2 ECAP1
ENCLK ENCLK ENCLK ENCLK ENCLK ENCLK
7-6 5 4 3 2 1 0
reserved EPWM6 EPWM5 EPWM4 EPWM3 EPWM2 EPWM1
ENCLK ENCLK ENCLK ENCLK ENCLK ENCLK

Module Enable Clock Bit

0 = disable
1 = enable

The peripheral clock control register allows individual peripheral clock signals to be enabled or
disabled. If a peripheral is not being used, its clock signal could be disabled, thus reducing power
consumption.

High / Low – Speed Peripheral Clock

Prescaler Registers (lab file: SysCtrl.c)
SysCtrlRegs.HISPCP.all
15 - 3 2-0
reserved HSPCLK

ADC
SysCtrlRegs.LOSPCP.all
15 - 3 2-0
reserved LSPCLK

SCI / SPI
H/LSPCLK Peripheral Clock Frequency
000 SYSCLKOUT / 1
001 SYSCLKOUT / 2 (default HISPCP)
NOTE:
010 SYSCLKOUT / 4 (default LOSPCP)
011 SYSCLKOUT / 6 All Other
100 SYSCLKOUT / 8 Peripherals
101 SYSCLKOUT / 10 Clocked By
110 SYSCLKOUT / 12 SYSCLKOUT
111 SYSCLKOUT / 14

5-4 TMS320C28x DSP Workshop - System Initialization

 Watchdog Timer

Watchdog Timer
Watchdog Timer

‹ Resets the C28x if the CPU crashes

Š Watchdog counter runs independent of CPU
Š If counter overflows, reset or interrupt is
triggered
Š CPU must write correct data key sequence to
reset the counter before overflow
‹ Watchdog must be serviced (or disabled)
within ~6.55ms after reset (20 MHz
OSCCLK for 100 MHz device)
‹ This translates into 131,072 instructions!

The watchdog timer provides a safeguard against CPU crashes by automatically initiating a reset
if it is not serviced by the CPU at regular intervals. In motor control applications, this helps
protect the motor and drive electronics when control is lost due to a CPU lockup. Any CPU reset
will revert the PWM outputs to a high-impedance state, which should turn off the power
converters in a properly designed system.

The watchdog timer is running immediately after system power-up/reset, and must be dealt with
by software soon after. Specifically, you have 6.55 ms (for a 100 MHz device) after any reset
before a watchdog initiated reset will occur. This translates into 131,072 instruction cycles,
which is a seemingly tremendous amount! Indeed, this is plenty of time to get the watchdog
configured as desired and serviced. A failure of your software to properly handle the watchdog
after reset could cause an endless cycle of watchdog initiated resets to occur.

TMS320C28x DSP Workshop - System Initialization 5-5

Watchdog Timer

Watchdog Timer Module (lab file: SysCtrl.c)

SCSR . 0
OSCCLK
/64 111
6 - Bit /32 110 WDOVERRIDE
Free - /16 101 WDPS
WDCR . 2 - 0
/512 • Running /8 100
Counter /4 011 • • •
/2 010 WDCR . 6
CLR 001
WDDIS
000
•
•
WDCNTR . 7 - 0
System
Reset • 8 - Bit Watchdog
WDFLAG
One-Cycle WDCR . 7
Counter
Delay
CLR
WDRST
Output •
Pulse
WDCR . 5 - 3 WDCHK 2-0 WDINT
55 + AA SCSR .1
Detector Good Key 3 WDENINT
•• /
•• 3
/ Bad WDCR Key
Watchdog 1 0 1
Reset Key WDKEY . 7 - 0
Register

Watchdog Period Selection

WDPS FRC WD timeout period

Bits rollover @ 20 MHz OSCCLK
00x: 1 6.55 ms
010: 2 13.11 ms
011: 4 26.21 ms
100: 8 52.43 ms
101: 16 104.86 ms
110: 32 209.72 ms
111: 64 419.43 ms

‹ WDPS set to 000 after any CPU reset

‹ Watchdog starts counting immediately after reset
is released
(for OSCCLK = 20 MHz ⇒ (1/20 MHz) * (512*256) = 6.55 ms)

5-6 TMS320C28x DSP Workshop - System Initialization

 Watchdog Timer

Watchdog Timer Control Register

SysCtrlRegs.WDCR (lab file: SysCtrl.c)

WD Flag Bit
Gets set when the WD causes a reset
• Writing a 1 clears this bit
• Writing a 0 has no effect

15 - 8 7 6 5-3 2-0

reserved WDFLAG WDDIS WDCHK WDPS

Logic Check Bits WD Prescale

Write as 101 or reset Selection Bits
Watchdog Disable Bit immediately triggered
Write 1 to disable
(Functions only if WD OVERRIDE
bit in SCSR is equal to 1)

Resetting the Watchdog

SysCtrlRegs.WDKEY (lab file: SysCtrl.c)

15 - 8 7-0

reserved WDKEY

‹ Allowable write values:

55h - counter enabled for reset on next AAh write
AAh - counter set to zero if reset enabled
‹ Writing any other value has no effect
‹ Watchdog should not be serviced solely in
an ISR
Š If main code crashes, but interrupt continues to
execute, the watchdog will not catch the crash
Š Could put the 55h WDKEY in the main code, and
the AAh WDKEY in an ISR; this catches main
code crashes and also ISR crashes

TMS320C28x DSP Workshop - System Initialization 5-7

Watchdog Timer

WDKEY Write Results

Sequential Value Written

Step to WDKEY Result

1 AAh No action
2 AAh No action
3 55h WD counter enabled for reset on next AAh write
4 55h WD counter enabled for reset on next AAh write
5 55h WD counter enabled for reset on next AAh write
6 AAh WD counter is reset
7 AAh No action
8 55h WD counter enabled for reset on next AAh write
9 AAh WD counter is reset
10 55h WD counter enabled for reset on next AAh write
11 23h No effect

System Control and Status Register

SysCtrlRegs.SCSR (lab file: SysCtrl.c)

WD Override (protect bit)

Protects WD from being disabled
0 = WDDIS bit in WDCR has no effect (WD cannot be disabled)
1 = WDDIS bit in WDCR can disable the watchdog
• This bit is a clear-only bit (write 1 to clear)
• The reset default of this bit is a 1

15 - 3 2 1 0

reserved WDINTS WDENINT WDOVERRIDE

WD Interrupt Status WD Enable Interrupt

(read only) 0 = WD generates a DSP reset
0 = active 1 = WD generates a WDINT interrupt
1 = not active

5-8 TMS320C28x DSP Workshop - System Initialization

 Low Power Modes

Low Power Modes

Low Power Modes

Low Power CPU Logic Peripheral Watchdog PLL /

Mode Clock Logic Clock Clock OSC
Normal Run on on on on

IDLE off on on on

STANDBY off off on on

HALT off off off off

Low Power Mode Control Register 0

SysCtrlRegs.LPMCR0 (lab file: SysCtrl.c)

Watchdog Interrupt 000000 = 2 OSCCLKs

wake device from 000001 = 3 OSCCLKs
STANDBY Qualify before waking
from STANDBY mode .. .. ..
0 = disable (default) . . .
1 = enable 111111 = 65 OSCCLKS (default)

15 14 - 8 7-2 1-0
WDINTE reserved QUALSTDBY LPM0

Low Power Mode Selection

00 = Idle (default)
Low Power Mode Entering 01 = Standby
1. Set LPM bits 1x = Halt
2. Enable desired exit interrupt(s)
3. Execute IDLE instruction
4. The Power down sequence of the hardware
depends on LP mode

TMS320C28x DSP Workshop - System Initialization 5-9

Low Power Modes

GPIO Low Power Wakeup Select

SysCtrlRegs.GPIOLPSEL

31 30 29 28 27 26 25 24

GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO25 GPIO24

23 22 21 20 19 18 17 16
GPIO23 GPIO22 GPIO21 GPIO20 GPIO19 GPIO18 GPIO17 GPIO16

15 14 13 12 11 10 9 8

GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8

7 6 5 4 3 2 1 0
GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0

Wake device from

HALT and STANDBY mode
(GPIO Port A)
0 = disable (default)
1 = enable

Low Power Mode Exit

Exit
Interrupt RESET Watchdog Any GPIO
or Interrupt Enabled Port A
Low Power XNMI Interrupt Signal
Mode

IDLE yes yes yes yes

STANDBY yes yes no yes

HALT yes no no yes

5 - 10 TMS320C28x DSP Workshop - System Initialization

 General-Purpose Digital I/O

General-Purpose Digital I/O

C280x GPIO Register Structure (lab file: Gpio.c)

GPIO Port A Mux1

GPIO Port A
Register (GPAMUX1)
[GPIO 0 to 15] GPIO Port A
Direction Register
(GPADIR)
GPIO Port A Mux2 [GPIO 0 to 31]
Internal Bus

Register (GPAMUX2)
[GPIO 16 to 31]

GPIO Port B Mux1

GPIO Port B
Register (GPBMUX1)
[GPIO 32 to 34] GPIO Port B
Direction Register
(GPBDIR)
GPIO Port B Mux2 [GPIO 32 to 34]
Register (GPBMUX2)
[reserved]

F2808 GPIO Pin Assignment (1 of 3)

GPAMUX1 (lab file: Gpio.c)
Bits 0, 0 (default) 0, 1 1, 0 1, 1
1-0 GPIO0 EPWM1A reserved reserved
3-2 GPIO1 EPWM1B SPISIMO reserved
QUALPRD0

5-4 GPIO2 EPWM2A reserved reserved

GPACTRL

7-6 GPIO3 EPWM2B SPISOMID reserved

9-8 GPIO4 EPWM3A reserved reserved
11-10 GPIO5 EPWM3B SPICLKD ECAP1
13-12 GPIO6 EPWM4A EPWMSYNCI EPWMSYNCO
15-14 GPIO7 EPWM4B SPISTED ECAP2
17-16 GPIO8 EPWM5A CANTXB ADCSOCAO
19-18 GPIO9 EPWM5B SCITXB ECAP3
QUALPRD1

21-20 GPIO10 EPWM6A CANRXB ADCSOCBO

GPACTRL

23-22 GPIO11 EPWM6B SCIRXB ECAP4

25-24 GPIO12 TZ1 CANTXB SPISIMOB
27-26 GPIO13 TZ2 CANRXB SPISOMIB
29-28 GPIO14 TZ3 SCITXB SPICLKB
31-30 GPIO15 TZ4 SCIRXB SPISTEB

TMS320C28x DSP Workshop - System Initialization 5 - 11

General-Purpose Digital I/O

F2808 GPIO Pin Assignment (2 of 3)

GPAMUX2 (lab file: Gpio.c)
Bits 0, 0 (default) 0, 1 1, 0 1, 1
1-0 GPIO16 SPISIMOA CANTXB TZ5
3-2 GPIO17 SPISOMIA CANRXB TZ6

QUALPRD2
5-4 GPIO18 SPICLKA SCITXB reserved

GPACTRL
7-6 GPIO19 SPISTEA SCIRXB reserved
9-8 GPIO20 EQEP1A SPISIMOC CANTXB
11-10 GPIO21 EQEP1B SPISOMIC CANRXB
13-12 GPIO22 EQEP1S SPICLKC SCITXB
15-14 GPIO23 EQEP1I SPISTEC SCIRXB
17-16 GPIO24 ECAP1 EQEP2A SPISIMOB
19-18 GPIO25 ECAP2 EQEP2B SPISOMIB

QUALPRD3
21-20 GPIO26 ECAP3 EQEP2I SPICLKB

GPACTRL
23-22 GPIO27 ECAP4 EQEP2S SPISTEB
25-24 GPIO28 SCIRXDA reserved TZ5
27-26 GPIO29 SCITXDA reserved TZ6
29-28 GPIO30 CANRXA reserved reserved
31-30 GPIO31 CANTXA reserved reserved

F2808 GPIO Pin Assignment (3 of 3)

GPBMUX1 (lab file: Gpio.c)
Bits 0, 0 (default) 0, 1 1, 0 1, 1 QUALPRD0
1-0 GPIO32 SDAA EPWMSYNCI ADCSOCAO GPBCTRL
3-2 GPIO33 SCLA EPWMSYNCO ADCSOCBO
5-4 GPIO34 reserved reserved reserved

5 - 12 TMS320C28x DSP Workshop - System Initialization

 General-Purpose Digital I/O

C280x GPIO Functional Block Diagram

Peripheral Peripheral Peripheral
GPxDIR 1 2 3
GPxSET
GPxCLEAR I/O DIR Bit
GPxTOGGLE 0 = Input
1 = Output
GPxMUX1/2
GPxDAT
Out
• • 10
01
MUX Control Bit
00•
• •11
00 = GPIO
I/O DAT 01 = Peripheral
Bit (R/W) In 10 = Peripheral
11 = Peripheral

GPxPUD Internal
15 - 8 7-0 Pull-Up
GPACTRL
QUALPRD1
31 - 24
QUALPRD0
23 - 16 • • 0 = enable
(default GPIO 12-31)
1 = disable
QUALPRD3 QUALPRD2 (default GPIO 0-11)
31 - 8 7-0
GPBCTRL reserved QUALPRD0 Pin
00h no qualification (SYNC to SYSCLKOUT)
01h QUALPRD = SYSCLKOUT/2 GPAQSEL1 / GPAQSEL2 / GPBQSEL1 / GPBQSEL2
02h QUALPRD = SYSCLKOUT/4 00 = SYNC to SYSCLKOUT
.. .. .. 01 = qual to 3 samples – time specified in GPxCTRL
. . . 10 = qual to 6 samples – time specified in GPxCTRL
FFh QUALPRD = SYSCLKOUT/510 11 = no sync or qual (for peripheral; GPIO same as 00)

C280x GPIO Control Registers

GpioCtrlRegs.name (lab file: Gpio.c)

Name Description
GPACTRL GPIO A Control Register [GPIO 0 – 31]
GPAQSEL1 GPIO A Qualifier Select 1 Register [GPIO 0 – 15]
GPAQSEL2 GPIO A Qualifier Select 2 Register [GPIO 16 – 31]
GPAMUX1 GPIO A Mux1 Register [GPIO 0 – 15]
GPAMUX2 GPIO A Mux2 Register [GPIO 16 – 31]
GPADIR GPIO A Direction Register [GPIO 0 – 31]
GPAPUD GPIO A Pull-Up Disable Register [GPIO 0 – 31]
GPBCTRL GPIO B Control Register [GPIO 32 – 34]
GPBQSEL1 GPIO B Qualifier Select 1 Register [GPIO 32 – 34]
GPBQSEL2 GPIO B Qualifier Select 2 Register [reserved]
GPBMUX1 GPIO B Mux1 Register [GPIO 32 – 34]
GPBMUX2 GPIO B Mux2 Register [reserved]
GPBDIR GPIO B Direction Register [GPIO 32 – 34]
GPBPUD GPIO B Pull-Up Disable Register [GPIO 32 – 34]

TMS320C28x DSP Workshop - System Initialization 5 - 13

General-Purpose Digital I/O

C280x GPIO Data Registers

GpioDataRegs.name (lab file: Gpio.c)

Name Description
GPADAT GPIO A Data Register [GPIO 0 – 31]
GPASET GPIO A Data Set Register [GPIO 0 – 31]
GPACLEAR GPIO A Data Clear Register [GPIO 0 – 31]
GPATOGGLE GPIO A Data Toggle [GPIO 0 – 31]
GPBDAT GPIO B Data Register [GPIO 32 – 34]
GPBSET GPIO B Data Set Register [GPIO 32 – 34]
GPBCLEAR GPIO B Data Clear Register [GPIO 32 – 34]
GPBTOGGLE GPIO B Data Toggle [GPIO 32 – 34]

External Interrupts
‹ There are 3 external interrupt signals: XINT1, XINT2, XNMI
‹ Any GPIO port A pin (GPIO0 – GPIO31) can be mapped to any
of these three interrupt signals
GpioIntRegs.name
Name Description
GPIOXINT1SEL selects GPIO0 – GPIO31 pin as XINT1 source
GPIOXINT2SEL selects GPIO0 – GPIO31 pin as XINT2 source
GPIOXNMISEL selects GPIO0 – GPIO31 pin as XNMI source

XIntruptRegs.name
Name Description
XINT1CR enable / disable interrupt, polarity
XINT2CR enable / disable interrupt, polarity
XNMICR enable / disable interrupt, polarity

For each external interrupt, there is also a 16-bit counter (XINT1CTR, XINT2CTR, and XNMICTR)
that is reset to 0x0000 whenever an interrupt edge is detected. These counters can be used to
accurately time stamp an occurrence of the interrupt.

‹ Note that the eCAP pins can also be used as external

interrupts, and are completely independent on XINT1, XINT2,
and XNMI

5 - 14 TMS320C28x DSP Workshop - System Initialization

 EALLOW Protected Registers

EALLOW Protected Registers

EALLOW Protected Registers
Register Name Address Range size (x16)
Device Emulation 0x00 0880 – 0x00 09FF 384
FLASH (also protected by CSM) 0x00 0A80 – 0x00 0ADF 96
PF0
Code Security Module 0x00 0AE0 – 0x00 0AEF 16
PIE Vector Table 0x00 0D00 – 0x00 0DFF 256
eCANA 0x00 6000 – 0x00 60FF 256 (128x32)
eCANB 0x00 6200 – 0x00 62FF 256 (128x32)
PF1 ePWM1 – 6 0x00 6800 – 0x00 697F 384 (32x32)
GPIO Control 0x00 6F80 – 0x00 6FBF 128 (64x32)
GPIO Interrupt 0x00 6FE0 – 0x00 6FFF 32 (16x32)
PF2 System Control 0x00 7010 – 0x00 702F 32

while(1) // dummy loop - wait for an interrupt

{
asm(" EALLOW"); // enable EALLOW protected register access
SysCtrlRegs.WDKEY=0x55; // watchdog enabled for reset on next 0xAA write
asm(" EDIS"); // disable EALLOW protected register access
}
Note: “SysCtrlRegs.WDKEY=0xAA” is located in an interrupt service routine

Lab 5: Procedure - System Initialization

‹ LAB5 files have been provided as a starting point
‹ Modify LAB5 files to:
Part 1
Š Disable the watchdog – clear WD flag, disable watchdog, WD
prescale = 1
Š Setup the clock module – PLL = x10/2, HISPCP = /1, LOSPCP = /4,
low-power modes to default values, enable all module clocks
Š Setup system control register – DO NOT clear WD OVERRIDE bit,
WD generate a DSP reset
Š Setup shared I/O pins – set all GPIO pins to GPIO function (e.g. a
“00” setting for GPIO function, and a “01”, 10”, or “11” setting for a
peripheral function)
Part 2
Š Initialize peripheral interrupt expansion (PIE) vectors

‹ Build, debug, and test your code using Code

Composer Studio

TMS320C28x DSP Workshop - System Initialization 5 - 15

Lab 5: System Initialization

Lab 5: System Initialization

¾ Objective
The objective of this lab is to perform the processor system initialization by applying the
techniques discussed in module 5. Additionally, the peripheral interrupt expansion (PIE) vectors
will be initialized and tested using the information discussed in the previous module. This
initialization process will be used again in the module 6 analog-to-digital converter lab, and the
module 7 control peripherals lab. The system initialization for this lab will consist of the
following:

• Disable the watchdog – clear WD flag, disable watchdog, WD prescale = 1

• Setup the clock module – PLL = x10/2, HISPCP = /1, LOSPCP = /4, low-power modes to
default values, enable all module clocks
• Setup system control register – DO NOT clear WD OVERRIDE bit, WD generate a DSP
reset
• Setup shared I/O pins – set all GPIO pins to GPIO function (e.g. a "00" setting for GPIO
function, and a “01”, “10”, or “11” setting for a peripheral function.)

The first part of the lab exercise will setup the system initialization and test the watchdog
operation by having the watchdog cause a reset. In the second part of the lab exercise the PIE
vectors will be added and tested by using the watchdog to generate an interrupt. This lab will
make use of the DSP280x C-code header files to simplify the programming of the device, as well
as take care of the register definitions and addresses. Please review these files, and make use of
them in the future, as needed.

¾ Procedure

Create Project File

Note: LAB 5 files have been provided as a starting point for the lab and need to be
completed. DO NOT copy files from a previous lab.

1. Create a new project called Lab5.pjt in C:\C28x\Labs\Lab5 and add the

following files to it:

Main_5.c DSP280x_GlobalVariableDefs.c
Lab.cdb DSP280x_Headers_BIOS.cmd
User_5_6_7.cmd CodeStartBranch.asm
SysCtrl.c Gpio.c

Note that include files, such as DSP280x_Device.h and Lab.h, are automatically
added at project build time. (Also, the generated linker command file, Labcfg.cmd, is
automatically added with the configuration file).

5 - 16 TMS320C28x DSP Workshop - System Initialization

 Lab 5: System Initialization

Project Build Options

2. We need to setup the search path to include the peripheral register header files. Click:

Project Æ Build Options…

Select the Compiler tab. In the Preprocessor Category, find the Include Search
Path (-i) box and enter:

..\DSP280x_headers\include

This is the path for the header files. Then select OK to save the Build Options.

Modify Memory Configuration

3. Open and inspect the user linker command file User_5_6_7.cmd. Notice that the
section “codestart” is being linked to a memory block named BEGIN_M0. The
codestart section contains code that branches to the code entry point of the project. The
bootloader must branch to the codestart section at the end of the boot process. Recall that
the "Boot to M0" bootloader mode branches to address 0x000000 upon bootloader
completion.

Modify the configuration file lab.cdb to create a new memory block named
BEGIN_M0: base = 0x000000, length = 0x0002, space = code. Uncheck the “create
a heap in memory” box. You will also need to modify the existing memory block
M0SARAM to avoid any overlaps with this new memory block.

Setup System Initialization

4. Modify SysCtrl.c to implement the system initialization as described in the objective
for this lab.

5. Open and inspect Gpio.c. Notice that the shared I/O pins have been set to the GPIO
function. (Note: In Main_5.c do not edit the “main loop” section. This section will be
used to test the watchdog operation.) Save your work.

Build and Load

6. Click the “Build” button and watch the tools run in the build window. The output
file should automatically load.

7. Under Debug on the menu bar click “Reset CPU”.

8. Under Debug on the menu bar click “Go Main”. You should now be at the start of
Main().

TMS320C28x DSP Workshop - System Initialization 5 - 17

Lab 5: System Initialization

Run the Code – Watchdog Reset

9. Place the cursor on the first line of code in main() and set a breakpoint by right
clicking the mouse key and select Toggle Software Breakpoint. Notice that
line is highlighted with a red dot indicating that the breakpoint has been set.

10. Single-step your code into the “main loop” section and watch the lines of code
execute. If you don’t want to see each line execute, place the cursor in the “main
loop” section (on the asm(“ NOP”); instruction line) and right click the mouse key
and select Run To Cursor. This is the same as setting a breakpoint on the selected
line, running to that breakpoint, and then removing the breakpoint.

11. Run your code for a few seconds by using the <F5> key, or using the Run button on the
vertical toolbar, or using Debug Æ Run on the menu bar. After a few seconds halt
your code by using Shift <F5>, or the Halt button on the vertical toolbar. Where did your
code stop? Are the results as expected? If things went as expected, your code should be
in the “main loop”.

12. Modify the InitSysCtrl() function to enable the watchdog (WDCR). This will
enable the watchdog to function and cause a reset. Save the file and click the “Build”
button. Then reset the DSP by clicking on Debug Æ Reset CPU. Under Debug on
the menu bar click “Go Main”.

13. Single-step your code off of the breakpoint.

14. Run your code. Where did your code stop? Are the results as expected? If things went
as expected, your code should stop at the breakpoint.

Setup PIE Vector for Watchdog Interrupt

The first part of this lab exercise used the watchdog to generate a CPU reset. This was tested
using a breakpoint set at the beginning of main(). Next, we are going to use the watchdog
to generate an interrupt. This part will demonstrate the interrupt concepts learned in the
previous module.

15. Add the following files to the project:

PieCtrl_5_6_7_8_9.c
DefaultIsr_5_6_7.c

Check your files list to make sure the files are there.

16. In Main_5.c, add code to call the InitPieCtrl() function. There are no passed
parameters or return values, so the call code is simply:

InitPieCtrl();

17. Using the “PIE Interrupt Assignment Table” shown in the previous module find the
location for the watchdog interrupt, “WAKEINT”.

5 - 18 TMS320C28x DSP Workshop - System Initialization

 Lab 5: System Initialization

18. Modify main() to do the following:

enable the "WAKEINT" interrupt in the PIE (Hint: use the PieCtrlRegs structure)
enable core INT1 (IER register)
enable global interrupts (INTM bit)

19. In SysCtrl.c modify the system control and status register (SCSR) to cause the
watchdog to generate a WAKEINT rather than a reset.

20. Open and inspect DefaultIsr_5_6_7.c. This file contains interrupt service
routines. The ISR for WAKEINT has been trapped by an emulation breakpoint contained
in an inline assembly statement using “ESTOP0”. This gives the same results as placing
a breakpoint in the ISR. We will run the lab exercise as before, except this time the
watchdog will generate an interrupt. If the registers have been configured properly, the
code will be trapped in the ISR.

21. Modify the configuration file Lab.cdb to setup the PIE vector for the watchdog
interrupt. Click on the plus sign (+) to the left of Scheduling and again on the plus
sign (+) to the left of HWI – Hardware Interrupt Service Routine
Manager. Click the plus sign (+) to the left of PIE INTERRUPTS. Locate the
interrupt location for the watchdog. Right click, select Properties, and type
_WAKEINT_ISR (with a leading underscore) in the function field. Click OK and save
all updates.

Build and Load

22. Save all changes to the files and click the “Build” button. Then reset the DSP, and
then “Go Main”.

Run the Code – Watchdog Interrupt

23. Place the cursor in the “main loop” section, right click the mouse key and select
Run To Cursor.

24. Run your code. Where did your code stop? Are the results as expected? If things went
as expected, your code should stop at the “ESTOP0” instruction in the WAKEINT ISR.

End of Exercise

Note: By default, the watchdog timer is enabled out of reset. Code in the file
CodeStartBranch.asm has been configured to disable the watchdog. This can be
important for large C code projects (ask your instructor if this has not already been
explained). During this lab exercise, the watchdog was actually re-enabled (or disabled
again) in the file SysCtrl.c.

TMS320C28x DSP Workshop - System Initialization 5 - 19

Lab 5: System Initialization

5 - 20 TMS320C28x DSP Workshop - System Initialization

 Analog-to-Digital Converter

Introduction
This module explains the operation of the analog-to-digital converter. The system consists of a
12-bit analog-to-digital converter with 16 analog input channels. The analog input channels have
a range from 0 to 3 volts. Two input analog multiplexers are used, each supporting 8 analog input
channels. Each multiplexer has its own dedicated sample and hold circuit. Therefore, sequential,
as well as simultaneous sampling is supported. Also, the ADC system features programmable
auto sequence conversions with 16 results registers. Start of conversion (SOC) can be performed
by an external trigger, software, or an ePWM event.

Learning Objectives
Learning Objectives

‹ Understand the operation of

Analog-to-Digital converter
‹ Show how to use the Analog-to-
Digital converter to perform data
acquisition

TMS320C28x DSP Workshop - Analog-to-Digital Converter 6-1

Module Topics

Module Topics
Analog-to-Digital Converter..................................................................................................................... 6-1

Module Topics......................................................................................................................................... 6-2

Analog-to-Digital Converter................................................................................................................... 6-3
Analog-to-Digital Converter Registers............................................................................................... 6-5
Example – Sequencer “Start/Stop” Operation ...................................................................................6-10
ADC Conversion Result Buffer Register...........................................................................................6-11
Numerical Format..............................................................................................................................6-12
Lab 6: Analog-to-Digital Converter ......................................................................................................6-13

6-2 TMS320C28x DSP Workshop - Analog-to-Digital Converter

 Analog-to-Digital Converter

Analog-to-Digital Converter
ADC Module Block Diagram (Cascaded Mode)
Analog MUX
ADCINA0
ADCINA1 Result MUX
MUX S/H
RESULT0
...
ADCINA7
A A
RESULT1
S/H 12-bit A/D RESULT2
MUX Converter

...
ADCINB0
ADCINB1 MUX S/H Result
SOC EOC
...

B B Select RESULT15
ADCINB7 Autosequencer
MAX_CONV1
Ch Sel (CONV00)
Ch Sel (CONV01)
Ch Sel (CONV02)
Software Ch Sel (CONV03)
ePWM_SOC_A

...
ePWM_SOC_B
External Pin Ch Sel (CONV15)
(GPIO/XINT2_ADCSOC)
Start Sequence
Trigger

ADC Module Block Diagram (Dual-Sequencer mode)

Analog MUX
Result MUX
ADCINA0
ADCINA1 S/H RESULT0
MUX
...

A A RESULT1
12-bit A/D
...
ADCINA7 Result
S/H Converter
MUX Select RESULT7
ADCINB0 Sequencer
ADCINB1 MUX S/H Arbiter
...

B B SOC1/ SOC2/
RESULT8
ADCINB7 EOC1 EOC2 RESULT9
...

SEQ1 SEQ2 Result

Autosequencer Autosequencer Select RESULT15
MAX_CONV1 MAX_CONV2
Ch Sel (CONV00) Ch Sel (CONV08)
Ch Sel (CONV01) Ch Sel (CONV09)
Ch Sel (CONV02) Ch Sel (CONV10)
Software
...
...

Software
ePWM_SOC_A
ePWM_SOC_B
External Pin Ch Sel (CONV07) Ch Sel (CONV15)
(GPIO/XINT2 Start Sequence Start Sequence
_ADCSOC)
Trigger Trigger

TMS320C28x DSP Workshop - Analog-to-Digital Converter 6-3

Analog-to-Digital Converter

ADC Module
‹ 12-bit resolution ADC core
‹ Sixteen analog inputs (range of 0 to 3V)
‹ Two analog input multiplexers
Š Up to 8 analog input channels each
‹ Two sample/hold units (for each input mux)
‹ Sequential and simultaneous sampling modes
‹ Autosequencing capability - up to 16
autoconversions
Š Two independent 8-state sequencers
Š “Dual-sequencer mode”
Š “Cascaded mode”
‹ Sixteen individually addressable result registers
‹ Multiple trigger sources for start-of-conversion
Š External trigger, S/W, and ePWM triggers

F2808 ADC Clocking Example

CLKIN PLLCR SYSCLKOUT HISPCP HSPCLK
(20 MHz) DIV (100 MHz) HSPCLK (100 MHz)
bits To CPU
bits
1010b 000b
PCLKCR0.ADCENCLK = 1

ADCTRL3 FCLK ADCTRL1 ADCCLK

ADCCLKPS (12.5 MHz) (12.5 MHz) To ADC
CPS bit pipeline
bits
0100b
ADCTRL1
0b sampling
ACQ_PS window
FCLK = HSPCLK/(2*ADCCLKPS) ADCCLK =
FCLK/(CPS+1) bits
0111b
sampling window = (ACQ_PS + 1)*(1/ADCCLK)

Note: ADCCLK can be a maximum of 12.5 MHz. See device data sheet
for more information.

6-4 TMS320C28x DSP Workshop - Analog-to-Digital Converter

 Analog-to-Digital Converter

Analog-to-Digital Converter Registers

Analog-to-Digital Converter Registers
AdcRegs.name (lab file: Adc.c)
Register Description
ADCTRL1 ADC Control Register 1
ADCTRL2 ADC Control Register 2
ADCTRL3 ADC Control Register 3
ADCMAXCONV ADC Maximum Conversion Channels Register
ADCCHSELSEQ1 ADC Channel Select Sequencing Control Register 1
ADCCHSELSEQ2 ADC Channel Select Sequencing Control Register 2
ADCCHSELSEQ3 ADC Channel Select Sequencing Control Register 3
ADCCHSELSEQ4 ADC Channel Select Sequencing Control Register 4
ADCASEQSR ADC Autosequence Status Register
ADCRESULT0 ADC Conversion Result Buffer Register 0
ADCRESULT1 ADC Conversion Result Buffer Register 1
ADCRESULT2 ADC Conversion Result Buffer Register 2
: : : : : : :
ADCRESULT14 ADC Conversion Result Buffer Register 14
ADCRESULT15 ADC Conversion Result Buffer Register 15
ADCREFSEL ADC Reference Select Register
ADCOFFTRIM ADC Offset Trim Register
ADCST ADC Status and Flag Register

TMS320C28x DSP Workshop - Analog-to-Digital Converter 6-5

Analog-to-Digital Converter

ADC Control Register 1

AdcRegs.ADCTRL1 (lab file: Adc.c)

Upper Register:

ADC Module Reset Acquisition Time Prescale (S/H)

0 = no effect Value = (binary+1)
1 = reset (set back to 0 * Time dependent on the “Conversion
by ADC logic) Clock Prescale” bit (Bit 7 “CPS”)

15 14 13 - 12 11 - 8 7
reserved RESET SUSMOD ACQ_PS CPS

Emulation Suspend Mode Conversion Prescale

00 = [Mode 0] free run (do not stop) 0: ADCCLK = FCLK / 1
01 = [Mode 1] stop after current sequence 1: ADCCLK = FCLK / 2
10 = [Mode 2] stop after current conversion
11 = [Mode 3] stop immediately

ADC Control Register 1

AdcRegs.ADCTRL1 (lab file: Adc.c)

Lower Register:
Continuous Run Sequencer Mode
0 = stops after reaching 0 = dual mode
end of sequence 1 = cascaded mode
1 = continuous (starts all over
again from “initial state”)

6 5 4 3-0
CONT_RUN SEQ_OVRD SEQ_CASC reserved

Sequencer Override
(continuous run mode)
0 = sequencer pointer resets to “initial state”
at end of MAX_CONVn
1 = sequencer pointer resets to “initial state”
after “end state”

6-6 TMS320C28x DSP Workshop - Analog-to-Digital Converter

 Analog-to-Digital Converter

ADC Control Register 2

AdcRegs.ADCTRL2 (lab file: Adc.c)

Upper Register:
ePWM SOC A
ePWM SOC B SEQ1 Mask Bit
Start Conversion (SEQ1) 0 = cannot be started
(cascaded mode only) 0 = clear pending SOC trigger
0 = no action by ePWM trigger
1 = software trigger-start SEQ1 1 = can be started
1 = start by ePWM
signal by ePWM trigger

15 14 13 12 11 10 9 8
ePWM_SOCB RST_SEQ1 SOC_SEQ1 reserved INT_ENA INT_MOD reserved ePWM_SOCA
_SEQ _SEQ1 _SEQ1 _SEQ1

Reset SEQ1 Interrupt Enable (SEQ1) Interrupt Mode (SEQ1)

0 = no action 0 = interrupt disable 0 = interrupt every EOS
1 = immediate reset 1 = interrupt enable 1 = interrupt every other EOS
SEQ1 to “initial state”

ADC Control Register 2

AdcRegs.ADCTRL2 (lab file: Adc.c)

Lower Register:
ePWM SOC B
SEQ2 Mask Bit
Start Conversion (SEQ2) 0 = cannot be started
External SOC (SEQ1) (dual-sequencer mode only)
0 = no action by ePWM trigger
0 = clear pending SOC trigger
1 = start by signal from 1 = can be started
1 = software trigger-start SEQ2
ADCSOC pin by ePWM trigger

7 6 5 4 3 2 1 0
EXT_SOC RST_SEQ2 SOC_SEQ2 reserved INT_ENA INT_MOD reserved ePWM_SOCB
_SEQ1 _SEQ2 _SEQ2 _SEQ2

Reset SEQ2 Interrupt Enable (SEQ2) Interrupt Mode (SEQ2)

0 = no action 0 = interrupt disable 0 = interrupt every EOS
1 = immediate reset 1 = interrupt enable 1 = interrupt every other EOS
SEQ2 to “initial state”

TMS320C28x DSP Workshop - Analog-to-Digital Converter 6-7

Analog-to-Digital Converter

ADC Control Register 3

AdcRegs.ADCTRL3 (lab file: Adc.c)

ADC Reference ADC Bandgap ADC Power Down

Power Down Power Down (except Bandgap & Ref.)
0 = powered down 0 = powered down 0 = powered down
1 = powered up 1 = powered up 1 = powered up

15 - 8 7 6 5 4-1 0
reserved ADCBGRFDN1 ADCBGRFDN0 ADCPWDN ADCCLKPS SMODE_SEL

ADC Clock Prescale Sampling Mode Select

0: FCLK = HSPCLK 0 = sequential sampling mode
1 to F: FCLK = HSPCLK / (2*ADCCLKPS) 1 = simultaneous sampling mode

Maximum Conversion Channels Register

AdcRegs.ADCMAXCONV (lab file: Adc.c)

♦ Bit fields define the maximum number of autoconversions (binary+1)

Cascaded Mode

15-7 6 5 4 3 2 1 0
MAX_ MAX_ MAX_ MAX_ MAX_ MAX_ MAX_
reserved
CONV 2_2 CONV 2_1 CONV 2_0 CONV 1_3 CONV 1_2 CONV 1_1 CONV 1_0

SEQ2 SEQ1
Dual Mode

♦ Autoconversion session always starts with the “initial state”

and continues sequentially until the “end state”, if allowed

SEQ1 SEQ2 Cascaded

Initial state CONV00 CONV08 CONV00
End state CONV07 CONV15 CONV15

6-8 TMS320C28x DSP Workshop - Analog-to-Digital Converter

 Analog-to-Digital Converter

ADC Input Channel Select Sequencing

Control Register
AdcRegs.ADCCHSELSEQx.bit.CONVyy = (lab file: Adc.c)

Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0

ADCCHSELSEQ1 CONV03 CONV02 CONV01 CONV00

Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0

ADCCHSELSEQ2 CONV07 CONV06 CONV05 CONV04

Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0

ADCCHSELSEQ3 CONV11 CONV10 CONV09 CONV08

Bits 15-12 Bits 11-8 Bits 7-4 Bits 3-0

ADCCHSELSEQ4 CONV15 CONV14 CONV13 CONV12

TMS320C28x DSP Workshop - Analog-to-Digital Converter 6-9

Analog-to-Digital Converter

Example – Sequencer “Start/Stop” Operation

Example - Sequencer “Start/Stop”
Operation
ePWM
Time Base
Couter

ePWM
Output

I1, I2, I3 V1, V2, V3 I1, I2, I3 V1, V2, V3

System Requirements:
•Three autoconversions (I1, I2, I3) off trigger 1 (CTR = 0)
•Three autoconversions (V1, V2, V3) off trigger 2 (CTR = PRD)

ePWM and SEQ1 are used for this example with sequential sampling mode

Example - Sequencer “Start/Stop”

Operation (Continued)
• MAX_CONV1 is set to 2 and Channel Select Sequencing Control Registers are set to:
Bits → 15-12 11-8 7-4 3-0
V1 I3 I2 I1 ADCCHSELSEQ1
x x V3 V2 ADCCHSELSEQ2

• Once reset and initialized, SEQ1 waits for a trigger

• First trigger three conversions performed: CONV00 (I1), CONV01 (I2), CONV02 (I3)
• MAX_CONV1 value is reset to 2 (unless changed by software)
• SEQ1 waits for second trigger
• Second trigger three conversions performed: CONV03 (V1), CONV04 (V2), CONV05 (V3)
• End of second auto conversion session, ADC Results registers have the following values:

RESULT0 I1 RESULT3 V1
RESULT1 I2 RESULT4 V2
RESULT2 I3 RESULT5 V3

→ User can reset SEQ1 by software to state CONV00 and repeat same trigger 1, 2 session
• SEQ1 keeps “waiting” at current state for another trigger

6 - 10 TMS320C28x DSP Workshop - Analog-to-Digital Converter

 Analog-to-Digital Converter

ADC Conversion Result Buffer Register

ADC Conversion Result Buffer Register
AdcRegs.ADCRESULT0 through AdcRegs.ADCRESULT15
(lab file: Adc.c)
(Total of 16 Registers)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MSB LSB

With analog input 0V to 3V, we have:

analog volts converted value RESULTx
3.0 FFFh 1111|1111|1111|0000
1.5 7FFh 0111|1111|1111|0000
0.00073 1h 0000|0000|0001|0000
0 0h 0000|0000|0000|0000

TMS320C28x DSP Workshop - Analog-to-Digital Converter 6 - 11

Analog-to-Digital Converter

Numerical Format
How do we Read the Result?
Integer format
x x x x x x x x x x x x 0 0 0 0 RESULTx

0 0 0 0 x x x x x x x x x x x x Data Mem

Example: read RESULT0 register

#include “DSP280x_Device.h”

void main(void)
{
Uint16 value; // unsigned

value = AdcRegs.ADCRESULT0 >> 4;

}

Note: The ADC result registers are dual mapped. The result registers that are located
in PF2 (have 2 wait states) are left justified, and the result registers located
in PF0 (have 0 wait states) are right justified.

What About Signed Input Voltages?

Example: -1.5 V ≤ Vin ≤ +1.5 V R
R
Vin R C28x
- R
+ -
1.5V + Input
R Ch. x

1) Add 1.5 volts to analog input:

ADCLO
2) Subtract “1.5” from digital result:
GND
#include
#include “DSP280x_Device.h”
“DSP280x_Device.h”
#define
#define offset
offset 0x07FF
0x07FF

void
void main(void)
main(void)
{{
int16
int16 value;
value; //
// signed
signed

value
value == (AdcRegs.ADCRESULT0
(AdcRegs.ADCRESULT0 >>
>> 4)
4) –– offset;
offset;
}}

6 - 12 TMS320C28x DSP Workshop - Analog-to-Digital Converter

 Lab 6: Analog-to-Digital Converter

Lab 6: Analog-to-Digital Converter

¾ Objective

The objective of this lab is to apply the techniques discussed in module 6 and to become familiar
with the programming and operation of the on-chip analog-to-digital converter. The DSP will be
setup to sample a single ADC input channel at a prescribed sampling rate and store the
conversion result in a buffer in the DSP memory. This buffer will operate in a circular fashion,
such that new conversion data continuously overwrites older results in the buffer.

Lab 6: Analog-to-Digital Converter (1 of 2)

Sampling
+3.3 V Toggle
GND (GPIO32) (GPIO33)
data
ADC memory
CPU copies result
connector
to buffer during
wire RESULT0

pointer rewind
ADC ISR

ADCINA0

...
ePWM2 triggering
ADC on period match
using SOC A trigger
every 20 µs (50 kHz) View ADC
buffer PWM
Samples

Code Composer
Studio

ePWM2

Recall that there are three basic ways to initiate an ADC start of conversion (SOC):
1. Using software
a. SOC_SEQ1/SOC_SEQ2 bit in ADCTRL2 causes an SOC upon completion of the current
conversion (if the ADC is currently idle, an SOC occurs immediately)
2. Automatically triggered on user selectable ePWM conditions
a. ePWM underflow (CTR = 0)
b. ePWM period match (CTR = PRD)
c. ePWM compare match (CTRU/D = CMPA/B)
3. Externally triggered using a pin
a. ADCSOC pin

One or more of these methods may be applicable to a particular application. In this lab, we will
be using the ADC for data acquisition. Therefore, one of the ePWMs (ePWM2) will be
configured to automatically trigger an SOC A at the desired sampling rate (SOC method 2b
above). The ADC end-of-conversion interrupt will be used to prompt the CPU to copy the results
of the ADC conversion into a results buffer in memory. This buffer pointer will be managed in a
circular fashion, such that new conversion results will continuously overwrite older conversion
results in the buffer. In order to generate an interesting input signal, the code also alternately
toggles a GPIO pin (GPIO33) high and low in the ADC interrupt service routine. The ADC ISR

TMS320C28x DSP Workshop - Analog-to-Digital Converter 6 - 13

Lab 6: Analog-to-Digital Converter

will also toggle LED DS2 on the eZdsp™ as a visual indication that the ISR is running. This pin
will be connected to the ADC input pin, and sampled. After taking some data, Code Composer
Studio will be used to plot the results. A flow chart of the code is shown in the following slide.

Lab 6: Code Flow Diagram (2 of 2)

Start CPU Initialization

• watchdog disable
• SCSR register ADC interrupt
• core interrupts
• shared pins
• GPIO setup ADC ISR
• context save
• read the ADC result
ADC Initialization Main Loop • write to result buffer
• convert channel A0 on • adjust the buffer pointer
ePWM2 period match loop: B loop • toggle the GPIO pin
• send interrupt on • context restore
every conversion • re-enable interrupts
• setup a results buffer • return
in memory

ePWM2 Initialization return

• clear counter
• set period register
• set to trigger ADC on
period match
• set the clock prescaler
• enable the timer

Notes
• Program performs conversion on ADC channel A0 (ADCINA0 pin)
• ADC conversion is set at a 50kHz sampling rate
• ePWM2 is triggering the ADC on period match using SOC A trigger
• Data is continuously stored in a circular buffer
• GPIO33 pin is also toggled in the ADC ISR
• ADC ISR will also toggle the eZdsp™ LED DS2 as a visual indication that it is running

¾ Procedure

Project File

Note: LAB6 files have been provided as a starting point for the lab and need to be
completed. DO NOT copy files from a previous lab.

1. A project named Lab6.pjt has been created for this lab. Open the project by clicking
on Project Æ Open… and look in C:\C28x\Labs\Lab6. All Build Options
have been configured like the previous lab. The files used in this lab are:

6 - 14 TMS320C28x DSP Workshop - Analog-to-Digital Converter

 Lab 6: Analog-to-Digital Converter

Main_6.c Labcfg.cmd
Lab.cdb DSP280x_Headers_BIOS.cmd
User_5_6_7.cmd CodeStartBranch.asm
SysCtrl.c Gpio.c
DSP280x_GlobalVariableDefs.c PieCtrl_5_6_7_8_9.c
DefaultIsr_5_6_7.c Adc.c
EPwm_6.c DelayUs.asm

Setup ADC Initialization and Enable Core/PIE Interrupts

2. In Main_6.c add code to call InitAdc() and InitEPwm() functions. The
InitEPwm() function is used to configure ePWM2 to trigger the ADC at a 50 kHz rate.
Details about the ePWM and control peripherals will be discussed in the next module.
3. Edit Adc.c to implement the ADC initialization as described above in the objective for
the lab by configuring the following registers: ADCTRL1, ADCTRL2, ADCMAXCONV
and ADCCHSELSEQ1. (Set ADC for cascaded sequencer mode, CPS = CLK/1, and
acquisition time prescale = 8 * (1/ADCCLK), ePWM2 triggering the ADC on period
match using SOC A trigger).

4. Using the “PIE Interrupt Assignment Table” find the location for the
ADC interrupt, “ADCINT” and fill in the following information:

PIE group #: # within group:

This information will be used in the next step.

5. Modify the end of Adc.c to do the following:

enable the "ADCINT" interrupt in the PIE (Hint: use the PieCtrlRegs structure)
enable core INT1 (IER register)
6. Open and inspect DefaultIsr_5_6_7.c. This file contains the ADC interrupt
service routine.

7. Modify the configuration file lab.cdb to setup the PIE vector for the ADC interrupt.
Click on the plus sign (+) to the left of Scheduling and again on the plus sign (+) to
the left of HWI – Hardware Interrupt Service Routine Manager. Click
the plus sign (+) to the left of PIE INTERRUPTS. Locate the interrupt location for the
ADC (use the information from step #4). Right click, select Properties, and type
_ADCINT_ISR (with a leading underscore) in the function field. Click OK and save all
updates.

Build and Load

8. Save all changes to the files and click the “Build” button.

9. Reset the DSP, and then “Go Main”.

TMS320C28x DSP Workshop - Analog-to-Digital Converter 6 - 15

Lab 6: Analog-to-Digital Converter

Run the Code

10. In Main_6.c place the cursor in the “main loop” section, right click on the
mouse key and select Run To Cursor.

11. Open a memory window to view some of the contents of the ADC results buffer. The
address label for the ADC results buffer is AdcBuf.

Note: Exercise care when connecting any wires, as the power to the eZdsp™ is on, and we
do not want to damage the eZdsp™! Details of pin assignments can be found in
Appendix A.

12. Using a connector wire provided, connect the ADCINA0 (pin # P9-2) to “GND” (pin #
P9-1) on the eZdsp™. Then run the code again, and halt it after a few seconds. Verify
that the ADC results buffer contains the expected value of 0x0000.

13. Adjust the connector wire to connect the ADCINA0 (pin # P9-2) to “+3.3V” (pin # P8-
36) on the eZdsp™. (Note: pin # P8-36 / GPIO32 has been set to “1” in Gpio.c). Then
run the code again, and halt it after a few seconds. Verify that the ADC results buffer
contains the expected value of 0x0FFF.

14. Adjust the connector wire to connect the ADCINA0 (pin # P9-2) to GPIO33 (pin # P8-
38) on the eZdsp™. Then run the code again, and halt it after a few seconds. Examine
the contents of the ADC results buffer (the contents should be alternating 0x0000 and
0x0FFF values). Are the contents what you expected?

15. Open and setup a graph to plot a 50-point window of the ADC results buffer.
Click: View Æ Graph Æ Time/Frequency… and set the following values:

Start Address AdcBuf

Acquisition Buffer Size 50

Display Data Size 50

DSP Data Type 16-bit unsigned integer

Sampling Rate (Hz) 50000

Time Display Unit μs

Select OK to save the graph options.

16. Recall that the code toggled the GPIO33 pin alternately high and low. (Also, the ADC
ISR is toggling the LED DS2 on the eZdsp™ as a visual indication that the ISR is
running). If you had an oscilloscope available to display GPIO33, you would expect to
see a square-wave. Why does Code Composer Studio plot resemble a triangle wave?
What is the signal processing term for what is happening here?

6 - 16 TMS320C28x DSP Workshop - Analog-to-Digital Converter

 Lab 6: Analog-to-Digital Converter

17. Recall that the program toggled the GPIO33 pin at a 50 kHz rate. Therefore, a complete
cycle (toggle high, then toggle low) occurs at half this rate, or 25 kHz. We therefore
expect the period of the waveform to be 40 μs. Confirm this by measuring the period of
the triangle wave using the graph (you may want to enlarge the graph window using the
mouse). The measurement is best done with the mouse. The lower left-hand corner of
the graph window will display the X and Y axis values. Subtract the X-axis values taken
over a complete waveform period.

Using Real-time Emulation

Real-time emulation is a special emulation feature that offers two valuable capabilities:

1. Windows within Code Composer Studio can be updated at up to a 10 Hz rate while the
DSP is running. This not only allows graphs and watch windows to update, but also
allows the user to change values in watch or memory windows, and have those
changes affect the DSP behavior. This is very useful when tuning control law
parameters on-the-fly, for example.

2. It allows the user to halt the DSP and step through foreground tasks, while specified
interrupts continue to get serviced in the background. This is useful when debugging
portions of a realtime system (e.g., serial port receive code) while keeping critical
parts of your system operating (e.g., commutation and current loops in motor control).

We will only be utilizing capability #1 above during the workshop. Capability #2 is a

particularly advanced feature, and will not be covered in the workshop.

18. Reset the DSP, and then enable real-time mode by selecting:

Debug Æ Real-time Mode

19. A message box will appear. Select YES to enable debug events. This will set bit 1
(DGBM bit) of status register 1 (ST1) to a “0”. The DGBM is the debug enable mask bit.
When the DGBM bit is set to “0”, memory and register values can be passed to the host
processor for updating the debugger windows.

20. The memory and graph windows displaying AdcBuf should still be open. The connector
wire between ADCINA0 (pin # P9-2) and GPIO33 (pin # P8-38) should still be
connected. In real-time mode, we would like to have our window continuously refresh.
Click:

View Æ Real-time Refresh Options…

and check “Global Continuous Refresh”. Alternately, we could have right

clicked on each window individually and selected “Continuous Refresh”.

TMS320C28x DSP Workshop - Analog-to-Digital Converter 6 - 17

Lab 6: Analog-to-Digital Converter

Note: “Global Continuous Refresh” causes all open windows to refresh at the
refresh rate. This can be problematic when a large number of windows are open, as
bandwidth over the emulation link is limited. Updating too many windows can cause the
refresh frequency to bog down. In that case, either close some windows, or disable
global refresh and selectively enable “Continuous Refresh” for individual
windows of interest instead.

21. Run the code and watch the windows update in real-time mode. Are the values updating
as expected?

22. Fully halting the DSP when in real-time mode is a two-step process. First, halt the
processor with Debug Æ Halt. Then uncheck the “Real-time mode” to take
the DSP out of real-time mode.

23. So far, we have seen data flowing from the DSP to the debugger in realtime. In this step,
we will flow data from the debugger to the DSP.
• Open and inspect DefaultIsr_5_6_7.c. Notice that the global variable
DEBUG_TOGGLE is used to control the toggling of the GPIO33 pin. This is the pin
being read with the ADC.
• Highlight DEBUG_TOGGLE with the mouse, right click and select “Add to
Watch Window”. The global variable DEBUG_TOGGLE should now be in the
watch window with a value of “1”.
• Run the code in real-time mode and change the value to “0”. Are the results shown
in the memory and graph window as expected? Change the value back to “1”. As
you can see, we are modifying data memory contents while the processor is running
in real-time (i.e., we are not halting the DSP nor interfering with its operation in any
way)! When done, fully halt the DSP.
24. Code Composer Studio includes GEL (General Extension Language) functions which
automate entering and exiting real-time mode. Four functions are available:
• Run_Realtime_with_Reset (reset DSP, enter real-time mode, run DSP)
• Run_Realtime_with_Restart (restart DSP, enter real-time mode, run DSP)
• Full_Halt (exit real-time mode, halt DSP)
• Full_Halt_with_Reset (exit real-time mode, halt DSP, reset DSP)
These GEL functions can be executed by clicking:
GEL Æ Realtime Emulation Control Æ GEL Function
In the remaining lab exercises we will be using the above GEL functions to run and halt
the code in real-time mode. If you would like, try repeating the previous step using the
following GEL functions:
GEL Æ Realtime Emulation Control Æ Run_Realtime_with_Reset
GEL Æ Realtime Emulation Control Æ Full_Halt

End of Exercise

6 - 18 TMS320C28x DSP Workshop - Analog-to-Digital Converter

 Control Peripherals

Introduction
This module explains how to generate PWM waveforms using the ePWM unit. Also, the eCAP
unit, and eQEP unit will be discussed.

Learning Objectives
Learning Objectives

‹ Pulse Width Modulation (PWM) review

‹ Generate PWM waveform with the Pulse
Width Modulator Module (ePWM)
‹ Use the Capture Module to measure the
width of a waveform (eCAP)
‹ Explain function of Quadrature Encoder
Pulse Module (eQEP)

Note: Up to 6 ePWM modules, 4 eCAP modules, and 2 eQEP modules are

available on the F280x devices. The lower case “e” used with
the module name refers to “enhanced”. For simplicity, the “e” has
been dropped in this slide set.

TMS320C28x DSP Workshop - Control Peripherals 7-1

Module Topics

Module Topics

Control Peripherals................................................................................................................................... 7-1

Module Topics......................................................................................................................................... 7-2

PWM Review........................................................................................................................................... 7-3
ePWM...................................................................................................................................................... 7-5
ePWM Time-Base Module ................................................................................................................. 7-5
ePWM Compare Module.................................................................................................................... 7-9
ePWM Action Qualifier Module .......................................................................................................7-11
ePWM Dead-Band Module ...............................................................................................................7-16
ePWM PWM Chopper Module .........................................................................................................7-20
ePWM Trip-Zone Module .................................................................................................................7-22
ePWM Event-Trigger Module...........................................................................................................7-26
Hi-Resolution PWM (HRPWM) .......................................................................................................7-28
Asymmetric and Symmetric Waveform Generation using the ePWM ....................................................7-29
ePWM Exercise .................................................................................................................................7-30
eCAP ......................................................................................................................................................7-31
eQEP......................................................................................................................................................7-37
Lab 7: Control Peripherals....................................................................................................................7-39
ePWM Exercise Solution........................................................................................................................7-44

7-2 TMS320C28x DSP Workshop - Control Peripherals

 PWM Review

PWM Review
What is Pulse Width Modulation?

‹ PWM is a scheme to represent a

signal as a sequence of pulses
Š fixed carrier frequency
Š fixed pulse amplitude
Š pulse width proportional to
instantaneous signal amplitude
Š PWM energy ≈ original signal energy

t t
T
Original Signal PWM representation

Pulse width modulation (PWM) is a method for representing an analog signal with a digital
approximation. The PWM signal consists of a sequence of variable width, constant amplitude
pulses which contain the same total energy as the original analog signal. This property is
valuable in digital motor control as sinusoidal current (energy) can be delivered to the motor
using PWM signals applied to the power converter. Although energy is input to the motor in
discrete packets, the mechanical inertia of the rotor acts as a smoothing filter. Dynamic motor
motion is therefore similar to having applied the sinusoidal currents directly.

TMS320C28x DSP Workshop - Control Peripherals 7-3

PWM Review

Why use PWM with Power

Switching Devices?
‹ Desired output currents or voltages are known
‹ Power switching devices are transistors
Š Difficult to control in proportional region
Š Easy to control in saturated region
‹ PWM is a digital signal ⇒ easy for DSP to output

DC Supply DC Supply

? PWM
Desired PWM approx.
signal to of desired
system signal
Unknown Gate Signal Gate Signal Known with PWM

7-4 TMS320C28x DSP Workshop - Control Peripherals

 ePWM

ePWM
ePWM Block Diagram

CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed EPWMxB
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0
PCCTL . 10 - 0 TZx
TZSEL . 15 - 0

Note: x = 1, 2, 3, 4, 5, or 6

ePWM Time-Base Module

ePWM Time-Base Module

CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed EPWMxB
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0
PCCTL . 10 - 0 TZx
TZSEL . 15 - 0

Note: x = 1, 2, 3, 4, 5, or 6

TMS320C28x DSP Workshop - Control Peripherals 7-5

ePWM

ePWM Time-Base Count Modes

TBCTR

TBPRD
Asymmetrical
Waveform

Count Up Mode
TBCTR

TBPRD
Asymmetrical
Waveform

Count Down Mode

TBCTR

TBPRD

Symmetrical
Waveform

Count Up and Down Mode

ePWM Phase Synchronization

Ext SyncIn
(optional)

Phase
φ=0°
En
o o .
SyncIn
EPWM1A
o
CTR=zero o
CTR=CMPB o o EPWM1B
X o
SyncOut

Phase
φ=120°
En
o o .
SyncIn
EPWM2A φ=120°
o
CTR=zero o
CTR=CMPB o o EPWM2B
X o
SyncOut

Phase
φ=240°
En
o o .
SyncIn
EPWM3A
φ=120°

o
CTR=zero o
CTR=CMPB o o EPWM3B
X o
SyncOut φ=240°

7-6 TMS320C28x DSP Workshop - Control Peripherals

 ePWM

ePWM Time-Base Module Registers

Name Description Structure

TBCTL Time-Base Control EPwmxRegs.TBCTL.all =
TBSTS Time-Base Status EPwmxRegs.TBSTS.all =
TBPHS Time-Base Phase EPwmxRegs.TBPHS =
TBCTR Time-Base Counter EPwmxRegs.TBCTR =
TBPRD Time-Base Period EPwmxRegs.TBPRD =

ePWM Time-Base Control Register

EPwmxRegs.TBCTL.bit.yyyy =

Upper Register:

Phase Direction TBCLK = SYSCLKOUT / (HSPCLKDIV * CLKDIV)

0 = count down after sync
1 = count up after sync

15 - 14 13 12 - 10 9-7
FREE_SOFT PHSDIR CLKDIV HSPCLKDIV

Emulation Halt Behavior TB Clock Prescale High Speed TB

00 = stop after next CTR inc/dec 000 = /1 (default) Clock Prescale
01 = stop when: 001 = /2 000 = /1
Up Mode – CTR = PRD 010 = /4 001 = /2 (default)
Down Mode – CTR = 0 011 = /8 010 = /4
Up/Down Mode – CTR = 0 100 = /16 011 = /6
1x = free run (do not stop) 101 = /32 100 = /8
110 = /64 101 = /10
111 = /128 110 = /12
111 = /14
(HSPCLKDIV emulates HSPCLK in F281x device)

TMS320C28x DSP Workshop - Control Peripherals 7-7

ePWM

ePWM Time-Base Control Register

EPwmxRegs.TBCTL.bit.yyyy =

Lower Register:
Counter Mode
Software Force Sync Pulse 00 = count up
01 = count down
0 = no action 10 = count up and down
1 = force one-time sync 11 = stop – freeze (default)

6 5-4 3 2 1-0
SWFSYNC SYNCOSEL PRDLD PHSEN CTRMODE

Sync Output Select Period Shadow Load Phase Reg. Enable

(source of EPWMxSYNC0 signal) 0 = load on CTR = 0 0 = disable
00 = EPWMxSYNCI 1 = load immediately 1 = CTR = TBPHS on
01 = CTR = 0 EPWMxSYNCI signal
10 = CTR = CMPB
11 = disable SyncOut

ePWM Time-Base Status Register

EPwmxRegs.TBSTS.bit.yyyy =

Counter Max Latched Counter Direction

0 = max value not reached 0 = CTR counting down
1 = CTR = 0xFFFF (write 1 to clear) 1 = CTR counting up

15 - 3 2 1 0
reserved CTRMAX SYNCI CTRDIR

External Input Sync Latched

0 = no sync event occurred
1 = sync has occurred (write 1 to clear)

7-8 TMS320C28x DSP Workshop - Control Peripherals

 ePWM

ePWM Compare Module

ePWM Compare Module

CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCI
Period
Register EPWMxA
PWM Trip
Shadowed EPWMxB
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0
PCCTL . 10 - 0 TZx
TZSEL . 15 - 0

Note: x = 1, 2, 3, 4, 5, or 6

ePWM Compare Event Waveforms

TBCTR . = compare events are fed to the Action Qualifier Module

.. .. ..
TBPRD
CMPA Asymmetrical
CMPB Waveform

Count Up Mode
TBCTR

TBPRD
CMPA
CMPB
.. .. .. Asymmetrical
Waveform

Count Down Mode

TBCTR

.. .. .. ..
TBPRD
CMPA Symmetrical
CMPB Waveform

Count Up and Down Mode

TMS320C28x DSP Workshop - Control Peripherals 7-9

ePWM

ePWM Compare Module Registers

Name Description Structure

CMPCTL Compare Control EPwmxRegs.CMPCTL.all =
CMPA Compare A EPwmxRegs.CMPA =
CMPB Compare B EPwmxRegs.CMPB =

ePWM Compare Control Register

EPwmxRegs.CMPCTL.bit.yyyy =

Upper Register:

15 - 10 9 8 7
reserved SHDWBFULL SHDWAFULL reserved

CMPB / A Shadow Full Flag

(bit automatically clears on load)
0 = shadow not full
1 = shadow full

7 - 10 TMS320C28x DSP Workshop - Control Peripherals

 ePWM

ePWM Compare Control Register

EPwmxRegs.CMPCTL.bit.yyyy =

Lower Register: Active CMPB and CMPA Shadow Load Mode

00 = load on CTR = 0
01 = load on CTR = PRD
10 = load on either CTR = 0 or CTR = PRD
11 = freeze (no load possible)

6 5 4 3-2 1-0
SHDWBMODE reserved SHDWAMODE LOADBMODE LOADAMODE

CMPB and CMPA Operating Mode

0 = shadow mode; double buffer with
writes to shadow register
1 = immediate mode; only active register
used with writes directly to active register

ePWM Action Qualifier Module

ePWM Action Qualifier Module

CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed EPWMxB
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0
PCCTL . 10 - 0 TZx
TZSEL . 15 - 0

Note: x = 1, 2, 3, 4, 5, or 6

TMS320C28x DSP Workshop - Control Peripherals 7 - 11

ePWM

ePWM Action Qualifier Actions

for EPWMA and EPWMB

Time-Base Counter equals: EPWM

S/W Output
Force Actions
Zero CMPA CMPB TBPRD

SW Z CA CB P Do Nothing
X X X X X

SW Z CA CB P Clear Low
↓ ↓ ↓ ↓ ↓

SW Z CA CB P Set High
↑ ↑ ↑ ↑ ↑

SW Z CA CB P
Toggle
T T T T T

ePWM Count Up Asymmetric Waveform

with Independent Modulation on EPWMA / B

TBCTR

TBPRD
. .
. .
Z P CB CA Z P CB CA Z P
↑ X X ↓ ↑ X X ↓ ↑ X

EPWMA

Z P CB CA Z P CB CA Z P
↑ X ↓ X ↑ X ↓ X ↑ X

EPWMB

7 - 12 TMS320C28x DSP Workshop - Control Peripherals

 ePWM

ePWM Count Up Asymmetric Waveform

with Independent Modulation on EPWMA

TBCTR

TBPRD
. .
. .
CA CB CA CB
↑ ↓ ↑ ↓

EPWMA

Z Z Z
T T T

EPWMB

ePWM Count Up-Down Symmetric

Waveform
with Independent Modulation on EPWMA / B
TBCTR

TBPRD
. . . .
. . . .
CA CA CA CA
↑ ↓ ↑ ↓

EPWMA

CB CB CB CB
↑ ↓ ↑ ↓

EPWMB

TMS320C28x DSP Workshop - Control Peripherals 7 - 13

ePWM

ePWM Count Up-Down Symmetric

Waveform
with Independent Modulation on EPWMA
TBCTR

TBPRD
. .
. .
CA CB CA CB
↑ ↓ ↑ ↓

EPWMA

Z P Z P
↓ ↑ ↓ ↑

EPWMB

ePWM Action Qualifier Module Registers

Name Description Structure

AQCTLA AQ Control Output A EPwmxRegs.AQCTLA.all =
AQCTLB AQ Control Output B EPwmxRegs.AQCTLB.all =
AQSFRC AQ S/W Force EPwmxRegs.AQSFRC.all =
AQCSFRC AQ Cont. S/W Force EPwmxRegs.AQCSFRC.all =

7 - 14 TMS320C28x DSP Workshop - Control Peripherals

 ePWM

ePWM Action Qualifier Control Register

EPwmxRegs.AQCTLz.bit.yyyy =
(z = A or B)

Action when Action when

CTR = CMPB CTR = CMPA Action when
on UP Count on UP Count CTR = 0

15 - 12 11 - 10 9-8 7-6 5-4 3-2 1-0

reserved CBD CBU CAD CAU PRD ZRO

Action when Action when Action when

CTR = CMPB CTR = CMPA CTR = PRD
on DOWN Count on DOWN Count

00 = do nothing (action disabled)

01 = clear (low)
10 = set (high)
11 = toggle (low → high; high → low)

ePWM Action Qualifier S/W Force

Register
EPwmxRegs.AQSFRC.bit.yyyy =

One-Time S/W Force on Output B / A

0 = no action
1 = single s/w force event

15 - 8 7-6 5 4-3 2 1-0

reserved RLDCSF OTSFB ACTSFB OTSFA ACTSFA

Shadow Reload Options Action on One-Time S/W Force B / A

00 = load on event CTR = 0 00 = do nothing (action disabled)
01 = load on event CTR = PRD 01 = clear (low)
10 = load on event CTR = 0 or CTR = PRD 10 = set (high)
11 = load immediately (from active reg.) 11 = toggle (low → high; high → low)

TMS320C28x DSP Workshop - Control Peripherals 7 - 15

ePWM

ePWM AQ Continuous S/W Force

Register
EPwmxRegs.AQCSFRC.bit.yyyy =

15 - 4 3-2 1-0
reserved CSFB CSFA

Continuous S/W Force on Output B / A

00 = forcing disabled
01 = force continuous low on output
10 = force continuous high on output
11 = forcing disabled

ePWM Dead-Band Module

ePWM Dead-Band Module

CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed EPWMxB
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0
PCCTL . 10 - 0 TZx
TZSEL . 15 - 0

Note: x = 1, 2, 3, 4, 5, or 6

7 - 16 TMS320C28x DSP Workshop - Control Peripherals

 ePWM

Motivation for Dead-Band

supply rail

Gate Signals are to motor phase

Complementary PWM

♦ Transistor gates turn on faster than they shut off

♦ Short circuit if both gates are on at same time!

Dead-band control provides a convenient means of combating current shoot-through problems in

a power converter. Shoot-through occurs when both the upper and lower gates in the same phase
of a power converter are open simultaneously. This condition shorts the power supply and results
in a large current draw. Shoot-through problems occur because transistors open faster than they
close, and because high-side and low-side power converter gates are typically switched in a
complimentary fashion. Although the duration of the shoot-through current path is finite during
PWM cycling, (i.e. the closing gate will eventually shut), even brief periods of a short circuit
condition can produce excessive heating and over stress in the power converter and power supply.

TMS320C28x DSP Workshop - Control Peripherals 7 - 17

ePWM

ePWM Dead-Band Module Block Diagram

PWMxA

Rising

.
0

.
Edge
°
0 S1 PWMxA
0 Delay ° S2 RED °
° ° S4
° °1
°1
In Out
(10-bit
° °1
counter)

Falling

.
Edge 0

. ° S3
0 Delay FED 1
° ° S5
° ° S0° PWMxB

°1
In Out
(10-bit
° °1 °0
counter)
IN-MODE POLSEL OUT-MODE

PWMxB

Two basic approaches exist for controlling shoot-through: modify the transistors, or modify the
PWM gate signals controlling the transistors. In the first case, the opening time of the transistor
gate must be increased so that it (slightly) exceeds the closing time. One way to accomplish this
is by adding a cluster of passive components such as resistors and diodes in series with the
transistor gate, as shown in the next figure.

by-pass diode

PWM
signal
R

Shoot-through control via power circuit modification

The resistor acts to limit the current rise rate towards the gate during transistor opening, thus
increasing the opening time. When closing the transistor however, current flows unimpeded from
the gate via the by-pass diode and closing time is therefore not affected. While this passive
approach offers an inexpensive solution that is independent of the control microprocessor, it is
imprecise, the component parameters must be individually tailored to the power converter, and it
cannot adapt to changing system conditions.

The second approach to shoot-through control separates transitions on complimentary PWM

signals with a fixed period of time. This is called dead-band. While it is possible to perform
software implementation of dead-band, the C28x offers on-chip hardware for this purpose that
requires no additional CPU overhead. Compared to the passive approach, dead-band offers more

7 - 18 TMS320C28x DSP Workshop - Control Peripherals

 ePWM

precise control of gate timing requirements. In addition, the dead time is typically specified with
a single program variable that is easily changed for different power converters or adapted on-line.

ePWM Dead-Band Module Registers

Name Description Structure

DBCTL Dead-Band Control EPwmxRegs.DBCTL.all =
DBRED DB Rising Edge Delay EPwmxRegs.DBRED =
DBFED DB Falling Edge Delay EPwmxRegs.DBFED =

10-Bit Counter for Rising Edge and Falling Edge Delay

ePWM Dead Band Control Register

EPwmxRegs.DBCTL.bit.yyyy =

Polarity Select
00 = active high
01 = active low complementary (RED)
10 = active high complementary (FED)
11 = active low

15 - 6 5-4 3-2 1-0

reserved IN_MODE POLSEL OUT_MODE

In-Mode Control Out-Mode Control

00 = PWMxA is source for RED and FED 00 = disabled (DBM bypass)
01 = PWMxA is source for FED 01 = PWMxA = no delay
PWMxB is source for RED PWMxB = FED
10 = PWMxA is source for RED 10 = PWMxA = RED
PWMxB is source for FED PWMxB = no delay
11 = PWMxB is source for RED and FED 11 = RED and FED (DBM fully
enabled)

TMS320C28x DSP Workshop - Control Peripherals 7 - 19

ePWM

ePWM PWM Chopper Module

ePWM PWM Chopper Module

CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed EPWMxB
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0
PCCTL . 10 - 0 TZx
TZSEL . 15 - 0

Note: x = 1, 2, 3, 4, 5, or 6

Purpose of PWM Chopper

‹ Allows a high frequency carrier

signal to modulate the PWM
waveform generated by the Action
Qualifier and Dead-Band modules
‹ Used with pulse transformer-based
gate drivers to control power
switching elements

7 - 20 TMS320C28x DSP Workshop - Control Peripherals

 ePWM

ePWM Chopper Waveform

EPWMxA

EPWMxB

CHPFREQ

EPWMxA

EPWMxB

Programmable
Pulse Width
OSHT (OSHTWTH)

Sustaining
EPWMxA Pulses

With One-Shot Pulse on EPWMxA and/or EPWMxB

ePWM-Chopper Module Registers

Name Description Structure

PCCTL PWM-Chopper Control EPwmxRegs.PCCTL.all =

TMS320C28x DSP Workshop - Control Peripherals 7 - 21

ePWM

ePWM Chopper Control Register

EPwmxRegs.PCCTL.bit.yyyy =

Chopper Clk Duty Cycle Chopper Clk Freq.

000 = 1/8 (12.5%) 000 = sysclk/8 ÷ 1
001 = 2/8 (25.0%) 001 = sysclk/8 ÷ 2
010 = 3/8 (37.5%) 010 = sysclk/8 ÷ 3
011 = 4/8 (50.0%) 011 = sysclk/8 ÷ 4
100 = 5/8 (62.5%) 100 = sysclk/8 ÷ 5 Chopper Enable
101 = 6/8 (75.0%) 101 = sysclk/8 ÷ 6 0 = disable (bypass)
110 = 7/8 (87.5%) 110 = sysclk/8 ÷ 7 1 = enable
111 = reserved 111 = sysclk/8 ÷ 8

15 - 11 10 - 8 7-5 4-1 0
reserved CHPDUTY CHPFREQ OSHTWTH CHPEN

One-Shot Pulse Width

0000 = 1 x sysclk/8 wide 1000 = 9 x sysclk/8 wide
0001 = 2 x sysclk/8 wide 1001 = 10 x sysclk/8 wide
0010 = 3 x sysclk/8 wide 1010 = 11 x sysclk/8 wide
0011 = 4 x sysclk/8 wide 1011 = 12 x sysclk/8 wide
0100 = 5 x sysclk/8 wide 1100 = 13 x sysclk/8 wide
0101 = 6 x sysclk/8 wide 1101 = 14 x sysclk/8 wide
0110 = 7 x sysclk/8 wide 1110 = 15 x sysclk/8 wide
0111 = 8 x sysclk/8 wide 1111 = 16 x sysclk/8 wide

ePWM Trip-Zone Module

ePWM Trip-Zone Module

CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed EPWMxB
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0
PCCTL . 10 - 0 TZx
TZSEL . 15 - 0

Note: x = 1, 2, 3, 4, 5, or 6

7 - 22 TMS320C28x DSP Workshop - Control Peripherals

 ePWM

Trip-Zone Module Features

♦ Trip-Zone has a fast, clock independent logic path to high-impedance
the EPWMxA/B output pins
♦ Interrupt latency may not protect hardware when responding to over
current conditions or short-circuits through ISR software
♦ Supports: #1) one-shot trip for major short circuits or over
current conditions
#2) cycle-by-cycle trip for current limiting operation
EPWM1A
Over
Current DSP EPWM1B
EPWM2A
P
Sensors CORE W
EPWM2B M
EPWM3A
TZ1 EPWMxTZINT EPWM3B O
TZ2 Cycle-by-Cycle U
EPWM4A
TZ3 Mode EPWM4B T
P
…

TZ4 EPWM5A U
TZ5 One-Shot EPWM5B T
TZ6 Mode EPWM6A S
EPWM6B

The power drive protection is a safety feature that is provided for the safe operation of systems
such as power converters and motor drives. It can be used to inform the monitoring program of
motor drive abnormalities such as overvoltage, over-current, and excessive temperature rise. If
the power drive protection interrupt is unmasked, the PWM output pins will be put in the high-
impedance state immediately after the pin is driven low. An interrupt will also be generated.

TMS320C28x DSP Workshop - Control Peripherals 7 - 23

ePWM

ePWM Trip-Zone Module Registers

Name Description Structure

TZCTL Trip-Zone Control EPwmxRegs.TZCTL.all =
TZSEL Trip-Zone Select EPwmxRegs.TZSEL.all =
TZEINT Enable Interrupt EPwmxRegs.TZEINT.all =
TZFLG Trip-Zone Flag EPwmxRegs.TZFLG.all =
TZCLR Trip-Zone Clear EPwmxRegs.TZCLR.all =
TZFRC Trip-Zone Force EPwmxRegs.TZFRC.all =

ePWM Trip-Zone Control Register

EPwmxRegs.TZCTL.bit.yyyy =

15 - 4 3-2 1-0
reserved TZB TZA

TZ1 to TZ6 Action on EPWMxB / EPWMxA

00 = high impedance
01 = force high
10 = force low
11 = do nothing (disable)

7 - 24 TMS320C28x DSP Workshop - Control Peripherals

 ePWM

ePWM Trip-Zone Select Register

EPwmxRegs.TZSEL.bit.yyyy =

One-Shot Trip Zone

(event only cleared under S/W
control; remains latched)
0 = disable as trip source
1 = enable as trip source

15 - 14 13 12 11 10 9 8
reserved OSHT6 OSHT5 OSHT4 OSHT3 OSHT2 OSHT1

7-6 5 4 3 2 1 0
reserved CBC6 CBC5 CBC4 CBC3 CBC2 CBC1

Cycle-by-Cycle Trip Zone

(event cleared when CTR = 0;
i.e. cleared every PWM cycle)
0 = disable as trip source
1 = enable as trip source

ePWM Trip-Zone Enable Interrupt

Register
EPwmxRegs.TZEINT.bit.yyyy =

15 - 3 2 1 0
reserved OST CBC reserved

One-Shot Cycle-by-Cycle
Interrupt Enable Interrupt Enable
0 = disable 0 = disable
1 = enable 1 = enable

TMS320C28x DSP Workshop - Control Peripherals 7 - 25

ePWM

ePWM Event-Trigger Module

ePWM Event-Trigger Module

CMPA . 15 - 0 CMPB . 15 - 0
TBCTL . 12 - 7
Shadowed Shadowed
Clock Compare Compare
Prescaler Register Register
AQCTLA . 11 - 0
TBCTR . 15 - 0
AQCTLB . 11 - 0 DBCTL . 4 - 0
16-Bit
Compare Action Dead
Time-Base
Logic Qualifier Band
Counter

EPWMxSYNCI EPWMxSYNCO
Period
Register EPWMxA
PWM Trip
Shadowed EPWMxB
Chopper Zone
SYSCLKOUT TBPRD . 15 - 0
PCCTL . 10 - 0 TZx
TZSEL . 15 - 0

Note: x = 1, 2, 3, 4, 5, or 6

ePWM Event-Trigger Interrupts and SOC

TBCTR

. . . . . . . .
TBPRD
CMPB
CMPA

EPWMA

EPWMB

CTR = 0

CTR = PRD
CTRU = CMPA
CTRD = CMPA

CTRU = CMPB
CTRD = CMPB

7 - 26 TMS320C28x DSP Workshop - Control Peripherals

 ePWM

ePWM Event-Trigger Module Registers

Name Description Structure

ETSEL ET Selection EPwmxRegs.ETSEL.all =
ETPS ET Pre-Scale EPwmxRegs.ETPS.all =
ETFLG Event-Trigger Flag EPwmxRegs.ETFLG.all =
ETCLR Event-Trigger Clear EPwmxRegs.ETCLR.all =
ETFRC Event-Trigger Force EPwmxRegs.ETFRC.all =

ePWM Event-Trigger Selection Register

EPwmxRegs.ETSEL.bit.yyyy =

Enable SOCB / A Enable EPWMxINT

0 = disable 0 = disable
1 = enable 1 = enable

15 14 - 12 11 10 - 8 7-4 3 2-0
SOCBEN SOCBSEL SOCAEN SOCASEL reserved INTEN INTSEL

EPWMxSOCB / A Select EPWMxINT Select

000 = reserved 000 = reserved
001 = CTR = 0 001 = CTR = 0
010 = CTR = PRD 010 = CTR = PRD
011 = reserved 011 = reserved
100 = CTRU = CMPA 100 = CTRU = CMPA
101 = CTRD = CMPA 101 = CTRD = CMPA
110 = CTRU = CMPB 110 = CTRU = CMPB
111 = CTRD = CMPB 111 = CTRD = CMPB

TMS320C28x DSP Workshop - Control Peripherals 7 - 27

ePWM

ePWM Event-Trigger Prescale Register

EPwmxRegs.ETPS.bit.yyyy =

EPWMxSOCB / A Counter EPWMxINT Counter

(number of events have occurred) (number of events have occurred)
00 = no events 00 = no events
01 = 1 event 01 = 1 event
10 = 2 events 10 = 2 events
11 = 3 events 11 = 3 events

15 - 14 13 - 12 11 - 10 9-8 7-4 2-3 1-0

SOCBCNT SOCBPRD SOCACNT SOCAPRD reserved INTCNT INTPRD

EPWMxSOCB / A Period EPWMxINT Period

(number of events before SOC) (number of events before INT)
00 = disabled 00 = disabled
01 = SOC on first event 01 = INT on first event
10 = SOC on second event 10 = INT on second event
11 = SOC on third event 11 = INT on third event

Hi-Resolution PWM (HRPWM)

Hi-Resolution PWM (HRPWM)
PWM Period

Regular
Device Clock PWM Step
(i.e. 100MHz) (i.e. 10ns)

HRPWM divides a clock Calibration Logic tracks the

cycle into smaller steps number of Micro Steps per
ms ms ms ms ms ms
called Micro Steps clock to account for
(Step Size ~= 150ps) Calibration Logic variations caused by
Temp/Volt/Process

HRPWM
Micro Step (~150ps)

‹ Significantly increases the resolution of conventionally derived digital PWM

‹ Uses 8-bit extensions to Compare registers (CMPxHR) and Phase register
(TBPHSHR) for edge positioning control
‹ Typically used when PWM resolution falls below ~9-10 bits which occurs at
frequencies greater than ~200 kHz (with system clock of 100 MHz)
‹ Not all ePWM outputs support HRPWM feature (see device data manual)

7 - 28 TMS320C28x DSP Workshop - Control Peripherals

 Asymmetric and Symmetric Waveform Generation using the ePWM

Asymmetric and Symmetric Waveform Generation

using the ePWM
PWM switching frequency:
The PWM carrier frequency is determined by the value contained in the time-base period register,
and the frequency of the clocking signal. The value needed in the period register is:

⎛ switching period ⎞
Asymmetric PWM: period register = ⎜⎜ ⎟⎟ − 1
⎝ timer period ⎠

switching period
Symmetric PWM: period register =
2(timer period)

Notice that in the symmetric case, the period value is half that of the asymmetric case. This is
because for up/down counting, the actual timer period is twice that specified in the period register
(i.e. the timer counts up to the period register value, and then counts back down).

PWM resolution:
The PWM compare function resolution can be computed once the period register value is
determined. The largest power of 2 is determined that is less than (or close to) the period value.
As an example, if asymmetric was 1000, and symmetric was 500, then:

Asymmetric PWM: approx. 10 bit resolution since 210 = 1024 ≈ 1000

Symmetric PWM: approx. 9 bit resolution since 29 = 512 ≈ 500

PWM duty cycle:

Duty cycle calculations are simple provided one remembers that the PWM signal is initially
inactive during any particular timer period, and becomes active after the (first) compare match
occurs. The timer compare register should be loaded with the value as follows:

Asymmetric PWM: TxCMPR = (100% - duty cycle) ∗ TxPR

Symmetric PWM: TxCMPR = (100% - duty cycle) ∗ TxPR

Note that for symmetric PWM, the desired duty cycle is only achieved if the compare registers
contain the computed value for both the up-count compare and down-count compare portions of
the time-base period.

TMS320C28x DSP Workshop - Control Peripherals 7 - 29

Asymmetric and Symmetric Waveform Generation using the ePWM

ePWM Exercise

ePWM Exercise

Symmetric PWM is to be generated as follows:

• 50 kHz carrier frequency
• Timer counter clocked by 10 ns CPU clock
• 25% duty cycle initially

Determine the initialization values needed in the

TBPRD (period) and CMPA/B (compare) registers

7 - 30 TMS320C28x DSP Workshop - Control Peripherals

 eCAP

eCAP
Capture Units

Timer
Trigger .
Timestamp
Values

‹ Capture module timestamps

transitions on capture input pin
‹ Four capture registers (per capture
module) - associated with a capture
input pin
‹ Up to four capture modules per device

The capture units allow time-based logging of external TTL signal transitions on the capture input
pins. The C28x has up to four capture units.

Capture units can be configured to trigger an A/D conversion that is synchronized with an
external event. There are several potential advantages to using the capture for this function over
the ADCSOC pin associated with the ADC module. First, the ADCSOC pin is level triggered,
and therefore only low to high external signal transitions can start a conversion. The capture unit
does not suffer from this limitation since it is edge triggered and can be configured to start a
conversion on either rising edges, falling edges, or both. Second, if the ADCSOC pin is held high
longer than one conversion period, a second conversion will be immediately initiated upon
completion of the first. This unwanted second conversion could still be in progress when a
desired conversion is needed. In addition, if the end-of-conversion ADC interrupt is enabled, this
second conversion will trigger an unwanted interrupt upon its completion. These two problems
are not a concern with the capture unit. Finally, the capture unit can send an interrupt request to
the CPU while it simultaneously initiates the A/D conversion. This can yield a time savings
when computations are driven by an external event since the interrupt allows preliminary
calculations to begin at the start-of-conversion, rather than at the end-of-conversion using the
ADC end-of-conversion interrupt. The ADCSOC pin does not offer a start-of-conversion
interrupt. Rather, polling of the ADCSOC bit in the control register would need to be performed
to trap the externally initiated start of conversion.

TMS320C28x DSP Workshop - Control Peripherals 7 - 31

eCAP

Some Uses for the Capture Units

♦ Measure the time width of a pulse

♦ Low speed velocity estimation from incr. encoder:
Problem: At low speeds, calculation of speed
x -x
based on a measured position change at vk ≈ k k-1
fixed time intervals produces large estimate Δt
errors

Alternative: Estimate the speed using a measured time interval

at fixed position intervals
Signal from one
Δx
vk ≈ quadrature
tk - tk-1 encoder channel
Δx

eCAP Block Diagram

(Capture Mode)
CAP1POL
CAP1 . 31 - 0 ECCTL . 0

Capture 1 Polarity
Register Select 1
CAP2POL
CAP2 . 31 - 0 ECCTL . 2

TSCTR . 31 - 0 Capture 2 Polarity PRESCALE

Event Logic

Register Select 2 ECCTL . 13 - 9

32-Bit CAP3POL Event ECAPx
Time-Stamp CAP3 . 31 - 0 ECCTL . 4 Prescale
Counter
Capture 3 Polarity
Register Select 3
SYSCLKOUT CAP4POL
CAP4 . 31 - 0 ECCTL . 6

Capture 4 Polarity
Register Select 4
Note: x = 1, 2, 3, or 4

7 - 32 TMS320C28x DSP Workshop - Control Peripherals

 eCAP

eCAP Block Diagram

(APWM Mode)

Shadowed
Period CAP3 . 31 - 0
CAP1 . 31 - 0 Period Register shadow
immediate Register (CAP 3) mode
mode (Capture 1)

TSCTR . 31 - 0

32-Bit PWM APWMx

Time-Stamp Compare
Counter Logic

SYSCLKOUT
CAP2 . 31 - 0 Compare
immediate Register Compare CAP4 . 31 - 0
mode (Capture 2) Register shadow
Shadowed (CAP 4) mode

Note: x = 1, 2, 3, or 4

eCAP Module Registers

Name Description Structure
ECCTL1 Capture Control 1 ECapxRegs.ECCTL1.all =
ECCTL2 Capture Control 2 ECapxRegs.ECCTL2.all =
TSCTR Time-Stamp Counter ECapxRegs.TSCTR =
CTRPHS Counter Phase Offset ECapxRegs.CTRPHS =
CAP1 Capture 1 ECapxRegs.CAP1 =
CAP2 Capture 2 ECapxRegs.CAP2 =
CAP3 Capture 3 ECapxRegs.CAP3 =
CAP4 Capture 4 ECapxRegs.CAP4 =
ECEINT Enable Interrupt ECapxRegs.ECEINT.all =
ECFLG Interrupt Flag ECapxRegs.ECFLG.all =
ECCLR Interrupt Clear ECapxRegs.ECCLR.all =
ECFRC Interrupt Force ECapxRegs.ECFRC.all =

TMS320C28x DSP Workshop - Control Peripherals 7 - 33

eCAP

eCAP Control Register 1

ECapxRegs.ECCTL1.bit.yyyy =

Upper Register:
CAP1 – 4 Load
on Capture Event
0 = disable
1 = enable

15 - 14 13 - 9 8
FREE_SOFT PRESCALE CAPLDEN

Emulation Control Event Filter Prescale Counter

00 = TSCTR stops immediately 00000 = divide by 1 (bypass)
01 = TSCTR runs until equals 0 00001 = divide by 2
1X = free run (do not stop) 00010 = divide by 4
00011 = divide by 6
00100 = divide by 8
• • •
• • •
11110 = divide by 60
11111 = divide by 62

eCAP Control Register 1

ECapxRegs.ECCTL1.bit.yyyy =

Lower Register:
Counter Reset on Capture Event
0 = no reset (absolute time stamp mode)
1 = reset after capture (difference mode)

7 6 5 4 3 2 1 0
CTRRST4 CAP4POL CTRRST3 CAP3POL CTRRST2 CAP2POL CTRRST1 CAP1POL

Capture Event Polarity

0 = trigger on rising edge
1 = trigger on falling edge

7 - 34 TMS320C28x DSP Workshop - Control Peripherals

 eCAP

eCAP Control Register 2

ECapxRegs.ECCTL2.bit.yyyy =

Upper Register:
Capture / APWM mode
0 = capture mode
1 = APWM mode

15 - 11 10 9 8
reserved APWMPOL CAP_APWM SWSYNC

APWM Output Polarity Software Force

(valid only in APWM mode) Counter Synchronization
0 = active high output 0 = no effect
1 = active low output 1 = TSCTR load of current
module and other modules
if SYNCO_SEL bits = 00

eCAP Control Register 2

ECapxRegs.ECCTL2.bit.yyyy =

Lower Register:
Re-arm Continuous/One-Shot
Counter Sync-In (capture mode only) (capture mode only)
0 = disable 0 = no effect 0 = continuous mode
1 = enable 1 = arm sequence 1 = one-shot mode

7-6 5 4 3 2-1 0
SYNCO_SEL SYNCI_EN TSCTRSTOP REARM STOP_WRAP CONT_ONESHT

Sync-Out Select Time Stamp Stop Value for One-Shot Mode/

00 = sync-in to sync-out Counter Stop Wrap Value for Continuous Mode
01 = CTR = PRD event 0 = stop (capture mode only)
generates sync-out 1 = run 00 = stop/wrap after capture event 1
1X = disable 01 = stop/wrap after capture event 2
10 = stop/wrap after capture event 3
11 = stop/wrap after capture event 4

TMS320C28x DSP Workshop - Control Peripherals 7 - 35

eCAP

The capture unit interrupts offer immediate CPU notification of externally captured events. In
situations where this is not required, the interrupts can be masked and flag testing/polling can be
used instead. This offers increased flexibility for resource management. For example, consider a
servo application where a capture unit is being used for low-speed velocity estimation via a
pulsing sensor. The velocity estimate is not used until the next control law calculation is made,
which is driven in real-time using a timer interrupt. Upon entering the timer interrupt service
routine, software can test the capture interrupt flag bit. If sufficient servo motion has occurred
since the last control law calculation, the capture interrupt flag will be set and software can
proceed to compute a new velocity estimate. If the flag is not set, then sufficient motion has not
occurred and some alternate action would be taken for updating the velocity estimate. As a
second example, consider the case where two successive captures are needed before a
computation proceeds (e.g. measuring the width of a pulse). If the width of the pulse is needed as
soon as the pulse ends, then the capture interrupt is the best option. However, the capture
interrupt will occur after each of the two captures, the first of which will waste a small number of
cycles while the CPU is interrupted and then determines that it is indeed only the first capture. If
the width of the pulse is not needed as soon as the pulse ends, the CPU can check, as needed, the
capture registers to see if two captures have occurred, and proceed from there.

eCAP Interrupt Enable Register

ECapxRegs.ECEINT.bit.yyyy =

CTR = CMP CTR = Overflow Capture Event 3 Capture Event 1

Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable

15 - 8 7 6 5 4 3 2 1 0
reserved CTR=CMP CTR=PRD CTROVF CEVT4 CEVT3 CEVT2 CEVT1 reserved

CTR = PRD Capture Event 4 Capture Event 2

Interrupt Enable Interrupt Enable Interrupt Enable

0 = disable as interrupt source

1 = enable as interrupt source

7 - 36 TMS320C28x DSP Workshop - Control Peripherals

 eQEP

eQEP
What is an Incremental Quadrature
Encoder?
A digital (angular) position sensor

photo sensors spaced θ/4 deg. apart

slots spaced θ deg. apart θ/4

light source (LED)
θ

Ch. A

Ch. B
shaft rotation

Incremental Optical Encoder Quadrature Output from Photo Sensors

The eQEP circuit, when enabled, decodes and counts the quadrature encoded input pulses. The
QEP circuit can be used to interface with an optical encoder to get position and speed information
from a rotating machine.

How is Position Determined from

Quadrature Signals?
Position resolution is θ/4 degrees

(00) (11)
increment decrement
(A,B) = counter 10 counter
(10) (01)

Quadrature
Ch. A 00 Decoder 11
State Machine

Ch. B

01

TMS320C28x DSP Workshop - Control Peripherals 7 - 37

eQEP

eQEP Block Diagram

Measure the elapsed time

between the unit position events –
used for low speed measurement
Quadrature
Generate periodic
Capture
interrupts for velocity Quadrature - Direction -
calculations clock mode count mode
Monitors the quadrature
clock to indicate proper
operation of the motion EQEPxA/XCLK
control system
32-Bit Unit EQEPxB/XDIR
Time-Base Quadrature
QEP Decoder EQEPxI
Watchdog
EQEPxS
SYSCLKOUT
Position/Counter
Compare
Generate the direction and
clock for the position counter
Generate a sync output in quadrature count mode
and/or interrupt on a
position compare match

Note: up to two quadrature encoder interfaces on F280x device

eQEP Connections

Ch. A

Quadrature Ch. B
Capture

EQEPxA/XCLK
32-Bit Unit
Time-Base EQEPxB/XDIR
Quadrature
QEP Decoder EQEPxI Index
Watchdog
EQEPxS Strobe
from homing sensor
SYSCLKOUT
Position/Counter
Compare

7 - 38 TMS320C28x DSP Workshop - Control Peripherals

 Lab 7: Control Peripherals

Lab 7: Control Peripherals

¾ Objective

The objective of this lab is to apply the techniques discussed in module 7 and become familiar
with the programming and operation of the control peripherals and its interrupts. ePWM1A will
be setup to generate a 2 kHz, 25% duty cycle symmetric PWM waveform. The waveform will
then be sampled with the on-chip analog-to-digital converter and displayed using the graphing
feature of Code Composer Studio. Next, eCAP1 will be setup to detect the rising and falling
edges of the waveform. This information will be used to determine the width of the pulse and
duty cycle of the waveform. The results of this step will be viewed numerically in a memory
window.

Lab 7: Control Peripherals

ePWM1
TB Counter CPU copies
data
ADC memory
Compare connector result to
wire buffer during
Action Qualifier RESULT0

pointer rewind
ADC ISR
eCAP1 ADC-
Capture 1 Register INA0

...
Capture 2 Register
Capture 3 Register
Capture 4 Register
View ADC
buffer PWM
ePWM2 triggering ADC on
Samples
period match using SOC A
trigger every 20 µs (50 kHz)
ePWM2 Code Composer
Studio

¾ Procedure

Project File

Note: LAB7 files have been provided as a starting point for the lab and need to be
completed. DO NOT copy files from a previous lab.

1. A project named Lab7.pjt has been created for this lab. Open the project by clicking
on Project Æ Open… and look in C:\C28x\Labs\Lab7. All Build Options
have been configured like the previous lab. The files used in this lab are:

TMS320C28x DSP Workshop - Control Peripherals 7 - 39

Lab 7: Control Peripherals

Main_7.c Labcfg.cmd
Lab.cdb DSP280x_Headers_BIOS.cmd
User_5_6_7.cmd CodeStartBranch.asm
SysCtrl.c Gpio.c
DSP280x_GlobalVariableDefs.c PieCtrl_5_6_7_8_9.c
DefaultIsr_5_6_7.c Adc.c
EPwm_7_8_9_10.c DelayUs.asm

Setup Shared I/O and ePWM1

2. Edit Gpio.c and adjust the shared I/O pin in GPIO0 for the PWM1A function.

3. In EPwm_7_8_9_10.c, setup ePWM1 to implement the PWM waveform as described

in the objective for this lab. The following registers need to be modified: TBCTL (set
clock prescales to divide-by-1, no software force, sync and phase disabled), TBPRD,
CMPA, CMPCTL (load on 0 or PRD), and AQCTLA (set on up count and clear on down
count for output A). Software force, deadband, PWM chopper and trip action has been
disabled. (Hint – notice the last steps enable the timer count mode and enble the clock to
the ePWM module). Make use of the global variable names and values that have been set
using #define in the beginning of EPwm_7_8_9_10.c file. Notice that ePWM2 has
been initialized earlier in the code for the ADC lab. Save your work.

Build and Load

4. Save all changes to the files and click the “Build” button to build and load the project.

Run the Code – PWM Waveform

5. Open a memory window to view some of the contents of the ADC results buffer. The
address label for the ADC results buffer is AdcBuf. We will be running our code in real-
time mode, and will have our window continuously refresh.

6. Using a connector wire provided, connect the PWM1A (pin # P8-9) to ADCINA0 (pin #
P9-2) on the eZdsp™.

7. Run the code (real-time mode) using the GEL function: GEL Æ Realtime
Emulation Control Æ Run_Realtime_with_Reset. Watch the window
update. Verify that the ADC result buffer contains the updated values.

8. Open and setup a graph to plot a 50-point window of the ADC results buffer.
Click: View Æ Graph Æ Time/Frequency… and set the following values:

7 - 40 TMS320C28x DSP Workshop - Control Peripherals

 Lab 7: Control Peripherals

Start Address AdcBuf

Acquisition Buffer Size 50

Display Data Size 50

DSP Data Type 16-bit unsigned integer

Sampling Rate (Hz) 50000

Time Display Unit μs

Select OK to save the graph options.

9. The graphical display should show the generated 2 kHz, 25% duty cycle symmetric
PWM waveform. The period of a 2 kHz signal is 500 μs. You can confirm this by
measuring the period of the waveform using the graph (you may want to enlarge the
graph window using the mouse). The measurement is best done with the mouse. The
lower left-hand corner of the graph window will display the X and Y-axis values.
Subtract the X-axis values taken over a complete waveform period (you can use the PC
calculator program found in Microsoft Windows to do this).

Frequency Domain Graphing Feature of Code Composer Studio

10. Code Composer Studio also has the ability to make frequency domain plots. It does this
by using the PC to perform a Fast Fourier Transform (FFT) of the DSP data. Let's make
a frequency domain plot of the contents in the ADC results buffer (i.e. the PWM
waveform).

Click: View Æ Graph Æ Time/Frequency… and set the following values:

Display Type FFT Magnitude

Start Address AdcBuf

Acquisition Buffer Size 50

FFT Framesize 50

DSP Data Type 16-bit unsigned integer

Sampling Rate (Hz) 50000

Select OK to save the graph options.

11. On the plot window, left-click the mouse to move the vertical marker line and observe the
frequencies of the different magnitude peaks. Do the peaks occur at the expected
frequencies?

TMS320C28x DSP Workshop - Control Peripherals 7 - 41

Lab 7: Control Peripherals

12. Fully halt the DSP (real-time mode) by using the GEL function: GEL Æ Realtime
Emulation Control Æ Full_Halt.

Setup eCAP1 to Measure Width of Pulse

The first part of this lab exercise generated a 2 kHz, 25% duty cycle symmetric PWM
waveform which was sampled with the on-chip analog-to-digital converter and displayed
using the graphing feature of Code Composer Studio. Next, eCAP1 will be setup to detect
the rising and falling edges of the waveform. This information will be used to determine the
width of the pulse and duty cycle of the waveform. The results of this step will be viewed
numerically in a memory window and can be compared to the results obtained using the
graphing features of Code Composer Studio.
13. Add the following file to the project:
ECap_7_8_9_10.c

Check your files list to make sure the file is there.

14. In Main_7.c, add code to call the InitECap() function. There are no passed
parameters or return values, so the call code is simply:
InitECap();

15. Edit Gpio.c and adjust the shared I/O pin in GPIO5 for the ECAP1 function.

16. Open and inspect the eCAP1 interrupt service routine (ECAP1_INT_ISR) in the file
DefaultIsr_5_6_7.c. Notice that PWM_duty is calculated by CAP2 – CAP1
(rising to falling edge) and that PWM_period is calculated by CAP3 – CAP1 (rising to
rising edge).

17. In ECap_7_8_9_10.c, setup eCAP1 to calculate PWM_duty and PWM_period. The

following registers need to be modified: ECCTL2 (continuous mode, re-arm disable, and
sync disable), ECCTL1 (set prescale to divide-by-1, configure capture event polarity
without reseting the counter), and ECEINT (enable desired eCAP interrupt).

18. Using the “PIE Interrupt Assignment Table” find the location for the
eCAP1 interrupt, “ECAP1_INT” and fill in the following information:

PIE group #: # within group:

This information will be used in the next step.

19. Modify the end of ECap_7_8_9_10.c to do the following:

enable the “ECAP1_INT” interrupt in the PIE (Hint: use the PieCtrlRegs structure)
enable core INT4 (IER register)
20. Modify the configuration file lab.cdb to setup the PIE vector for the ECAP1 interrupt.
Click on the plus sign (+) to the left of Scheduling and again on the plus sign (+) to
the left of HWI – Hardware Interrupt Service Routine Manager. Click
the plus sign (+) to the left of PIE INTERRUPTS. Locate the interrupt location for the

7 - 42 TMS320C28x DSP Workshop - Control Peripherals

 Lab 7: Control Peripherals

ECAP1_INT (use the information from step #18). Right click, select Properties, and
type _ECAP1_INT_ISR (with a leading underscore) in the function field. Click OK
and save all updates.

Build and Load

21. Save all changes to the files and click the “Build” button.

Run the Code – Pulse Width Measurement

22. Open a memory window to view the address label PWM_duty. (Type &PWM_duty in
the address box). The address label PWM_period (address &PWM_period) should
appear in the same memory window.

23. Set the memory window properties format to “32-Bit UnSigned Int”. Click OK.

24. Using the connector wire provided, connect the PWM1A (pin # P8-9) to ECAP1 (pin #
P8-14) on the eZdsp™.

25. Run the code (real-time mode) by using the GEL function: GEL Æ Realtime
Emulation Control Æ Run_Realtime_with_Reset. Notice the values for
PWM_duty and PWM_period.

26. Fully halt the DSP (real-time mode) by using the GEL function: GEL Æ Realtime
Emulation Control Æ Full_Halt.

Questions:
• How do the captured values for PWM_duty and PWM_period relate to the compare
register CMPA and time-base period TBPRD settings for ePWM1A?
• What is the value of PWM_duty in memory?
• What is the value of PWM_period in memory?
• How does it compare with the expected value?

End of Exercise

TMS320C28x DSP Workshop - Control Peripherals 7 - 43

ePWM Exercise Solution

ePWM Exercise Solution

ePWM Exercise Solution

1 . carrier period 1 . 20 μs
TBPRD = = = 1000 = 3E8h
2 timer period 2 10 ns

CMPA/B = (100% - duty cycle)*TBPRD = 0.75*1000 = 750 = 2EEh

TPWM
50 kHz = 20 μs

Period
CPU clock = 10 ns
Compare

Counter

Output Pin

7 - 44 TMS320C28x DSP Workshop - Control Peripherals

 Numerical Concepts & IQmath

Introduction
In this module, numerical concepts will be explored. One of the first considerations concerns
multiplication – how does the user store the results of a multiplication, when the process of mul-
tiplication creates results larger than the inputs. A similar concern arises when considering accu-
mulation – especially when long summations are performed. Then, IQmath will be described as a
technique for implementing a “virtual floating-point” system to simplify the design process.

The IQmath Library is a collection of highly optimized and high precision mathematical
functions used to seamlessly port floating-point algorithms into fixed-point code. These C/C++
routines are typically used in computationally intensive real-time applications where optimal
execution speed and high accuracy is needed. By using these routines a user can achieve
execution speeds considerable faster than equivalent code written in standard ANSI C language.
In addition, by incorporating the ready-to-use high precision functions, the IQmath library can
shorten significantly a DSP application development time. (The IQmath user's guide is included
in the application zip file, and can be found in the /docs folder once the file is extracted and
installed).

Learning Objectives
Learning Objectives

‹ Compare/contrast integer and

fractional operations
‹ Discuss fixed-point math
development limitations
‹ Compare/contrast floating-point and
IQ representation
‹ Describe the IQmath approach and
the problem it solves

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8-1

Module Topics

Module Topics
Numerical Concepts & IQmath ............................................................................................................... 8-1

Module Topics......................................................................................................................................... 8-2

Numbering System Basics ....................................................................................................................... 8-3
Binary Numbers.................................................................................................................................. 8-3
Two's Complement Numbers ............................................................................................................. 8-3
Sign Extension Mode.......................................................................................................................... 8-5
Binary Multiplication.............................................................................................................................. 8-6
Binary Fractions ..................................................................................................................................... 8-8
Representing Fractions in Binary ....................................................................................................... 8-8
Multiplying Binary Fractions ............................................................................................................. 8-9
Correcting Redundant Sign Bit..........................................................................................................8-10
Fraction Coding.....................................................................................................................................8-11
Fractional vs. Integer Representation....................................................................................................8-12
IQmath ...................................................................................................................................................8-13
Floating-Point Representation ...........................................................................................................8-14
IQ Fractional Representation.............................................................................................................8-15
Traditional “Q” Math Approach........................................................................................................8-17
IQmath Approach ..............................................................................................................................8-19
IQmath Library ......................................................................................................................................8-24
AC Induction Motor Example ................................................................................................................8-26
IQmath Appications and Summary ........................................................................................................8-33
Converting ADC Results into IQ Format...............................................................................................8-35
Lab 8: IQmath FIR Filter.......................................................................................................................8-36

8-2 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 Numbering System Basics

Numbering System Basics

Given the ability to perform arithmetic processes (addition and multiplication) with the C28x, it is
important to understand the underlying mathematical issues which come into play. Therefore, we
shall examine the numerical concepts which apply to the C28x and, to a large degree, most
processors.

Binary Numbers
The binary numbering system is the simplest numbering scheme used in computers, and is the
basis for other schemes. Some details about this system are:
• It uses only two values: 1 and 0
• Each binary digit, commonly referred to as a bit, is one “place” in a binary number
and represents an increasing power of 2.
• The least significant bit (LSB) is to the right and has the value of 1.
• Values are represented by setting the appropriate 1's in the binary number.
• The number of bits used determines how large a number may be represented.

Examples:
01102 = (0 * 8) + (1 * 4) + (1 * 2) + (0 * 1) = 610
111102 = (1 * 16) + (1 * 8) + (1 * 4) + (1 * 2) + (0 * 1) = 3010

Two's Complement Numbers

Notice that binary numbers can only represent positive numbers. Often it is desirable to be able to
represent both positive and negative numbers. The two's complement numbering system modifies
the binary system to include negative numbers by making the most significant bit (MSB)
negative. Thus, two's complement numbers:
• Follow the binary progression of simple binary except that the MSB is negative — in
addition to its magnitude
• Can have any number of bits — more bits allow larger numbers to be represented

Examples:
01102 = (0 * -8) + (1 * 4) + (1 * 2) + (0 * 1) = 610
111102 = (1 * -16) + (1 * 8) + (1 * 4) + (1 * 2) + (0 * 1) = -210

The same binary values are used in these examples for two's complement as were used above for
binary. Notice that the decimal value is the same when the MSB is 0, but the decimal value is
quite different when the MSB is 1.

Two operations are useful in working with two's complement numbers:

• The ability to obtain an additive inverse of a value
• The ability to load small numbers into larger registers (by sign extending)

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8-3

Numbering System Basics

To load small two's complement numbers into larger

registers:
The MSB of the original number must carry to the MSB of the number when represented in the
larger register.
1. Load the small number “right justified” into the larger register.
2. Copy the sign bit (the MSB) of the original number to all unfilled bits to the left in the
register (sign extension).

Consider our two previous values, copied into an 8-bit register:

Examples:
Original No. 0 1 1 02 = 610 1 1 1 1 02 = -210

1. Load low 0110 11110

2. Sign Extend 00000110 =4+2=6 11111110 = -128 + 64 + ... + 2 = -2

8-4 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 Numbering System Basics

Sign Extension Mode

The C28x can operate on either unsigned binary or two's complement operands. The “Sign
Extension Mode” (SXM) bit, present within a status register of the C28x, identifies whether or
not the sign extension process is used when a value is brought into the accumulator. It is good
programming practice to always select the desired SXM at the beginning of a module to assure
the proper mode.

What is Sign Extension?

‹ When moving a value from a narrowed width location
to a wider width location, the sign bit is extended to fill
the width of the destination
‹ Sign extension applies to signed numbers only
‹ It keeps negative numbers negative!
‹ Sign extension controlled by SXM bit in ST0 register;
When SXM = 1, sign extension happens automatically

4 bit Example: Load a memory value into the ACC

memory 1101 = -23 + 22 + 20 = -3

Load and sign extend

ACC 1111 1101 = -27 + 26 + 25 + 24 + 23 + 22 + 20

= -128 + 64 + 32 + 16 + 8 + 4 + 1
= -3

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8-5

Binary Multiplication

Binary Multiplication
Now that you understand two's complement numbers, consider the process of multiplying two
two's complement values. As with “long hand” decimal multiplication, we can perform binary
multiplication one “place” at a time, and sum the results together at the end to obtain the total
product.

Note: This is not the method the C28x uses in multiplying numbers — it is merely a way of observing
how binary numbers work in arithmetic processes.

The C28x uses 16-bit operands and a 32-bit accumulator. For the sake of clarity, consider the
example below where we shall investigate the use of 4-bit values and an 8-bit accumulation:

Four-Bit Integer Multiplication

0100 4
x 1101 x -3
00000100
0000000
000100
11100
11110100 -12
Accumulator 11110100
11110100
Data Memory ?

Is there a better numbering system?

In this example, consider the following:

• What are the two input values, and the expected result?
• Why are the “partial products” shifted left as the calculation continues?
• Why is the final partial product “different” than the others?
• What is the result obtained when adding the partial products?
• How shall this result be loaded into the accumulator?
• How shall we fill the remaining bit? Is this value still the expected one?
• How can the result be stored back to memory? What problems arise?

8-6 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 Binary Multiplication

Note: With two’s complement multiplication, the leading “1” in the second multiplicand is a
sign bit. If the sign bit is “1”, then take the 2’s complement of the first multiplicand.
Additionally, each partial product must be sign-extended for correct computation.

Note: All of the above questions except the final one are addressed in this module. The last
question may have several answers:

• Store the lower accumulator to memory. What problem is apparent using this
method in this example?
• Store the upper accumulator back to memory. Wouldn't this create a loss of
precision, and a problem in how to interpret the results later?
• Store both the upper and lower accumulator to memory. This solves the above
problems, but creates some new ones:
− Extra code space, memory space, and cycle time are used
− How can the result be used as the input to a subsequent calculation? Is such a
condition likely (consider any “feedback” system)?

From this analysis, it is clear that integers do not behave well when multiplied. Might some other
type of number system behave better? Is there a number system where the results of a
multiplication are bounded?

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8-7

Binary Fractions

Binary Fractions
Given the problems associated with integers and multiplication, consider the possibilities of using
fractional values. Fractions do not grow when multiplied, therefore, they remain representable
within a given word size and solve the problem. Given the benefit of fractional multiplication,
consider the issues involved with using fractions:
• How are fractions represented in two's complement?
• What issues are involved when multiplying two fractions?

Representing Fractions in Binary

In order to represent both positive and negative values, the two's complement process will again
be used. However, in the case of fractions, we will not set the LSB to 1 (as was the case for
integers). When one considers that the range of fractions is from -1 to ~+1, and that the only bit
which conveys negative information is the MSB, it seems that the MSB must be the “negative
ones position.” Since binary representation is based on powers of two, it follows that the next bit
would be the “one-halves” position, and that each following bit would have half the magnitude
again. Considering, as before, a 4-bit model, we have the representation shown in the following
example.

1 . 0 1 1 = -1 + 1/4 + 1/8 = -5/8

-1 1/2 1/4 1/8

8-8 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 Binary Fractions

Multiplying Binary Fractions

When the C28x performs multiplication, the process is identical for all operands, integers or
fractions. Therefore, the user must determine how to interpret the results. As before, consider the
4-bit multiply example:

Four-Bit Multiplication

0100
. 1/2
x 1101
. x - 3/8
00000100
0000000
000100
11100
11110100 -3/16
Accumulator 11110100
11110100

Data Memory 1110

. -1/4

As before, consider the following:

• What are the two input values and the expected result?
• As before, “partial products” are shifted left and the final is negative.
• How is the result (obtained when adding the partial products) read?
• How shall this result be loaded into the accumulator?
• How shall we fill the remaining bit? Is this value still the expected one?
• How can the result be stored back to memory? What problems arise?

To “read” the result of the fractional multiply, it is necessary to locate the binary point (the base 2
equivalent of the base 10 decimal point). Start by identifying the location of the binary point in
the input values. The MSB is an integer and the next bit is 1/2, therefore, the binary point would
be located between them. In our example, therefore, we would have three bits to the right of the
binary point in each input value. For ease of description, we can refer to these as “Q3” numbers,
where Q refers to the number of places to the right of the point.

When multiplying numbers, the Q values add. Thus, we would (mentally) place a binary point
above the sixth LSB. We can now calculate the “Q6” result more readily.

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8-9

Binary Fractions

As with integers, the results are loaded low, and the MSB is a sign extension of the seventh bit. If
this value were loaded into the accumulator, we could store the results back to memory in a
variety of ways:
• Store both low and high accumulator values back to memory. This offers maximum
detail, but has the same problems as with integer multiply.
• Store only the high (or low) accumulator back to memory. This creates a potential for
a memory littered with varying Q-types.
• Store the upper accumulator shifted to the left by 1. This would store values back to
memory in the same Q format as the input values, and with equal precision to the
inputs. How shall the left shift be performed? Here’s three methods:
− Explicit shift (C or assembly code)
− Shift on store (assembly code)
− Use Product Mode shifter (assembly code)

Correcting Redundant Sign Bit

Correcting Redundant Sign Bit

Accumulator 11 11 11 11 00 11 00 00
Redundant
Sign Bit

‹ Correcting Redundant Sign Bit

Š IQmath: automatically handled (next topic)
Š Q math in “C”, shift in software:
int x,y,z;
z = ((long)x * (long)y) >> 15;

8 - 10 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 Fraction Coding

Fraction Coding
Although COFF tools recognize values in integer, hex, binary, and other forms, they understand
only integer, or non-fractional values. To use fractions within the C28x, it is necessary to describe
them as though they were integers. This turns out to be a very simple trick. Consider the
following number lines:

How is a fraction coded?

~1 ~ 32K 7FFF

½ 16K 4000

0
⇒ 0 0000
*32768
–½ –16K C000

–1 –32K 8000
Fractions Integers Hex

‹ Example: represent the fraction number 0.707

void main(void) {
int coef = 32768 * 707 / 1000;
}

By multiplying a fraction by 32K (32768), a normalized fraction is created, which can be passed
through the COFF tools as an integer. Once in the C28x, the normalized fraction looks and
behaves exactly as a fraction. Thus, when using fractional constants in a C28x program, the coder
first multiplies the fraction by 32768, and uses the resulting integer (rounded to the nearest whole
value) to represent the fraction.

The following is a simple, but effective method for getting fractions past the assembler:
1. Express the fraction as a decimal number (drop the decimal point).
2. Multiply by 32768.
3. Divide by the proper multiple of 10 to restore the decimal position.

¾ Examples:
• To represent 0.62: 32768 x 62 / 100
• To represent 0.1405: 32768 x 1405 / 10000

This method produces a valid number accurate to 16 bits. You will not need to do the math
yourself, and changing values in your code becomes rather simple.

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 11

Fractional vs. Integer Representation

Fractional vs. Integer Representation

Fractional vs. Integer

‹ Range
Š Integers have a maximum range
determined by the number of bits
Š Fractions have a maximum range of ±1
‹ Precision
Š Integers have a maximum precision of 1
Š Fractional precision is determined by
the number of bits

The C28x accumulator, a 32-bit register, adds extra range to integer calculations, but this
becomes a problem in storing the results back to 16-bit memory.

Conversely, when using fractions, the extra accumulator bits increase precision, which helps
minimize accumulative errors. Since any number is accurate (at best) to ± one-half of a LSB,
summing two of these values together would yield a worst case result of 1 LSB error. Four
summations produce two LSBs of error. By 256 summations, eight LSBs are “noisy.” Since the
accumulator holds 32 bits of information, and fractional results are stored from the high
accumulator, the extra range of the accumulator is a major benefit in noise reduction for long
sum-of-products type calculations.

8 - 12 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 IQmath

IQmath
Implementing complex digital control algorithms on a Digital Signal Processor (DSP), or any
other DSP capable processor, typically come across the following issues:
• Algorithms are typically developed using floating-point math
• Floating-point devices are more expensive than fixed-point devices
• Converting floating-point algorithms to a fixed-point device is very time consuming
• Conversion process is one way and therefore backward simulation is not always possible

The diagram below illustrates a typical development scenario in use today:

So how do we really use all this fraction stuff?

The Fix-Point Development Dilemma

Natural development
Simulation
Platform starts with simulation in
Takes many days/weeks (i.e. MatLab) floating-point
to convert (one way
process)

Can be easily ported

Fixed-Point Floating-Point
Algorithm Algorithm to floating-point
(ASM, C, C++) (C or C++) device

Floating-Point DSP
Fix-Point DSP

The design may initially start with a simulation (i.e. MatLab) of a control algorithm, which
typically would be written in floating-point math (C or C++). This algorithm can be easily ported
to a floating-point device, however because of cost reasons, most likely a 16-bit or 32-bit fixed-
point device would be used in many target systems.

The effort and skill involved in converting a floating-point algorithm to function using a 16-bit or
32-bit fixed-point device is quite significant. A great deal of time (many days or weeks) would
be needed for reformatting, scaling and coding the problem. Additionally, the final
implementation typically has little resemblance to the original algorithm. Debugging is not an
easy task and the code is not easy to maintain or document.

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 13

IQmath

Floating-Point Representation
IEEE Std. 754 Single Precision
Floating-Point
31 30 23 22 0
s eeeeeeee fffffffffffffffffffffff
1 bit sign 8 bit exponent 23 bit mantissa (fraction)

Case 1: if e = 255 and f =/ 0, then v = NaN

Case 2: if e = 255 and f = 0, then v = [(-1)s]*infinity

Case 3: if 0 < e < 255, then v = [(-1)s]*[2(e-127)]*(1.f)

Case 4: if e = 0 and f =/ 0, then v = [(-1)s]*[2(-126)]*(0.f)
Case 5: if e = 0 and f = 0, then v = [(-1)s]*0

Advantage ⇒ Exponent gives large dynamic range

Disadvantage ⇒ Precision of a number depends on its exponent

Floating-Point does not Solve

Everything!
Example: x = 10.0 (0x41200000)
+ y = 0.000000238 (0x347F8CF1)

z = 10.000000238 WRONG!
RIGHT?
You cannot represent 10.000000238 with
single-precision floating point

0x412000000 = 10.000000000
10.000000238 ⇐ can’t represent!
0x412000001 = 10.000000950

So z gets rounded down to 10.000000000

8 - 14 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 IQmath

IQ Fractional Representation
A new approach to fixed-point algorithm development, termed “IQmath”, can greatly simplify the
design development task. This approach can also be termed “virtual floating-point” since it looks
like floating-point, but it is implemented using fixed-point techniques.

IQ Fractional Representation

31 0
S IIIIIIII fffffffffffffffffffffff
32 bit mantissa

.
-2I + 2I-1 + … + 21 + 20 2-1 + 2-2 + … + 2-Q

Advantage ⇒ Precision same for all numbers in an IQ format

Disadvantage ⇒ Limited dynamic range compared to floating point

The IQmath approach enables the seamless portability of code between fixed and floating-point
devices. This approach is applicable to many problems that do not require a large dynamic range,
such as motor or digital control applications.

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 15

IQmath

IQmath Can Solve the Problem!

I8Q24 Example: x = 10.0 (0x0A000000)

+ y = 0.000000238 (0x00000004)

z = 10.000000238 (0x0A000004)

Exact Result (this example)

8 - 16 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 IQmath

Traditional “Q” Math Approach

Traditional 16-bit “Q” Math Approach
y = mx + b

s Q15 M
ss Q30
s Q15 X
sssssssssssss Q15 s Q15 B
Align Binary
<< 15 Point For Add
ss Q30

sI Q30

Align Binary
>> 15 Point For Store
ssssssssssssI Q15 s Q15 Y

in C: Y = ((i32) M * (i32) X + (i32) B << Q) >> Q;

Traditional 32-bit “Q” Math Approach

y = mx + b

I8 Q24 M
I16 Q48
I8 Q24 X
ssssssssssssssssssI8 Q24 I8 Q24 B
Align Decimal
<< 24 Point for Add
ssssI8 Q48

I16 Q48

Align Decimal
>> 24 Point for Store
sssssssssssssssssI16 Q24 I8 Q24 Y

in C: Y = ((i64) M * (i64) X + (i64) B << Q) >> Q;

Note: Requires support for 64-bit integer data type in compiler

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 17

IQmath

The traditional approach to performing math operations, using fixed-point numerical techniques
can be demonstrated using a simple linear equation example. The floating-point code for a linear
equation would be:
float Y, M, X, B;
Y = M * X + B;

For the fixed-point implementation, assume all data is 32-bits, and that the "Q" value, or location
of the binary point, is set to 24 fractional bits (Q24). The numerical range and resolution for a
32-bit Q24 number is as follows:

Q value Min Value Max Value Resolution

Q24 -2(32-24) = -128.000 000 00 2(32-24) – (½)24 = 127.999 999 94 (½)24 = 0.000 000 06

The C code implementation of the linear equation is:

int32 Y, M, X, B; // numbers are all Q24

Y = ((int64) M * (int64) X + (int64) B << 24) >> 24;

Compared to the floating-point representation, it looks quite cumbersome and has little resem-
blance to the floating-point equation. It is obvious why programmers prefer using floating-point
math.

The slide shows the implementation of the equation on a processor containing hardware that can
perform a 32x32 bit multiplication, 64-bit addition and 64-bit shifts (logical and arithmetic) effi-
ciently.

The basic approach in traditional fixed-point "Q" math is to align the binary point of the operands
that get added to or subtracted from the multiplication result. As shown in the slide, the multipli-
cation of M and X (two Q24 numbers) results in a Q48 value that is stored in a 64-bit register.
The value B (Q24) needs to be scaled to a Q48 number before addition to the M*X value (low
order bits zero filled, high order bits sign extended). The final result is then scaled back to a Q24
number (arithmetic shift right) before storing into Y (Q24). Many programmers may be familiar
with 16-bit fixed-point "Q" math that is in common use. The same example using 16-bit numbers
with 15 fractional bits (Q15) would be coded as follows:

int16 Y, M, X, B; // numbers are all Q15

Y = ((int32) M * (int32) X + (int32) B << 15) >> 15;

In both cases, the principal methodology is the same. The binary point of the operands that get
added to or subtracted from the multiplication result must be aligned.

8 - 18 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 IQmath

IQmath Approach
32-bit IQmath Approach
y = mx + b

I8 Q24 M
I16 Q48
I8 Q24 X
Align Decimal
Point Of Multiply
>> 24
sssssssssssssssssI16 Q24

I8 Q24 B

I8 Q24 I8 Q24 Y

in C: Y = ((i64) M * (i64) X) >> Q + B;

In the "IQmath" approach, rather then scaling the operands, which get added to or subtracted
from the multiplication result, we do the reverse. The multiplication result binary point is scaled
back such that it aligns to the operands, which are added to or subtracted from it. The C code
implementation of this is given by linear equation below:

int32 Y, M, X, B;
Y = ((int64) M * (int64) X) >> 24 + B;

The slide shows the implementation of the equation on a processor containing hardware that can
perform a 32x32 bit multiply, 32-bit addition/subtraction and 64-bit logical and arithmetic shifts
efficiently.

The key advantage of this approach is shown by what can then be done with the C and C++ com-
piler to simplify the coding of the linear equation example.

Lets take an additional step and create a multiply function in C that performs the following opera-
tion:

int32 _IQ24mpy(int32 M, int32 X) { return ((int64) M * (int64) X) >> 24; }

The linear equation can then be written as follows:

Y = _IQ24mpy(M , X) + B;

Already we can see a marked improvement in the readability of the linear equation.

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 19

IQmath

Using the operator overloading features of C++, we can overload the multiplication operand "*"
such that when a particular data type is encountered, it will automatically implement the scaled
multiply operation. Lets define a data type called "iq" and assign the linear variables to this data
type:

iq Y, M, X, B // numbers are all Q24

The overloading of the multiply operand in C++ can be defined as follows:

iq operator * (const iq &M, const iq &X) { return ((int64) M * (int64) X) >> 24; }

Then the linear equation, in C++, becomes:

Y = M * X + B;

This final equation looks identical to the floating-point representation. It looks "natural". The
four approaches are summarized in the table below:

Math Implementations Linear Equation Code

32-bit floating-point math in C Y = M * X + B;
32-bit fixed-point "Q" math in C Y = ((int64) M * (int64) X) + (int64) B << 24) >> 24;
32-bit IQmath in C Y = _IQ24mpy(M, X) + B;
32-bit IQmath in C++ Y = M * X + B;

Essentially, the mathematical approach of scaling the multiplier operand enables a cleaner and a
more "natural" approach to coding fixed-point problems. For want of a better term, we call this
approach "IQmath" or can also be described as "virtual floating-point".

8 - 20 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 IQmath

IQmath Approach
Multiply Operation

Y = ((i64) M * (i64) X) >> Q + B;

Redefine the multiply operation as follows:
_IQmpy(M,X) == ((i64) M * (i64) X) >> Q

This simplifies the equation as follows:

Y = _IQmpy(M,X) + B;

C28x compiler supports “_IQmpy” intrinsic; assembly code generated:

MOVL XT,@M
IMPYL P,XT,@X ; P = low 32-bits of M*X
QMPYL ACC,XT,@X ; ACC = high 32-bits of M*X
LSL64 ACC:P,#(32-Q) ; ACC = ACC:P << 32-Q
; (same as P = ACC:P >> Q)
ADDL ACC,@B ; Add B
MOVL @Y,ACC ; Result = Y = _IQmpy(M*X) + B
; 7 Cycles

IQmath Approach
It looks like floating-point!

float Y, M, X, B;
Floating-Point
Y = M * X + B;

long Y, M, X, B;
Traditional
Fix-Point Q Y = ((i64) M * (i64) X + (i64) B << Q)) >> Q;

“IQmath” _iq Y, M, X, B;

In C Y = _IQmpy(M, X) + B;

“IQmath” iq Y, M, X, B;

In C++ Y = M * X + B;

Taking advantage of operator overloading feature in C++,

“IQmath” looks like floating-point math (looks natural!)

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 21

IQmath

IQmath Approach
GLOBAL_Q simplification
User selects “Global Q” value for the whole application
GLOBAL_Q
based on the required dynamic range or resolution, for example:
GLOBAL_Q Max Val Min Val Resolution
28 7.999 999 996 -8.000 000 000 0.000 000 004
24 127.999 999 94 -128.000 000 00 0.000 000 06
20 2047.999 999 -2048.000 000 0.000 001

#define GLOBAL_Q 18 // set in “IQmathLib.h” file

_iq Y, M, X, B;
Y = _IQmpy(M,X) + B; // all values are in Q = 18
The user can also explicitly specify the Q value to use:
_iq20 Y, M, X, B;
Y = _IQ20mpy(M,X) + B; // all values are in Q = 20

The basic "IQmath" approach was adopted in the creation of a standard math library for the Texas
Instruments TMS320C28x DSP fixed-point processor. This processor contains efficient hardware
for performing 32x32 bit multiply, 64-bit shifts (logical and arithmetic) and 32-bit add/subtract
operations, which are ideally suited for 32 bit "IQmath".

Some enhancements were made to the basic "IQmath" approach to improve flexibility. They are:

Setting Of GLOBAL_Q Parameter Value: Depending on the application, the amount of nu-
merical resolution or dynamic range required may vary. In the linear equation example, we used
a Q value of 24 (Q24). There is no reason why any value of Q can't be used. In the "IQmath"
library, the user can set a GLOBAL_Q parameter, with a range of 1 to 30 (Q1 to Q30). All func-
tions used in the program will use this GLOBAL_Q value. For example:

#define GLOBAL_Q 18
Y = _IQmpy(M, X) + B; // all values use GLOBAL_Q = 18

If, for some reason a particular function or equation requires a different resolution, then the user
has the option to implicitly specify the Q value for the operation. For example:

Y = _IQ23mpy(M,X) + B; // all values use Q23, including B and Y

The Q value must be consistent for all expressions in the same line of code.

8 - 22 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 IQmath

IQmath Approach
Targeting Fixed-Point or Floating-Point device

Y = _IQmpy(M, X) + B;
User selects target math type
(in “IQmathLib.h” file)
#if MATH_TYPE == IQ_MATH #if MATH_TYPE == FLOAT_MATH

Y = (float)M * (float)X + (float)B;

Compile & Run Compile & Run

using “IQmath” on using floating-point math on
C28x C3x, C67x,C28x (RTS), PC,..

All “IQmath” operations have an equivalent floating-point operation

Selecting FLOAT_MATH Or IQ_MATH Mode: As was highlighted in the introduction, we

would ideally like to be able to have a single source code that can execute on a floating-point or
fixed-point target device simply by recompiling the code. The "IQmath" library supports this by
setting a mode, which selects either IQ_MATH or FLOAT_MATH. This operation is performed
by simply redefining the function in a header file. For example:

#if MATH_TYPE == IQ_MATH

#define _IQmpy(M , X) _IQmpy(M , X)
#elseif MATH_TYPE == FLOAT_MATH
#define _IQmpy(M , X) (float) M * (float) X
#endif

Essentially, the programmer writes the code using the "IQmath" library functions and the code
can be compiled for floating-point or "IQmath" operations.

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 23

IQmath Library

IQmath Library
IQmath Library: math & trig functions (v1.4)
Operation Floating-Point “IQmath” in C “IQmath” in C++
type float A, B; _iq A, B; iq A, B;
constant A = 1.2345 A = _IQ(1.2345) A = IQ(1.2345)
multiply A*B _IQmpy(A , B) A*B
divide A/B _IQdiv (A , B) A/B
add A+B A+B A+B
substract A-B A-B A–B
boolean >, >=, <, <=, ==, |=, &&, || >, >=, <, <=, ==, |=, &&, || >, >=, <, <=, ==, |=, &&, ||
trig sin(A),cos(A) _IQsin(A), _IQcos(A) IQsin(A),IQcos(A)
functions sin(A*2pi),cos(A*2pi) _IQsinPU(A), _IQcosPU(A) IQsinPU(A),IQcosPU(A)
atan(A),atan2(A,B) _IQatan(A), _IQatan2(A,B) IQatan(A),IQatan2(A,B)
atan2(A,B)/2pi _IQatan2PU(A,B) IQatan2PU(A,B)
sqrt(A),1/sqrt(A) _IQsqrt(A), _IQisqrt(A) IQsqrt(A),IQisqrt(A)
sqrt(A*A + B*B) _IQmag(A,B) IQmag(A,B)
saturation if(A > Pos) A = Pos _IQsat(A,Pos,Neg) IQsat(A,Pos,Neg)
if(A < Neg) A = Neg

Accuracy of functions/operations approx ~28 to ~31 bits

Additionally, the "IQmath" library contains DSP library modules for filters (FIR & IIR) and Fast
Fourier Transforms (FFT & IFFT).

IQmath Library: Conversion Functions (v1.4)

Operation Floating-Point “IQmath” in C “IQmath” in C++

iq to iqN A _IQtoIQN(A) IQtoIQN(A)
iqN to iq A _IQNtoIQ(A) IQNtoIQ(A)
integer(iq) (long) A _IQint(A) IQint(A)
fraction(iq) A – (long) A _IQfrac(A) IQfrac(A)
iq = iq*long A * (float) B _IQmpyI32(A,B) IQmpyI32(A,B)
integer(iq*long) (long) (A * (float) B) _IQmpyI32int(A,B) IQmpyI32int(A,B)
fraction(iq*long) A - (long) (A * (float) B) _IQmpyI32frac(A,B) IQmpyI32frac(A,B)
qN to iq A _QNtoIQ(A) QNtoIQ(A)
iq to qN A _IQtoQN(A) IQtoQN(A)
string to iq atof(char) _atoIQ(char) atoIQ(char)
IQ to float A _IQtoF(A) IQtoF(A)

IQmath.lib > contains library of math functions

IQmathLib.h > C header file
IQmathCPP.h > C++ header file

8 - 24 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 IQmath Library

16-Bit vs. 32-Bit

The "IQmath" approach could also be used on 16 bit sized numbers and for many problems, this
is sufficient resolution. However, in many control cases, the user needs to use many different
"Q" values to accommodate the limited resolution of a 16-bit number.

With DSP devices like the TMS320C28x processor, which can perform 16 bit and 32 bit sized
math with equal efficiency, the choice becomes more of productivity (time to market). Why
bother spending a whole lot of time trying to code using 16 bit numbers when you can simply use
32 bit numbers, pick one value of "Q" that will accommodate all cases and not worry about
spending too much time optimizing.

Of course there is a concern on data RAM usage if numbers that could be represented in 16 bits
all use 32 bits. This is becoming less of an issue in today's processors because of the finer tech-
nology used and the amount of RAM that can be cheaply integrated. However, in many cases,
this problem can be mitigated by performing intermediate calculations using 32 bit numbers and
converting the input from 16 bit to 32 bit and converting the output from 32 to 16 bit before stor-
ing the final results. In many problems, it is the intermediate calculations that require additional
accuracy to avoid quantization problems.

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 25

AC Induction Motor Example

AC Induction Motor Example

AC Induction Motor Example
One of the more complex motor control algorithms

‹ Sensorless, ACI induction machine direct rotor flux control

‹ Goal: motor speed estimation & alpha-axis stator current estimation

The "IQmath" approach is ideally suited for applications where a large numerical dynamic range
is not required. Motor control is an example of such an application (audio and communication
algorithms are other applications). As an example, the IQmath approach has been applied to the
sensor-less direct field control of an AC induction motor. This is probably one of the most chal-
lenging motor control problems and as will be shown later, requires numerical accuracy greater
then 16-bits in the control calculations.

The above slide is a block diagram representation of the key control blocks and their interconnec-
tions. Essentially this system implements a "Forward Control" block for controlling the d-q axis
motor current using PID controllers and a "Feedback Control" block using back emf's integration
with compensated voltage from current model for estimating rotor flux based on current and volt-
age measurements. The motor speed is simply estimated from rotor flux differentiation and open-
loop slip computation. The system was initially implemented on a "Simulator Test Bench" which
uses a simulation of an "AC Induction Motor Model" in place of a real motor. Once working, the
system was then tested using a real motor on an appropriate hardware platform.

Each individual block shown in the slide exists as a stand-alone C/C++ module, which can be
interconnected to form the complete control system. This modular approach allows reusability
and portability of the code.

8 - 26 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 AC Induction Motor Example

The next few slides shows the coding of one particular block, PARK Transform, using floating-
point and "IQmath" approaches in C and C++:

AC Induction Motor Example

Park Transform - floating-point C code

#include “math.h”
#define TWO_PI 6.28318530717959
void park_calc(PARK *v)
{
float cos_ang , sin_ang;
sin_ang = sin(TWO_PI * v->ang);
cos_ang = cos(TWO_PI * v->ang);

v->de = (v->ds * cos_ang) + (v->qs * sin_ang);

v->qe = (v->qs * cos_ang) - (v->ds * sin_ang);
}

AC Induction Motor Example

Park Transform - converting to “IQmath” C code

#include “math.h”
#include “IQmathLib.h”
#define TWO_PI _IQ(6.28318530717959)
6.28318530717959
void park_calc(PARK *v)
{
float
_iq cos_ang , sin_ang;
sin_ang = _IQsin(_IQmpy(TWO_PI
sin(TWO_PI * v->ang);, v->ang));
cos_ang = _IQcos(_IQmpy(TWO_PI
cos(TWO_PI * v->ang);, v->ang));

v->de = _IQmpy(v->ds , cos_ang)

(v->ds * cos_ang) + _IQmpy(v->qs
+ (v->qs * sin_ang); , sin_ang);
v->qe = _IQmpy(v->qs , cos_ang)
(v->qs * cos_ang) - _IQmpy(v->ds
- (v->ds * sin_ang); , sin_ang);
}

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 27

AC Induction Motor Example

AC Induction Motor Example

Park Transform - converting to “IQmath” C++ code

#include “math.h”
extern “C” { #include “IQmathLib.h” }
#include “IQmathCPP.h”

#define TWO_PI IQ(6.28318530717959)

6.28318530717959
void park_calc(PARK *v)
{
iq
float cos_ang , sin_ang;
sin_ang = IQsin(TWO_PI
sin(TWO_PI * * v->ang);
v->ang);
cos_ang = IQcos(TWO_PI
cos(TWO_PI * *
v->ang);
v->ang);

v->de = (v->ds * cos_ang) + (v->qs * sin_ang);

v->qe = (v->qs * cos_ang) - (v->ds * sin_ang);
}

As can be seen, the floating-point C and "IQmath" C++ code looks almost identical. It is quite a
simple and fast procedure to take any floating-point algorithm and convert it to an "IQmath" algo-
rithm.

The complete system was coded using "IQmath". Based on analysis of coefficients in the system,
the largest coefficient had a value of 33.3333. This indicated that a minimum dynamic range of 7
bits (+/-64 range) was required. Therefore, this translated to a GLOBAL_Q value of 32-7 = 25
(Q25). Just to be safe, the initial simulation runs were conducted with GLOBAL_Q = 24 (Q24)
value.

8 - 28 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 AC Induction Motor Example

The code was compiled and run on the Texas Instruments TMS320C28x fixed-point DSP device
(IQ_MATH mode) and on the TMS320C3x floating-point DSP device (FLOAT_MATH mode).
The plots of speed and stator current for both devices matched and are shown below.

The plots start from a step change in reference speed from 0.0 to 0.5 and 1024 samples are taken.
The speed eventually settles to the desired reference value and the stator current exhibits a clean
and stable oscillation. The block diagram slide shows at which points in the control system the
plots are taken from.

AC Induction Motor Example

GLOBAL_Q = 24, system stable

IQmath: speed IQmath: current

Floating Point: speed Floating Point: current

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 29

AC Induction Motor Example

AC Induction Motor Example

GLOBAL_Q = 27, system unstable

IQmath: speed

IQmath: current

AC Induction Motor Example

GLOBAL_Q = 16, system unstable

IQmath: speed

IQmath: current

8 - 30 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 AC Induction Motor Example

With the ability to select the GLOBAL_Q value for all calculations in the "IQmath", an experi-
ment was conducted to see what maximum and minimum Q value the system could tolerate be-
fore it became unstable. The results are tabulated in the slide below:

AC Induction Motor Example

Q stability range

Q range Stability Range

Unstable
Q31 to Q27 (not enough dynamic range)

Q26 to Q19 Stable

Q18 to Q0 Unstable
(not enough resolution, quantization problems)

The developer must pick the right GLOBAL_Q value!

The above indicates that, the AC induction motor system that we simulated requires a minimum
of 7 bits of dynamic range (+/-64) and requires a minimum of 19 bits of numerical resolution (+/-
0.000002). This confirms our initial analysis that the largest coefficient value being 33.33333
required a minimum dynamic range of 7 bits. As a general guideline, users using IQmath should
examine the largest coefficient used in the equations and this would be a good starting point for
setting the initial GLOBAL_Q value. Then, through simulation or experimentation, the user can
reduce the GLOBAL_Q until the system resolution starts to cause instability or performance deg-
radation. The user then has a maximum and minimum limit and a safe approach is to pick a mid-
point.

What the above analysis also confirms is that this particular problem does require some calcula-
tions to be performed using greater then 16 bit precision. The above example requires a mini-
mum of 7 + 19 = 26 bits of numerical accuracy for some parts of the calculations. Hence, if one
were implementing the AC induction motor control algorithm using a 16 bit fixed-point DSP, it
would require the implementation of higher precision math for certain portions. This would take
more cycles and programming effort.

The great benefit of using GLOBAL_Q is that the user does not necessarily need to go into de-
tails to assign an individual Q for each variable in a whole system, as is typically done in conven-
tional fixed-point programming. This is time consuming work. By using 32-bit resolution and the
"IQmath" approach, the user can easily evaluate the overall resolution and quickly implement a
typical digital motor control application without quantization problems.

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 31

AC Induction Motor Example

AC Induction Motor Example

Performance comparisons

C28x C C3x C C67x C C67x C

IQmath (-g) float (-g) float (-g) float (no –g)
Benchmark (150MHz) (75MHz) (167MHz) (167MHz)
B1: Forward control cycles 482 308 627 432
B2: ACI model cycles 564 215 321 183
B3: Feedback control cycles 1081 829 1295 973
Key benchmark cycles (B1+B3) 1563 1137 1922 1405
% of available MHz used 20.9% 30.3% 23.0% 16.8%
(20kHz control loop)

Notes: C28x compiled on CGT V3.03, V1.4c IQmath Lib (debug enabled (-g), max opt).
C3x compiled on CGT V5.12, RTS30R Lib (debug enabled (-g), max opt).
C67x compiled on CGT V4.20, RTSFast Lib (debug enabled (-g)/disabled, max opt).
On C67x, when debug is enabled (-g), parallel execution of operations are limited.
On C28x & C3x, turning off debug (no –g) has minimal impact on performance.

Using the profiling capabilities of the respective DSP tools, the table above summarizes the num-
ber of cycles and code size of the forward and feedback control blocks.

The MIPS used is based on a system sampling frequency of 20kHz, which is typical of such sys-
tems.

8 - 32 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 IQmath Appications and Summary

IQmath Appications and Summary

Where Is IQmath Applicable?

Anywhere a large dynamic range is not required

Motor Control (PID, State Estimator, Kalman,...)
Servo Control
Modems
Audio (MP3, etc.)
Imaging (JPEG, etc.)
Any application using 16/32-bit fixed-point Q math

Where it is not applicable

Graphical applications (3D rotation, etc.)
When trying to squeeze every last cycle

IQmath Approach Summary

“IQmath” + fixed-point processor with 32-bit capabilities =
‹ Seamless portability of code between fixed and floating-
point devices
Š User selects target math type in “IQmathLib.h” file
Š #if MATH_TYPE == IQ_MATH
Š #if MATH_TYPE == FLOAT_MATH
‹ One source code set for simulation vs. target device
‹ Numerical resolution adjustability based on application
requirement
Š Set in “IQmathLib.h” file
Š #define GLOBAL_Q 18
Š Explicitly specify Q value
Š _iq20 X, Y, Z;
‹ Numerical accuracy without sacrificing time and cycles
‹ Rapid conversion/porting and implementation of algorithms

IQmath library is freeware - available from TI DSP website

http://www.ti.com/c2000

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 33

IQmath Appications and Summary

The IQmath approach, matched to a fixed-point processor with 32x32 bit capabilities enables the
following:

• Seamless portability of code between fixed and floating-point devices

• Maintenance and support of one source code set from simulation to target device
• Adjustability of numerical resolution (Q value) based on application requirement
• Implementation of systems that may otherwise require floating-point device
• Rapid conversion/porting and implementation of algorithms

8 - 34 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 Converting ADC Results into IQ Format

Converting ADC Results into IQ Format

As you may recall, the converted values of the ADC are placed in the upper 12 bit of the
RESULT0 register. Before these values are filtered using the IQmath library, they need to to be
put into the IQ format as a 32-bit long.

Getting the ADC Result into IQ Format

x x x x x x x x x x x x 0 0 0 0 RESULTx

Do not sign extend

31 15 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x x x x x x x x 0 0 0 0 32-bit long

Notice that the 32-bit long is already in I16Q16 format!

#define AdcFsVoltage _IQ(3.0) // ADC full scale voltage
_iq Result, temp; // ADC result
void main(void)
{
// convert the unsigned 16-bit result to unsigned 32-bit
// temp = AdcRegs.ADCRESULT0;
// convert resulting IQ16 to IQ format
// temp = _IQ16toIQ(temp);
// scale by ADC full-scale range (optional)
// Result = _IQmpy(AdcFsVoltage, temp);
Result = _IQmpy(AdcFsVoltage, _IQ16toIQ( (_iq)AdcRegs.ADCRESULT0));
}

For uni-polar ADC inputs (i.e., 0 to 3 V inputs), a conversion to global IQ format can be achieved
with:

IQresult_unipolar = _IQmpy(_IQ(3.0),_IQ16toIQ((_iq) AdcRegs.ADCRESULT0));

How can we modify the above to recover bi-polar inputs, for example +-1.5 volts? One could do
the following to offset the +1.5V analog biasing applied to the ADC input:

IQresult_bipolar =
_IQmpy(_IQ(3.0),_IQ16toIQ((_iq) AdcRegs.ADCRESULT0)) - _IQ(1.5);

However, one can see that the largest intermediate value the equation above could reach is 3.0.
This means that it cannot be used with an IQ data type of IQ30 (IQ30 range is -2 < x < ~2). Since
the IQmath library supports IQ types from IQ1 to IQ30, this could be an issue in some applica-
tions.

The following clever approach supports IQ types from IQ1 to IQ30:

IQresult_bipolar =
_IQmpy(_IQ(1.5),_IQ15toIQ((_iq) ((int16) (AdcRegs.ADCRESULT0 ^ 0x8000))));

The largest intermediate value that this equation could reach is 1.5. Therefore, IQ30 is easily
supported.

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 35

Lab 8: IQmath FIR Filter

Lab 8: IQmath FIR Filter

¾ Objective

The objective of this lab is to apply the techniques discussed in module 8 and to become familiar
with IQmath programming. In the previous lab, ePWM1A was setup to generate a 2 kHz, 25%
duty cycle symmetric PWM waveform. The waveform was then sampled with the on-chip
analog-to-digital converter. In this lab the sampled waveform will be passed through an IQmath
FIR filter and displayed using the graphing feature of Code Composer Studio.

Lab 8: IQmath FIR Filter

ePWM1 ADC
TB Counter ADCINA0 RESULT0 IQmath
Compare
Action Qualifier FIR Filter
connector
wire

ePWM2 triggering ADC on

period match using SOC A data
trigger every 20 µs (50 kHz) memory
ePWM 2

pointer rewind CPU copies

result to
buffer during

...
ADC ISR

Display
using CCS

¾ Procedure

Project File

Note: LAB8 files have been provided as a starting point for the lab and need to be
completed. DO NOT copy files from a previous lab.

1. A project named Lab8.pjt has been created for this lab. Open the project by clicking
on Project Æ Open… and look in C:\C28x\Labs\Lab8. All Build Options
have been configured like the previous lab. The files used in this lab are:

8 - 36 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 Lab 8: IQmath FIR Filter

Main_8.c Labcfg.cmd
Lab.cdb DSP280x_Headers_BIOS.cmd
User_8_9.cmd CodeStartBranch.asm
SysCtrl.c Gpio.c
DSP280x_GlobalVariableDefs.c PieCtrl_5_6_7_8_9.c
DefaultIsr_8.c Adc.c
EPwm_7_8_9_10.c ECap_7_8_9_10.c
Filter.c DelayUs.asm

Project Build Options

2. Setup the include search path to include the IQmath header file. Open the Build
Options and select the Compiler tab. In the Preprocessor Category, find the Include
Search Path (-i) box and add to the end of the line (preceeded with a semicolon to
append this directory to the existing search path):

;c:\tidcs\c28\IQmath\cIQmath\include

3. Setup the library search path to include the IQmath library. Open the Build Options
and select the linker tab.

a. In the Basic Category, find the Library Search Path (-i) box and enter:

c:\tidcs\c28\IQmath\cIQmath\lib

b. In the Include Libraries (-l) box enter: IQmath.lib

Then select OK to save the Build Options.

Include IQmathLib.h
4. Open Lab.h and uncomment the line that includes the IQmathLib.h header file.
Next, in the Function Prototypes section, uncomment the function prototype for IQssfir(),
the IQ math single-sample FIR filter function.

Inspect User_8_9.cmd
5. Open and inspect User_8_9.cmd. First, notice that a section called “IQmath” is
being linked to H0SARAM. The IQmath section contains the IQmath library functions
(code). Second, notice that a section called “IqmathTables” is being linked to the
BOOTROM with a TYPE = NOLOAD modifier after its allocation. The IQmath tables are
used by the IQmath library functions. The NOLOAD modifier allows the linker to
resolve all addresses in the section, but the section is not actually placed into the .out
file. This is done because the section is already present in the device ROM (you cannot
load data into ROM after the device is manufactured!). The tables were put in the ROM
by TI when the device was manufactured. All we need to do is link the section to the
addresses where it is known to already reside (the tables are the very first thing in the
BOOT ROM, starting at address 0x3FF000).

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 37

Lab 8: IQmath FIR Filter

Select a Global IQ value

6. Open the file c:\tidcs\c28\IQmath\cIQmath\include\IQmathLib.h.
Confirm that the GLOBAL_Q type (near beginning of file) is set to a value of 24. If it is
not, modify as necessary:
#define GLOBAL_Q 24

Recall that this Q type will provide 8 integer bits and 24 fractional bits. Dynamic range
is therefore -128 < x < +128, which is sufficient for our purposes in the workshop.

IQmath Single-Sample FIR Filter

7. Open and inspect DefaultIsr_8.c. Notice that the ADCINT_ISR calls the IQmath
single-sample FIR filter function, IQssfir(). The filter coefficients have been defined in
the beginning of the file. Now open and inspect the IQssfir() function in Filter.c.
This is a simple, unoptimized coding of a basic IQmath single-sample FIR filter.

Build and Load

8. Click the “Build” button to build and load the project.

Run the Code – Filtered Waveform

9. Open a memory window to view some of the contents of the filtered ADC results buffer.
The address label for the filtered ADC results buffer is AdcBufFiltered. Set the Q-Value
to 24 (which matches the IQ format being used for this variable) and the Format to 32-Bit
Signed Int. We will be running our code in real-time mode, and will have our window
continuously refresh.

Note: For the next step, check to be sure that the jumper wire connecting PWM1A (pin # P8-9)
to ADCINA0 (pin # P9-2) is in place on the eZdsp™.

10. Run the code in real-time mode using the GEL function: GEL Æ Realtime
Emulation Control Æ Run_Realtime_with_Reset, and watch the memory
window update. Verify that the ADC result buffer contains updated values.

11. Open and setup a dual time graph to plot a 50-point window of the filtered and unfiltered
ADC results buffer. Click: View Æ Graph Æ Time/Frequency… and set the
following values:

8 - 38 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 Lab 8: IQmath FIR Filter

Display Type Dual Time

Start Address – upper display AdcBufFiltered

Start Address – lower display AdcBuf

Acquisition Buffer Size 50

Display Data Size 50

DSP Data Type 32-bit signed integer

Q-value 24

Sampling Rate (Hz) 50000

Time Display Unit μs

Select OK to save the graph options.

12. The graphical display should show the generated IQmath FIR filtered 2 kHz, 25% duty
cycle symmetric PWM waveform in the upper display and the unfiltered waveform
generated in the previous lab exercise in the lower display. Notice the shape and phase
differences between the waveform plots (the filtered curve has rounded edges, and lags
the unfiltered plot by several samples). The amplitudes of both plots should run from 0
to 3.0.

13. Open and setup two (2) frequency domain plots – one for the filtered and another for the
unfiltered ADC results buffer. Click: View Æ Graph Æ Time/Frequency…
and set the following values:

GRAPH #1 GRAPH #2

Display Type FFT Magnitude FFT Magnitude

Start Address AdcBuf AdcBufFiltered

Acquisition Buffer Size 50 50

FFT Framesize 50 50

DSP Data Type 32-bit signed integer 32-bit signed integer

Q-value 24 24

Sampling Rate (Hz) 50000 50000

Select OK to save the graph options.

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 39

Lab 8: IQmath FIR Filter

14. The graphical displays should show the frequency components of the filtered and
unfiltered 2 kHz, 25% duty cycle symmetric PWM waveforms. Notice that the higher
frequency components are reduced using the Low-Pass IQmath FIR filter in the filtered
graph as compared to the unfiltered graph.

15. Fully halt the DSP (real-time mode) by using the GEL function: GEL Æ Realtime
Emulation Control Æ Full_Halt.

End of Exercise

8 - 40 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 Lab 8: IQmath FIR Filter

Lab 8 Reference: IQmath FIR Filter

Bode Plot of Digital Low Pass Filter

Coefficients: [1/16, 4/16, 6/16, 4/16, 1/16]

Sample Rate: 50 kHz

TMS320C28x DSP Workshop - Numerical Concepts & IQmath 8 - 41

Lab 8: IQmath FIR Filter

8 - 42 TMS320C28x DSP Workshop - Numerical Concepts & IQmath

 Using DSP/BIOS

Introduction
This module discusses the basic features of using DSP/BIOS in a system. Scheduling threads,
periodic functions, and the use of real-time analysis tools will be demonstrated.

Learning Objectives
Learning Objectives

‹ Introduction to DSP/BIOS

‹ Scheduling DSP/BIOS threads

‹ Periodic Functions

‹ Real-time Analysis Tools

‹ DSP/BIOS API modules and summary

TMS320C28x DSP Workshop - Using DSP/BIOS 9-1

Module Topics

Module Topics
Using DSP/BIOS........................................................................................................................................ 9-1

Module Topics......................................................................................................................................... 9-2

Introduction to DSP/BIOS ...................................................................................................................... 9-3
Scheduling DSP/BIOS Threads............................................................................................................... 9-5
Periodic Functions.................................................................................................................................9-10
Real-time Analysis Tools........................................................................................................................9-11
DSP/BIOS API Module and Summary ...................................................................................................9-12
Lab 9: DSP/BIOS...................................................................................................................................9-13

9-2 TMS320C28x DSP Workshop - Using DSP/BIOS

 Introduction to DSP/BIOS

Introduction to DSP/BIOS
Introduction to DSP/BIOS
What is DSP/BIOS?
‹ A full-featured, scalable real-time kernel
Š System configuration tools
Š Preemptive multi-threading scheduler
Š Real-time analysis tools

Why use DSP/BIOS?

‹ Helps manage complex system resources
‹ Integrated with Code Composer Studio IDE
Š Requires no runtime license fees
Š Fully supported by TI and is a key component of TI’s
eXpressDSP™ real-time software technology
‹ Uses minimal MIPS and memory (2-8Kw)

DSP/BIOS Configuration Tool (file .cdb)

‹ System Setup Tools

Handles memory configuration
(builds .cmd file), run-time support
libraries, interrupt vectors, system
setup and reset, etc.
‹ Real-Time Analysis Tools
Allows application to run
uninterrupted while displaying
debug data
‹ Real-Time Scheduler
Preemptive tread manager kernel
‹ Real-Time I/O
Allows two way communication
between threads or between
target and PC host

TMS320C28x DSP Workshop - Using DSP/BIOS 9-3

Introduction to DSP/BIOS

DSP/BIOS Thread Types

HWI ‹ Used to implement ‘urgent’ part of real-time event

‹ Triggered by hardware interrupt
Hardware Interrupts ‹ HWI priorities fixed in hardware

‹ Use SWI to perform HWI ‘follow-up’ activity

SWI ‹ SWI's are ‘posted’ by software
Software Interrupts ‹ Multiple SWIs at each of 15 priority levels
Priority

‹ Use TSK to run different programs concurrently

TSK under separate contexts
Tasks ‹ TSK's enabled by posting ‘semaphore’ (a signal)

‹ Runs when no service routines are pending

IDL ‹ Runs as an infinite loop, like traditional while loop
Background ‹ All BIOS data transfers to host occur here

9-4 TMS320C28x DSP Workshop - Using DSP/BIOS

 Scheduling DSP/BIOS Threads

Scheduling DSP/BIOS Threads

Enabling BIOS – Return from main()
‹ Must delete the endless while() loop
‹ main() returns to BIOS and goes to IDLE thread,
allowing BIOS to schedule events, transfer
information to the host, etc.
‹ An endless while() loop in main() will not allow
BIOS to activate

void main(void)
{
/*** Initialization ***/
. . .
/*** Enable global interrupts ***/
// DSP/BIOS will enable global interrupts
/*** Main Loop ***/
// while() loop removed to enable DSP/BIOS
} //end of main()

Using Hardware Interrupts - HWI

‹ HWI manages hardware interrupts

‹ Configuration Tool used to assign
interrupt vectors
‹ DSP/BIOS HWI Dispatcher
performs context save/restore and
BIOS housekeeping
‹ Nested interrupts allow hardware
interrupts to preempt each other
‹ Number of HWI are determined by
the DSP architecture (PIE vector
table)
‹ Interrupt priority fixed by
architecture

Dispatcher allows the use of BIOS functionality in the ISR

TMS320C28x DSP Workshop - Using DSP/BIOS 9-5

Scheduling DSP/BIOS Threads

HWI Dispatcher for ISRs

‹ For non-BIOS code, use the interrupt keyword to declare an ISR
¾ tells the compiler to perform context save/restore
interrupt void MyHwi(void)
{
}

‹ For DSP/BIOS code, use the Dispatcher to perform the save/restore

¾ Remove the interrupt keyword from the MyHwi()
¾ Check the “Use Dispatcher” box when you configure the interrupt
vector in the DSP/BIOS configuration tool

Using Software Interrupts - SWI

‹ Make each algorithm an independent

software interrupt
‹ SWI scheduling is handled by DSP/BIOS
‹ HWI function triggered by hardware
‹ SWI function triggered by software
e.g. a call to SWI_post()
‹ Why use a SWI?
‹ No limitation on number of SWIs, and
priorities for SWIs are user-defined
‹ SWI can be scheduled by hardware or
software event(s)
‹ Defer processing from HWI to SWI

9-6 TMS320C28x DSP Workshop - Using DSP/BIOS

 Scheduling DSP/BIOS Threads

SWI Properties

Managing SWI Priority

‹
‹ Drag
DragandandDrop
DropSWIs
SWIstotochange
change
priority
priority
‹
‹ Equal
Equalpriority
prioritySWIs
SWIsrun
runin
inthe
the
order
orderthat
thatthey
theyare
areposted
posted

TMS320C28x DSP Workshop - Using DSP/BIOS 9-7

Scheduling DSP/BIOS Threads

Priority Based Thread Scheduling

post3 rtn
HWI 2 SWI_post(&swi2);
(highest)
post2 rtn
HWI 1
post1 rtn
SWI 3

int2 rtn
SWI 2
rtn
SWI 1
rtn
MAIN
int1
IDLE
(lowest)
User sets the priority...BIOS does the scheduling

Using Tasks - TSK

‹ DSP/BIOS tasks (TSK) are similar to
SWI, but offer additional flexibility
Š SWIs must run to completion
Š TSKs can be terminated by software
‹ Tradeoffs
Š SWI context switch is faster than TSK
Š TSK module requires more code space
Š TSKs have their own stack
‹ User preference and system needs
usually dictates choice – easy to
use both

9-8 TMS320C28x DSP Workshop - Using DSP/BIOS

 Scheduling DSP/BIOS Threads

SWIs and TSKs Compared

SWI SWI_post TSK SEM_post

start

SEM_pend Pause
“run to (blocked
completion” state)
start

end end

Š Similar to hardware interrupt, Š SEM_post() readies the TSK

but triggered by SWI_post() which pends on an event
Š All SWI's share system Š The event triggers the TSK
software stack to run once and pend
Š Each TSK has its own stack,
which allows them to pause
(or be terminated)

TMS320C28x DSP Workshop - Using DSP/BIOS 9-9

Periodic Functions

Periodic Functions
Using Periodic Functions - PRD
tick
DSP/BIOS
CLK

period

LED LED LED

‹ Periodic functions are a special type of SWI that are triggered by

DSP/BIOS
‹ Periodic functions run at a user specified rate:
- e.g. LED blink requires 0.5 Hz
‹ Use the CLK Manager to specify the DSP/BIOS CLK rate in
microseconds per “tick”
‹ Use the PRD Manager to specify the period (for the function) in ticks
‹ Allows multiple periodic functions with different rates

Creating a Periodic Function

tick
DSP/BIOS
CLK

period

func1 func1 func1

9 - 10 TMS320C28x DSP Workshop - Using DSP/BIOS

 Real-time Analysis Tools

Real-time Analysis Tools

Built-in Real-Time Analysis Tools
‹ Gather data on target (3-10 CPU cycles)
‹ Send data during BIOS IDL (100s of cycles)
‹ Format data on host (1000s of cycles)
‹ Data gathering does NOT stop target CPU

Execution Graph
‹ Software logic analyzer
‹ Debug event timing
and priority

CPU Load Graph

‹ Shows amount of CPU
horsepower being
consumed

Built-in Real-Time Analysis Tools

Statistics View
‹ Profile routines w/o
halting the CPU

Message LOG
‹ Send debug msgs to host
‹ Doesn’t halt the DSP
‹ Deterministic, low DSP
cycle count
‹ More efficient than
traditional printf()

LOG_printf(&trace, "AdcSwi_count = %u", AdcSwi_count++);

TMS320C28x DSP Workshop - Using DSP/BIOS 9 - 11

DSP/BIOS API Module and Summary

DSP/BIOS API Module and Summary

DSP/BIOS - API Modules
TSK Communication/Synchronization
Instrumentation/Real-Time Analysis
SEM Semaphores manager
LOG Message log manager MBX Mailboxes manager
STS Statistics accumulator manager LCK Resource lock manager
TRC Trace manager
Device-Independent Input/Output
RTDX Real-Time Data eXchange manager
PIP Data pipe manager
Thread Types
HST Host input/output manager
HWI Hardware interrupt manager SIO Stream I/O manager
SWI Software interrupt manager DEV Device driver interface
TSK Multi-tasking manager
Memory and Low-Level Primitives
IDL Idle function & process loop manager
MEM Memory manager
Clock and Periodic Functions
SYS System services manager
CLK System clock manager QUE Queue manager
PRD Periodic function manager ATM Atomic functions
GBL Global setting manager

Summary and Benefits of DSP/BIOS

‹ Fast time to market
Š no need to develop or maintain a “home-brew” kernel
‹ Efficient debugging of real-time applications
Š Real-Time Analysis
‹ Create robust applications
Š industry proven kernel technology
‹ Reduce cost of software maintenance
Š code reuse and standardized software
‹ Standardized APIs
Š enable rapid migration across C28x TMS320 DSPs
‹ Small footprint (2-8Kw)
Š easily fits in limited memory space
‹ Set of library functions (scalable)
Š use only what is needed to minimize code and data size
‹ Full featured kernel (extensible)
Š allows additional OS functions in future

9 - 12 TMS320C28x DSP Workshop - Using DSP/BIOS

 Lab 9: DSP/BIOS

Lab 9: DSP/BIOS
¾ Objective

The objective of this lab is to apply the techniques discussed in module 9 and to become familiar
with DSP/BIOS. In this lab exercise, we are going to change the ADCINT_ISR HWI to a SWI.
Then, we will replace the LED blink routine with a Periodic Function. Also, some features of the
real-time analysis tools will be demonstrated.

Lab 9: DSP/BIOS

ePWM1 ADC
TB Counter ADCINA0 RESULT0 IQmath
Compare
Action Qualifier FIR Filter
connector
wire

ePWM2 triggering ADC on

period match using SOC A data
trigger every 20 µs (50 kHz) memory
ePWM2

pointer rewind
Objective: CPU copies
result to
buffer during
‹ Change ADCINT_ISR

...
ADC ISR

HWI to SWI
‹ Replace LED blink Display
routine with a using CCS

Periodic Function

It will be interesting to investigate the DSP computational burden of the various parts of our
application, as well as the different pieces of DSP/BIOS that we will be using in this lab.
The ‘CPU Load Graph’ feature of DSP/BIOS will provide a quick and easy method for doing
this. We will be tabulating these results in the table that follows at various steps throughout the
remainder of this lab.

TMS320C28x DSP Workshop - Using DSP/BIOS 9 - 13

Lab 9: DSP/BIOS

Table 9-1: CPU Computational Burden Results

Case # Description CPU Load %

1 ADC processing handled in HWI. Filter inactive.

2 Case #1 + filter active.

3 ADC processing handled in SWI. Filter active.

LED blink handled in HWI.
RTA Global Host Enable disabled.

4 Case #3 + LED blink handled in PRD.

5 Case #4 + LOG_printf in SWI.

6 Case #5 + RTA SWI Logging enabled.

7 Case #6 + RTA SWI Accumulators enabled.

9 - 14 TMS320C28x DSP Workshop - Using DSP/BIOS

 Lab 9: DSP/BIOS

¾ Procedure

Project File

Note: LAB9 files have been provided as a starting point for the lab and need to be
completed. DO NOT copy files from a previous lab.

1. A project named Lab9.pjt has been created for this lab. Open the project by clicking
on Project Æ Open… and look in C:\C28x\Labs\Lab9. All Build Options
have been configured like the previous lab. The files used in this lab are:

Main_9.c Labcfg.cmd
Lab.cdb DSP280x_Headers_BIOS.cmd
User_8_9.cmd CodeStartBranch.asm
SysCtrl.c Gpio.c
DSP280x_GlobalVariableDefs.c PieCtrl_5_6_7_8_9.c
DefaultIsr_9.c Adc.c
EPwm_7_8_9_10.c ECap_7_8_9_10.c
Filter.c DelayUs.asm

Configuring DSP/BIOS Global Settings

2. Open the configuration file Lab.cdb and click on the plus sign (+) to the left of
System. Right click on Global Settings and select Properties. Change
the “DSP Speed in MHz (CLKOUT)” field to 100 so that it matches the processor
speed. Click OK to save the value and close the configuration window and select YES to
save the change to Lab.cdb. This value is used by the CLK manager to calculate the
register settings for the on-chip timers and provide the proper time-base for executing
CLK functions.

Prepare main() for DSP/BIOS

3. Open Main_9.c and delete the inline assembly code from main() that is used to enable
global interrupts. DSP/BIOS will enable global interrupts after main().

4. In Main_9.c, remove the endless while() loop from the end of main(). When using
DSP/BIOS, you must return from main(). In all DSP/BIOS programs, the main()
function should contain all one-time user-defined initialization functions. DSP/BIOS will
then take-over control of the software execution.

Build and Load

5. Click the “Build” button to build and load the project.

TMS320C28x DSP Workshop - Using DSP/BIOS 9 - 15

Lab 9: DSP/BIOS

Run the Code – HWI() Implementation

At this point, we have modified the code so that DSP/BIOS will take control after main()
completes. However, we have not made any other changes to the code since the previous lab.
Therefore, the computations we want performed in the ADCINT_ISR() (e.g., reading the ADC
result, running the filter) are still taking place in the hardware ISR, or to use DSP/BIOS
terminology, the HWI.

6. We will be running our code in real-time mode, and will have our window continuously
refresh. Run in Real-time Mode using the GEL function: GEL Æ Realtime
Emulation Control Æ Run_Realtime_with_Reset.

Note: For the next step, check to be sure that the jumper wire connecting PWM1A (pin # P8-9)
to ADCINA0 (pin # P9-2) is still in place on the eZdsp™.

7. Open and setup a dual time graph to plot a 50-point window of the filtered and unfiltered
ADC results buffer. Click: View Æ Graph Æ Time/Frequency… and set the
following values:

Display Type Dual Time

Start Address – upper display AdcBufFiltered

Start Address – lower display AdcBuf

Acquisition Buffer Size 50

Display Data Size 50

DSP Data Type 32-bit signed integer

Q-value 24

Sampling Rate (Hz) 50000

Time Display Unit μs

Select OK to save the graph options.

8. The graphical display should show the generated IQmath FIR filtered 2 kHz, 25% duty
cycle symmetric PWM waveform in the upper display and the unfiltered waveform
generated in the previous lab exercise in the lower display. The results should be the
same as the previous lab.

Fully halt the DSP (real-time mode) by using the GEL function: GEL Æ Realtime
Emulation Control Æ Full_Halt.

9. Open the RTA Control Panel by clicking DSP/BIOS Æ RTA Control Panel.
Uncheck ALL of the boxes. This disables most of the realtime analysis tools. We will
selectively enable them later in the lab.

9 - 16 TMS320C28x DSP Workshop - Using DSP/BIOS

 Lab 9: DSP/BIOS

10. Open the CPU Load Graph by clicking DSP/BIOS Æ CPU Load Graph. The CPU
load graph displays the percentage of available CPU computing horsepower that the
application is consuming. The CPU may be running ISRs, software interrupts, periodic
functions, performing I/O with the host, or running any user routine. When the CPU is
not executing user code, it will be idle (in the DSP/BIOS idle thread).

Run the code (real-time mode) by using the GEL function: GEL Æ Realtime
Emulation Control Æ Run_Realtime_with_Reset.

This graph should start updating, showing the percentage load on the DSP CPU. Keep
the DSP running to complete steps 11 through 14.

11. Open and inspect DefaultIsr_9.c. Notice that the global variable DEBUG_FILTER
is used to control the FIR filter in ADCINT_ISR(). If DEBUG_FILTER = 1, the FIR
filter is called and the AdcBufFilter array is filled with the filtered data. On the other
hand, if DEBUG_FILTER = 0, the filter is not called and the AdcBufFilter array is
filled with the unfiltered data.

12. Open the watch window and add the variable DEBUG_FILTER to it. Change its value
to “0” to turn off the FIR filtering. Notice the decrease in the CPU Load Graph.

13. Record the value shown in the CPU Load Graph under “Case #1” in Table 9-1.

14. Change the value of DEBUG_FILTER back to “1” in the watch window in order to bring
the FIR filter back online. Notice the jump in the CPU Load Graph.

15. Record the value shown in the CPU Load Graph under “Case #2” in Table 9-1.

16. Fully halt the DSP (real-time mode) by using the GEL function: GEL Æ Realtime
Emulation Control Æ Full_Halt.

Create a SWI
17. Open Main_9.c and notice that space has been added at the end of main() for two new
functions which will be used in this module – AdcSwi() and LedBlink(). In the next few
steps, we will move part of the ADCINT_ISR() routine from DefaultIsr_9.c to this
space in Main_9.c.

18. Open DefaultIsr_9.c and locate the ADCINT_ISR() routine. Move the entire
contents of the ADCINT_ISR() routine to the AdcSwi() function in Main_9.c with the
following exceptions:

DO NOT MOVE:

• The instruction used to acknowledge the PIE group interrupt.

• The GPIO pin toggle code.

• The LED toggle code.

TMS320C28x DSP Workshop - Using DSP/BIOS 9 - 17

Lab 9: DSP/BIOS

Be sure to move the static local variable declaration at the top of ADCINT_ISR() that is
used to index into the ADC buffers.

Comment: In almost all appplications, the PIE group acknowledge code is left in the HWI
(rather than move it to a SWI). This allows other interrupts to occur on that PIE group
even if the SWI has not yet executed. On the other hand, we are leaving the GPIO and
LED toggle code in the HWI just as an example. It illustrates that you can post a SWI
and also do additional operations in the HWI. DSP/BIOS is extremely flexible!

19. Open DefaultIsr_9.c and locate the section header comment:

/*** Global variables used by ADC_ISR() ***/.

Move the entire section contents that follow (e.g., all of the global variables, constant
definitions, and filter coefficients) to the space provided in Main_9.c, with the
following exception:

DO NOT MOVE:

• The variable definition for DEBUG_TOGGLE.

20. Delete the interrupt key word from the ADCINT_ISR. The interrupt keyword is not
used when a HWI is under DSP/BIOS control. A HWI is under DSP/BIOS control when
it uses any DSP/BIOS functionality, such as posting a SWI, or calling any DSP/BIOS
function or macro.

Post a SWI
21. In DefaultIsr_9.c add the following SWI_post to the ADCINT_ISR(), just after the
structure used to acknowledge the PIE group:

SWI_post(&ADC_swi); // post a SWI

This posts a SWI that will execute the ADC_swi() code you populated a few steps back
in the lab. In other words, the ADC interrupt still executes the same code as before.
However, most of that code is now in a posted SWI that DSP/BIOS will execute
according to the specified scheduling priorities.

Add the SWI to the CDB File

22. In the configuration file Lab.cdb we need to add and setup the AdcSwi() SWI. Open
Lab.cdb and click on the plus sign (+) to the left of Scheduling and again on the
plus sign (+) to the left of SWI – Software Interrupt Manager.

23. Right click on SWI – Software Interrupt Manager and select Insert SWI.
SWI0 will be added. Right-click on it, and rename it to ADC_swi. This is just an
arbitrary name. We want to differentiate the AdcSwi() function itself (which is nothing
but an ordinary C function) from the DSP/BIOS SWI object which we are calling
ADC_swi.

9 - 18 TMS320C28x DSP Workshop - Using DSP/BIOS

 Lab 9: DSP/BIOS

24. Select the Properties for ADC_swi and type _AdcSwi (with a leading underscore)
in the function field. Click OK. This tells DSP/BIOS that it should run the function
AdcSwi() when it executes the ADC_swi SWI.
25. We need to have the PIE for the ADC interrupt use the dispatcher. The dispatcher will
automatically perform the context save and restore, and allow the DSP/BIOS scheduler to
have insight into the ISR. You may recall from an earlier lab that the ADC interrupt is
located at PIE_INT1_6.

Click on the plus sign (+) to the left of HWI – Hardware Interrupt Service
Routine Manager. Click the plus sign (+) to the left of PIE INTERRUPTS. Locate
the interrupt location for the ADC: PIE_INT1_6. Right click, select Properties, and
select the Dispatcher tab.

Now check the “Use Dispatcher” box and select OK. Close the configuration file
and click YES to save changes.

Build and Load

26. Click the “Build” button to rebuild and load the project.

Run the Code – AdcSwi()

27. Run the code (real-time mode) by using the GEL function: GEL Æ Realtime
Emulation Control Æ Run_Realtime_with_Reset.

28. Confirm that the graphical display is showing the correct results. The results should be
the same as before (i.e., filtered PWM in the upper graph, unfiltered PWM in the lower
graph).

29. Record the value shown in the CPU Load Graph under “Case #3” in Table 9-1.

30. Fully halt the DSP (real-time mode) by using the GEL function: GEL Æ Realtime
Emulation Control Æ Full_Halt.

Add a Periodic Function

Recall that an instruction was used in the ADCINT_ISR to toggle the LED on the eZdsp™. This
instruction will be moved into a periodic function that will toggle the LED at the same rate.

31. Open DefaultIsr_9.c and locate the ADCINT_ISR routine. Move the instruction
used to toggle the LED to the LedBlink() function in Main_9.c:

GpioDataRegs.GPBTOGGLE.bit.GPIO34 = 1; // Toggle the pin

Now delete from the ADCINT_ISR() the code used to implement the interval counter for
the LED toggle (i.e., the GPIO34_count++ loop), and also delete the declaration of the
GPIO34_count itself from the beginning of ADCINT_ISR(). These are no longer
needed, as DSP/BIOS will implement the interval counter for us in the periodic function
configuration (next step in the lab).

TMS320C28x DSP Workshop - Using DSP/BIOS 9 - 19

Lab 9: DSP/BIOS

32. In the configuration file Lab.cdb we need to add and setup the LedBlink_PRD. Open
Lab.cdb and click on the plus sign (+) to the left of Scheduling. Right click on
PRD – Periodic Function Manger and select Insert PRD. PRD0 will be
added. Right-click on it and rename it to LedBlink_PRD.

Select the Properties for LedBlink_PRD and type _LedBlink (with a leading
underscore) in the function field. This tells DSP/BIOS to run the LedBlink() function
when it executes the LedBlink_PRD periodic function object.

Next, in the period (ticks) field type 500. The default DSP/BIOS system timer
increments every 1 millisecond, so what we are doing is telling the DSP/BIOS scheduler
to schedule the LedBlink() function to execute every 500 milliseconds. A PRD object is
just a special type of SWI which gets scheduled periodically and runs in the context of
the SWI level at a specified SWI priority. Click OK. Close the configuration file and
click YES to save changes.

Build and Load

33. Click the “Build” button to rebuild and load the project.

Run the Code – LedBlink_PRD

34. Run the code (real-time mode) by using the GEL function: GEL Æ Realtime
Emulation Control Æ Run_Realtime_with_Reset, and check to see if the
LED on the eZdsp™ is blinking.

35. Record the value shown in the CPU Load Graph under “Case #4” in Table 9-1.

36. When done, fully halt the DSP (real-time mode) by using the GEL function: GEL Æ
Realtime Emulation Control Æ Full_Halt. If you would like, experiment
with different period (tick) values and notice that the blink rate changes.

DSP/BIOS – Real-time Analysis Tools

The DSP/BIOS analysis tools complement the CCS environment by enabling real-time program
analysis of a DSP/BIOS application. You can visually monitor a DSP application as it runs with
essentially no impact on the application’s real-time performance. In CCS, the DSP/BIOS realt-
time analysis (RTA) tools are found on the DSP/BIOS menu. Unlike traditional debugging,
which is external to the executing program, DSP/BIOS program analysis requires that the target
program be instrumented with analysis code. By using DSP/BIOS APIs and objects, developers
automatically instrument the target for capturing and uploading real-time information to CCS
using these tools.

We have actually been already using one piece of the RTA tools in this lab: the CPU Load Graph.
We will now utilize two other basic items from the RTA toolbox.

37. In the next few steps the Log Event Manager will be setup to capture an event in real-
time while the program executes. We will be using LOG_printf() to write to a log

9 - 20 TMS320C28x DSP Workshop - Using DSP/BIOS

 Lab 9: DSP/BIOS

buffer. The LOG_printf() function is a very efficient means of sending a message

from the code to the CCS display. Unlike an ordinary C-language printf(), which can
consume several hundred DSP cycles to format the data on the DSP before transmission
to the CCS host PC, a LOG_printf() transmits the raw data to the host. The host then
formats the data and displays it in CCS. This consumes only 10’s of cycles rather than
100’s of cycles.

Add the following to Main_9.c just after the static local variable declaration in
AdcSwi():

static Uint32 AdcSwi_count=0; // used for LOG_printf

/*** Using LOG_printf() to write to a log buffer ***/

LOG_printf(&trace, "AdcSwi_count = %u", AdcSwi_count++);

38. In the configuration file Lab.cdb we need to add and setup the trace buffer. Open
Lab.cdb and click on the plus sign (+) to the left of Instrumentation and again on
the plus sign (+) to the left of LOG – Event Log Manager.

39. Right click on LOG – Event Log Manager and select Insert LOG. LOG0 will
be added. Right-click on it and rename it to trace.

40. Select the Properties for trace and set the logtype to circular and the datatype to
printf. Click OK. Close the configuration file and click YES to save changes.

41. Since the configuration file was modified, we need to rebuild the project. Click the
“Build” button.

Run the Code – Realtime Analysis Tools

42. Run the code (real-time mode) by using the GEL function: GEL Æ Realtime
Emulation Control Æ Run_Realtime_with_Reset.

43. Open the Message Log. On the menu bar, click:

DSP/BIOS Æ Message Log

The message log dialog box is displaying the commanded LOG_printf() output, i.e. the
number of times (count value) that the AdcSwi() has executed.

44. Verify that all the check boxes in the RTA Control Panel window are still unchecked
(from step 9). Then, check the box marked “Global Host Enable.” This is the main
control switch for most of the RTA tools. We will be selectively enabling the rest of the
check boxes in this portion of the exercise.

45. Record the value shown in the CPU Load Graph under “Case #5” in Table 9-1.

46. Open the Execution Graph. On the menu bar, click:

TMS320C28x DSP Workshop - Using DSP/BIOS 9 - 21

Lab 9: DSP/BIOS

DSP/BIOS Æ Execution Graph

Presently, the execution graph is not displaying anything. This is because we have it
disabled in the RTA Control Panel.

In the RTA Control Panel, check the top four boxes to enable logging of all event types to
the execution graph. Notice that the Execution Graph is now displaying information
about the execution threads being taken by your software. This graph is not based on
time, but the activity of events (i.e. when an event happens, such as a SWI or periodic
function begins execution). Notice that the execution graph simply records DSP/BIOS
CLK events along with other system events (the DSP/BIOS clock periodically triggers
the DSP/BIOS scheduler). As a result, the time scale on the execution graph is not linear.

The logging of events to the execution graph consumes CPU cycles, which is why the
CPU Load Graph jumped as you enabled logging.

47. Record the value shown in the CPU Load Graph under “Case #6” in Table 9-1.

48. Open the Statistics View window. On the menu bar, click:

DSP/BIOS Æ Statistics View

Presently, the statistics view window is not changing with the exception of the statistics
for the IDL_busyObj row (i.e., the idle loop). This is because we have it disabled in the
RTA Control Panel.

In the RTA Control Panel, check the next five boxes (i.e., those with the word
“Accumulator” in their description) to enable logging of statistics to the statistics view
window. The logging of statistics consumes CPU cycles, which is why the CPU Load
Graph jumped as you enabled logging.

49. Record the value shown in the CPU Load Graph under “Case #7” in Table 9-1.

50. Table 9-1 should now be completely filled in. Think about the results. Your instructor
will discuss them when the lecture starts again.

51. Fully halt the DSP (real-time mode) by using the GEL function: GEL Æ Realtime
Emulation Control Æ Full_Halt.

Note: In this module only the basic features of DSP/BIOS and the real-time analysis tools have
been used. For more information and details, please refer to the DSP/BIOS user’s
manuals and other DSP/BIOS related training.

End of Exercise

9 - 22 TMS320C28x DSP Workshop - Using DSP/BIOS

 Lab 9: DSP/BIOS

TMS320C28x DSP Workshop - Using DSP/BIOS 9 - 23

Lab 9: DSP/BIOS

Table 9-2: CPU Computational Burden Results (Solution)

Case # Description CPU Load %

1 ADC processing handled in HWI. Filter inactive. 8

2 Case #1 + filter active. 21

3 ADC processing handled in SWI. Filter active. 46

LED blink handled in HWI.
RTA Global Host Enable disabled.

4 Case #3 + LED blink handled in PRD. 46

5 Case #4 + LOG_printf in SWI. 49

6 Case #5 + RTA SWI Logging enabled. 60

7 Case #6 + RTA SWI Accumulators enabled. 71

9 - 24 TMS320C28x DSP Workshop - Using DSP/BIOS

 System Design

Introduction
This module discusses various aspects of system design. Details of the emulation and analysis
block along with JTAG will be explored. Flash memory programming and the Code Security
Module will be described.

Learning Objectives
Learning Objectives

‹ Emulation and Analysis Block

‹ Flash Configuration and

Memory Performance

‹ Flash Programming

‹ Code Security Module (CSM)

TMS320C28x DSP Workshop - System Design 10 - 1

Module Topics

Module Topics
System Design ...........................................................................................................................................10-1

Module Topics........................................................................................................................................10-2
Emulation and Analysis Block ...............................................................................................................10-3
Flash Configuration and Memory Performance ....................................................................................10-7
Flash Programming .............................................................................................................................10-10
Code Security Module (CSM) ..............................................................................................................10-12
Lab 10: Programming the Flash..........................................................................................................10-16

10 - 2 TMS320C28x DSP Workshop - System Design

 Emulation and Analysis Block

Emulation and Analysis Block

JTAG Emulation System
(based on IEEE 1149.1 Standard)

System Under Test

SCAN IN
Emulator TMS320F2000
Pod

H
E
Some Available Emulators A
D
Signum System JTAGjet-TMS-C2000
E
Spectrum Digital XDS510PP+ TMS320F2000
R
Spectrum Digital XDS510USB
Spectrum Digital PCI
BlackHawk USB
DSP Research PCI / USB / PCMCIA SCAN OUT

Connections Between Emulator and

Vcc Target
Vcc
JTAG Device Emulator Header
13 5
EMU0 EMU0 PD
14
EMU1 EMU1
2 4
TRST TRST GND
1 6
TMS TMS GND
3 8
TDI TDI GND
7 10
TDO TDO GND
11 12
TCK TCK GND
9
TCK_RET
GND

= If distance between device and header is greater than 6 inches

TMS320C28x DSP Workshop - System Design 10 - 3

Emulation and Analysis Block

Multiprocessor Connections
JTAG Device JTAG Device
TDO TDI TDO TDI Vcc

Vcc

EMU0
EMU1

EMU0
EMU1
TRST
TRST

TMS
TMS

TCK
TCK Emulator Header
13 5
EMU0 PD
14
EMU1
2 4
TRST GND
1 6
TMS GND
3 8
TDI GND
7 10
TDO GND
11 12
TCK GND
9 GND
TCK_RET

On-Chip Emulation Analysis Block:

Capabilities
Two hardware analysis units can be configured to provide
any one of the following advanced debug features:

Analysis Configuration Debug Activity

2 Hardware Breakpoints ⇒ Halt on a specified instruction
(for debugging in Flash)

2 Address Watchpoints ⇒ A memory location is getting

corrupted. Halt the processor when
any value is written to this location

1 Address Watchpoint with Data ⇒ Halt program execution after a

specific value is written to a variable

1 Pair Chained Breakpoints ⇒ Halt on a specified instruction only

after some other specific routine has
executed

10 - 4 TMS320C28x DSP Workshop - System Design

 Emulation and Analysis Block

On-Chip Emulation Analysis Block:

Hardware Breakpoints
Symbolic or
numeric address

Mask value for

specifying
address ranges

Chained
breakpoint
selection

On-Chip Emulation Analysis Block:

Watchpoints
Symbolic or
numeric address

Mask value for

specifying
address ranges

Bus selection

Address with Data

selection

TMS320C28x DSP Workshop - System Design 10 - 5

Emulation and Analysis Block

On-Chip Emulation Analysis Block:

Online Stack Overflow Detection
‹ Emulation analysis registers are accessible to code as well!
‹ Configure a watchpoint to monitor for writes near the end of
the stack
‹ Watchpoint triggers maskable RTOSINT interrupt
‹ Works with DSP/BIOS and non-DSP/BIOS
Š See TI application report SPRA820 for implementation details

Region of Stack grows

memory towards higher
occupied memory
by the addresses
stack Monitor for data
writes in region near
the end of the stack
Data Memory

10 - 6 TMS320C28x DSP Workshop - System Design

 Flash Configuration and Memory Performance

Flash Configuration and Memory Performance

Basic Flash Operation
‹ Flash is arranged in pages of 2048 bits
‹ Wait states are specified for consecutive accesses within a page,
and random accesses across pages
‹ OTP has random access only
‹ Must specify the number of SYSCLKOUT wait-states;
Reset defaults are maximum values
‹ Flash configuration code should not be run from the Flash memory
15 12 11 8 7 4 3 0

FlashRegs.FBANKWAIT reserved PAGEWAIT reserved RANDWAIT

15 4 3 0

FlashRegs.FOTPWAIT reserved OTPWAIT

*** Refer to the F280x datasheet for detailed numbers ***

For 100 MHz, PAGEWAIT = 3, RANDWAIT = 3, OTPWAIT = 5

Speeding Up Code Execution in Flash:

Flash Pipelining (for code fetch only)

16

16 or 32
64 dispatched
64 C28x Core
decoder unit
Aligned 2-level deep
64-bit fetch buffer
fetch
Flash Pipeline Enable
0 = disable (default)
1 = enable

FlashRegs.FOPT.bit.ENPIPE = 1;
15 1 0
reserved ENPIPE

TMS320C28x DSP Workshop - System Design 10 - 7

Flash Configuration and Memory Performance

Other Flash Configuration Registers

FlashRegs.name
Address Name Description
0x00 0A80 FOPT Flash option register
0x00 0A82 FPWR Flash power modes registers
0x00 0A83 FSTATUS Flash status register
0x00 0A84 FSTDBYWAIT Flash sleep to standby wait register
0x00 0A85 FACTIVEWAIT Flash standby to active wait register
0x00 0A86 FBANKWAIT Flash read access wait state register
0x00 0A87 FOTPWAIT OTP read access wait state register
‹ FPWR: Save power by putting Flash/OTP to ‘Sleep’ or ‘Standby’
mode; Flash will automatically enter active mode if a Flash/OTP
access is made
‹ FSTATUS: Various status bits (e.g. PWR mode)
‹ FSTDBYWAIT: Specify number of cycles to wait during wake-up
from sleep to standby
‹ FACTIVEWAIT: Specify number of cycles to wait during wake-up
from standby to active
Defaults for these registers are often sufficient – See “TMS320F28x DSP
System Control and Interrupts Reference Guide,” SPRU078, for more information

Code Execution Performance

‹ Assume 100 MHz SYSCLKOUT, 16-bit instructions

(80% of instructions are 16 bits wide – Rest are 32 bits)

Internal RAM: 100 MIPS

Fetch up to 32-bits every cycle Î 1 instruction/cycle * 100 MHz = 100 MIPS

Flash (w/ pipelining): 100 MIPS

RANDWAIT = 3
Fetch 64 bits every 4 cycles Î 4 instructions/4 cycles * 100 MHz = 100 MIPS
RPT will increase this; PC discontinuities and 32 bit instructions will degrade this
Benchmarking in control applications has shown actual performance of about 85 MIPS

10 - 8 TMS320C28x DSP Workshop - System Design

 Flash Configuration and Memory Performance

Data Access Performance

‹ Assume 100 MHz SYSCLKOUT (CPU clock)

Memory 16-bit access 32-bit access Notes

(words/cycle) (words/cycle)

Internal RAM 1 1

Flash 0.25 0.25 RANDWAIT = 3

Flash is read only!

‹ Flash performance usually sufficient for most constants and tables

‹ Use internal RAM for time-critical constants
‹ The performance executing from Flash (as discussed on the
pervious slide) will be reduced when that code accesses data
located in Flash

TMS320C28x DSP Workshop - System Design 10 - 9

Flash Programming

Flash Programming
Flash Programming Basics
‹ The DSP CPU itself performs the flash programming
‹ The CPU executes Flash utility code from RAM that reads the
Flash data and writes it into the Flash
‹ We need to get the Flash utility code and the Flash data into RAM

FLASH CPU

Flash
Utility
Code Emulator JTAG
RAM
RS232 SCI

SPI

Bootloader
ROM
Flash I2C
Data
eCAN

GPIO
F280x DSP

Flash Programming Basics

‹ Sequence of steps for Flash programming:

Algorithm Function
1. Erase - Set all bits to zero, then to one
2. Program - Program selected bits with zero
3. Verify - Verify flash contents

‹ Minimum Erase size is a sector (4Kw/8Kw/16Kw)

‹ Minimum Program size is a bit!
‹ Important not to lose power during erase step:
If CSM passwords happen to be all zeros, the
CSM will be permanently locked!
‹ Chance of this happening is quite small! (Erase
step is performed sector by sector)

10 - 10 TMS320C28x DSP Workshop - System Design

 Flash Programming

Flash Programming Utilities

‹ Code Composer Studio Plug-in (uses JTAG)

‹ Third-party JTAG utilities
Š SDFlash JTAG from Spectrum Digital (requires SD emulator)
Š Signum System Flash utilities (requires Signum emulator)
‹ SDFlash Serial utility (uses SCI boot)
‹ Gang Programmers (use GPIO boot)
Š BP Micro programmer
Š Data I/O programmer
‹ Build your own custom utility
Š Use a different ROM bootloader method than SCI
Š Embed flash programming into your application
Š Flash API algorithms provided by TI

* TI web has links to all utilities (http://www.ti.com/c2000)

Code Composer Studio Flash Plug-In

TMS320C28x DSP Workshop - System Design 10 - 11

Code Security Module (CSM)

Code Security Module (CSM)

Code Security Module (CSM)
‹ Access to the following on-chip memory is
restricted:
0x00 8000 LO SARAM (4Kw)
0x00 9000 L1 SARAM (4Kw)
0x00 A000
0x00 C000 reserved
0x3D 7800 OTP (1Kw) Dual
0x3D 7C00 reserved Mapped
0x3E 8000 FLASH (64Kw)
0x3F 7FF8 128-Bit Password
0x3F 8000 LO SARAM (4Kw)
0x3F 9000 L1 SARAM (4Kw)

‹ Data reads and writes from restricted memory

are only allowed for code running from
restricted memory
‹ All other data read/write accesses are blocked:
JTAG emulator/debugger, ROM bootloader, code running in
external memory or unrestricted internal memory

CSM Password

0x3E 8000

FLASH (64Kw) CSM Password

Locations (PWL)
0x3F 7FF8 0x3F 7FF8 - 0x3F 7FFF
128-Bit Password

‹ 128-bit user defined password is stored in Flash

‹ 128-bit Key Register used to lock and unlock the

device
Š Mapped in memory space 0x00 0AE0 – 0x00 0AE7
Š Register “EALLOW” protected

10 - 12 TMS320C28x DSP Workshop - System Design

 Code Security Module (CSM)

CSM Registers
Key Registers – accessible by user; EALLOW protected
Address Name Reset Value Description
0x00 0AE0 KEY0 0xFFFF Low word of 128-bit Key register
0x00 0AE1 KEY1 0xFFFF 2nd word of 128-bit Key register
0x00 0AE2 KEY2 0xFFFF 3rd word of 128-bit Key register
0x00 0AE3 KEY3 0xFFFF 4th word of 128-bit Key register
0x00 0AE4 KEY4 0xFFFF 5th word of 128-bit Key register
0x00 0AE5 KEY5 0xFFFF 6th word of 128-bit Key register
0x00 0AE6 KEY6 0xFFFF 7th word of 128-bit Key register
0x00 0AE7 KEY7 0xFFFF High word of 128-bit Key register
0x00 0AEF CSMSCR 0xFFFF CSM status and control register
PWL in memory – reserved for passwords only
Address Name Reset Value Description
0x3F 7FF8 PWL0 user defined Low word of 128-bit password
0x3F 7FF9 PWL1 user defined 2nd word of 128-bit password
0x3F 7FFA PWL2 user defined 3rd word of 128-bit password
0x3F 7FFB PWL3 user defined 4th word of 128-bit password
0x3F 7FFC PWL4 user defined 5th word of 128-bit password
0x3F 7FFD PWL5 user defined 6th word of 128-bit password
0x3F 7FFE PWL6 user defined 7th word of 128-bit password
0x3F 7FFF PWL7 user defined High word of 128-bit password

Locking and Unlocking the CSM

‹ The CSM is locked at power-up and reset

‹ To unlock the CSM:
Š Perform a dummy read of each password in
the Flash
Š Write the correct passwords to the key
registers
‹ New Flash Devices (PWL are all 0xFFFF):
Š When all passwords are 0xFFFF – only a
read of the PWL is required to bring the
device into unlocked mode

TMS320C28x DSP Workshop - System Design 10 - 13

Code Security Module (CSM)

CSM Caveats
‹ Never program all the PWL’s as 0x0000
Š Doing so will permanently lock the CSM
‹ Flash addresses 0x3F7F80 to 0x3F7FF5,
inclusive, must be programmed to 0x0000 to
securely lock the CSM
‹ Remember that code running in unsecured
RAM cannot access data in secured memory
Š Don’t link the stack to secured RAM if you have
any code that runs from unsecured RAM
‹ Do not embed the passwords in your code!
Š Generally, the CSM is unlocked only for debug
Š Code Composer Studio can do the unlocking

CSM Password Match Flow

Device permanently locked

Start Is PWL = Yes
CPU access is limited –
all 0s? device cannot be debugged
or reprogrammed
No
Flash device
secure after Yes
reset or runtime Is PWL =
all Fs?
No
Do dummy read of PWL Write password to KEY registers
0x3F 7FF8 – 0x3F 7FFF 0x00 0AE0 – 0x00 0AE7
(EALLOW) protected

Device unlocked
Correct Yes
password? User can access on-
chip secure memory
No

10 - 14 TMS320C28x DSP Workshop - System Design

 Code Security Module (CSM)

CSM C-Code Examples

Unlocking the CSM:
volatile int *PWL = &CsmPwl.PSWD0; //Pointer to PWL register file
volatile int i, tmp;

for (i = 0; i<8; i++) tmp = *PWL++; //Dummy reads of PWL locations

asm (” EALLOW”); //KEY regs are EALLOW protected

CsmRegs.KEY0 = PASSWORD0; //Write the passwords
CsmRegs.KEY1 = PASSWORD1; //to the Key registers
CsmRegs.KEY2 = PASSWORD2;
CsmRegs.KEY3 = PASSWORD3;
CsmRegs.KEY4 = PASSWORD4;
CsmRegs.KEY5 = PASSWORD5;
CsmRegs.KEY6 = PASSWORD6;
CsmRegs.KEY7 = PASSWORD7;
asm (” EDIS”);

Locking the CSM:

asm(” EALLOW”); //CSMSCR reg is EALLOW protected
CsmRegs.CSMSCR.bit.FORCESEC = 1; //Set FORCESEC bit
asm (” EDIS”);

TMS320C28x DSP Workshop - System Design 10 - 15

Lab 10: Programming the Flash

Lab 10: Programming the Flash

¾ Objective

The objective of this lab is to use the techniques discussed in module 10 and program the on-chip
flash memory. The TMS320F2808 device has been designed for standalone operation in an
embedded system. Using the on-chip flash eliminates the need for external non-volatile memory
or a host processor from which to bootload. In this lab, the steps required to properly configure
the software for execution from internal flash memory will be covered.

Lab 10: Programming the Flash

ePWM1 ADC
TB Counter ADCINA0 RESULT0 IQmath
Compare
Action Qualifier FIR Filter
connector
wire

ePWM2 triggering ADC on

period match using SOC A data
trigger every 20 µs (50 kHz) memory
ePWM2

Objective: pointer rewind CPU copies

result to
‹ Program system into Flash buffer during

...
ADC ISR
Memory
‹ Learn use of CCS Flash
Plug-in Display
using CCS
‹ DO NOT PROGRAM
PASSWORDS

¾ Procedure

Project File

Note: LAB10 files have been provided as a starting point for the lab and need to be
completed. DO NOT copy files from a previous lab.

1. A project named Lab10.pjt has been created for this lab. Open the project by
clicking on Project Æ Open… and look in C:\C28x\Labs\Lab10. All Build
Options have been configured like the previous lab. The files used in this lab are:

10 - 16 TMS320C28x DSP Workshop - System Design

 Lab 10: Programming the Flash

Main_10.c Labcfg.cmd
Lab.cdb DSP280x_Headers_BIOS.cmd
User_10.cmd CodeStartBranch.asm
SysCtrl.c Gpio.c
DSP280x_GlobalVariableDefs.c PieCtrl_10.c
DefaultIsr_10.c Adc.c
EPwm_7_8_9_10.c ECap_7_8_9_10.c
Filter.c DelayUs.asm

Link Initialized Sections to Flash

Initialized sections, such as code and constants, must contain valid values at device power-up.
For a stand-alone embedded system with the F2808 device, these initialized sections must be
linked to the on-chip flash memory. Note that a stand-alone embedded system must operate
without an emulator or debugger in use, and no host processor is used to perform bootloading.

Each initialized section actually has two addresses associated with it. First, it has a LOAD
address which is the address to which it gets loaded at load time (or at flash programming time).
Second, it has a RUN address which is the address from which the section is accessed at runtime.
The linker assigns both addresses to the section. Most initialized sections can have the same
LOAD and RUN address in the flash. However, some initialized sections need to be loaded to
flash, but then run from RAM. This is required, for example, if the contents of the section needs
to be modified at runtime by the code.

2. This step assigns the RUN address of those sections that need to run from flash. Using
the memory section manager in the DSP/BIOS configuration tool (Lab.cdb) link the
following sections to on-chip flash memory:

BIOS Data tab BIOS Code tab Compiler Sections tab

.gblinit .bios .text

.sysinit .switch

.hwi .cinit

.rtdx_text .pinit

.econst / .const

.data

3. This step assigns the LOAD address of those sections that need to load to flash. Again
using the memory section manager in the DSP/BIOS configuration tool (Lab.cdb),
select the Load Address tab and check the “Specify Separate Load
Addresses” box. Then set all entries to the flash memory block.

TMS320C28x DSP Workshop - System Design 10 - 17

Lab 10: Programming the Flash

4. The section named “IQmath” is an initialized section that needs to load to and run from
flash. Recall that this section is not linked using the DSP/BIOS configuration tool
(Lab.cdb). Instead, this section is linked with the user linker command file
(User_10.cmd). Open and inspect User_10.cmd. Previously the “IQmath”
section was linked to H0SARAM. Notice that this section is now linked to FLASH.

Copying .hwi_vec Section from Flash to RAM

The DSP/BIOS .hwi_vec section contains the interrupt vectors. This section must be loaded to
flash (load address) but run from RAM (run address). The code that performs this copy is located
in InitPieCtrl(). The DSP/BIOS configuration tool generates global symbols that can be accessed
by code in order to determine the load address, run address, and length of the .hwi_vec section.
The C-compiler runtime support library contains a memory copy function called memcpy() which
will be used to perform the copy.

5. Open and inspect InitPieCtrl() (in PieCtrl_10.c file). Notice the memcpy() function
and the symbols used to initialize (copy) the .hwi_vec section.

Copying the .trcdata Section from Flash to RAM

The DSP/BIOS .trcdata section is used by CCS and DSP/BIOS for certain real-time debugging
features. This section must be loaded to flash (load address) but run from RAM (run address).
The DSP/BIOS configuration tool generates global symbols that can be accessed by code in order
to determine the load address, run address, and length of the .trcdata section. The memory copy
function memcpy() will again be used to perform the copy.

The copying of .trcdata must be performed prior to main(). This is because DSP/BIOS modifies
the contents of .trcdata during DSP/BIOS initialization, which also occurs prior to main(). The
DSP/BIOS configuration tool provides a user initialization function which will be used to
perform the .trcdata section copy prior to both main() and DSP/BIOS initialization.

6. Open the DSP/BIOS configuration file (Lab.cdb) and select the Properties for the
Global Settings. Check the box “Call User Init Function” and enter
the UserInit() function name with a leading underscore: _UserInit. This will
cause the function UserInit() to execute prior to main().

7. Open and inspect the file Main_10.c. Notice that the function UserInit() is used
to copy the .trcdata section from its load address to its run address before main().

Initializing the Flash Control Registers

The initialization code for the flash control registers cannot execute from the flash memory (since
it is changing the flash configuration!). Therefore, the initialization function for the flash control
registers must be copied from flash (load address) to RAM (run address) at runtime. The memory
copy function memcpy() will again be used to perform the copy. The initialization code for the
flash control registers InitFlash() is located in the Flash.c file.

8. Add Flash.c to the project.

10 - 18 TMS320C28x DSP Workshop - System Design

 Lab 10: Programming the Flash

9. Open and inspect Flash.c. The C compiler CODE_SECTION pragma is used to place
the InitFlash() function into a linkable section named “secureRamFuncs”.

10. Since the DSP/BIOS configuration tool does not know about user defined sections, the
“secureRamFuncs” section will be linked using the user linker command file
User_10.cmd. Open and inspect User_10.cmd. The “secureRamFuncs” will
load to flash (load address) but will run from L1SARAM (run address). Also notice that
the linker has been asked to generate symbols for the load start, load end, and run start
addresses.

While not a requirement from a DSP hardware perspective (since the C28x DSP has a
unified memory architecture), Code Composer Studio generally prefers code to be linked
to program space (and data to be linked to data space). Therefore, notice that for the
L1SARAM memory we are linking “secureRamFuncs” to, we are specifiying
“PAGE = 0”(which is program space). The L1SARAM memory is currently defined in
data space in the Lab.cdb, but in the next step we will redefine it to exist in the
program space.

11. Using the DSP/BIOS configuration tool (Lab.cdb) modify the entry for L1SARAM so
that it is defined in the program space (code).

12. Open and inspect Main_10.c. Notice that the memory copy function memcpy() is
being used to copy the section “secureRamFuncs, which contains the initialization
function for the flash control registers.

13. Add a line of code to main() to call the InitFlash() function. There are no passed
parameters or return values. You just type

InitFlash();

at the desired spot in main().

Code Security Module and Passwords

The CSM module provides protection against unwanted copying (i.e. pirating!) of your code from
flash, OTP memory, and the L0 and L1 RAM blocks. The CSM uses a 128-bit password made
up of 8 individual 16-bit words. They are located in flash at addresses 0x3F7FF8 to 0x3F7FFF.
During this lab, dummy passwords of 0xFFFF will be used – therefore only dummy reads of the
password locations are needed to unsecure the CSM. DO NOT PROGRAM ANY REAL
PASSWORDS INTO THE DEVICE. After development, real passwords are typically placed in
the password locations to protect your code. We will not be using real passwords in the
workshop.

The CSM module also requires programming values of 0x0000 into flash addresses 0x3F7F80
through 0x3F7FF5 in order to properly secure the CSM. Both tasks will be accomplished using a
simple assembly language program Passwords.asm.

14. Add Passwords.asm to your CCS project.

TMS320C28x DSP Workshop - System Design 10 - 19

Lab 10: Programming the Flash

15. Open and inspect Passwords.asm. This file specifies the desired password values
(DO NOT CHANGE THE VALUES FROM 0xFFFF) and places them in an initialized
section named “passwords”. It also creates an initialized section named
“csm_rsvd” which contains all 0x0000 values for locations 0x3F7F80 to 0x3F7FF5
(length of 0x76).

16. Open User_10.cmd and notice that the initialized sections for “passwords” and
“csm_rsvd” are linked to memories named PASSWORDS and CSM_RSVD,
respectively.

17. Using the DSP/BIOS configuration tool (Lab.cdb) define memory blocks for
PASSWORDS and CSM_RSVD. You will need to setup the MEM Properties for each
memory block with the proper base address and length. Set the space to code for both
memory blocks. (Uncheck the “create a heap in this memory” box for each block). You
may also need to modify the existing flash memory block to avoid conflicts. If needed, a
slide is available at the end of this lab showing the base address and length for the
memory blocks.

Executing from Flash after Reset

The F2808 device contains a ROM bootloader that will transfer code execution to the flash after
reset. When the boot mode selection pins are set for “Jump to Flash” mode, the bootloader will
branch to the instruction located at address 0x3F7FF6 in the flash. An instruction that branches
to the beginning of your program needs to be placed at this address. Note that the CSM
passwords begin at address 0x3F7FF8. There are exactly two words available to hold this branch
instruction, and not coincidentally, a long branch instruction “LB” in assembly code occupies
exactly two words. Generally, the branch instruction will branch to the start of the C-
environment initialization routine located in the C-compiler runtime support library. The entry
symbol for this routine is _c_int00. Recall that C code cannot be executed until this setup routine
is run. Therefore, assembly code must be used for the branch. We are using the assembly code
file named CodeStartBranch.asm.

18. Open and inspect CodeStartBranch.asm. This file creates an initialized section
named “codestart” that contains a long branch to the C-environment setup routine.
This section needs to be placed in memory using the DSP/BIOS configuration tool.

19. Using the DSP/BIOS configuration tool (Lab.cdb) define a memory space named
BEGIN_FLASH.

20. Setup the MEM Properties with the proper base address, length, and space.
(Uncheck the “create a heap in this memory” box). Be sure to avoid memory section
conflicts. If needed, a slide is available at the end of this lab showing the base address
and length for the memory block.

21. In the earlier lab exercises, the section “codestart” was directed to the memory
named BEGIN_M0. Open and modify User_10.cmd so that the section
“codestart” will be directed to BEGIN_FLASH.

22. The eZdsp™ board needs to be configured for “Jump to Flash” bootmode. Move switch
SW1 positions 1, 2 and 3 to the “open” position to accomplish this. Details of switch

10 - 20 TMS320C28x DSP Workshop - System Design

 Lab 10: Programming the Flash

positions can be found in Appendix A. This switch controls the pullup/down resistor on
the GPIO18, GPIO29, and GPIO34 pins, which are the pins sampled by the bootloader to
determine the bootmode. (For additional information on configuring the “Jump to Flash”
bootmode see the TMS320x280x DSP Boot ROM Reference Guide, and also the eZdsp
F2808 Technical Reference).

Build – Lab.out
23. At this point we need to build the project, but not have CCS automatically load it since
CCS cannot load code into the flash! (the flash must be programmed). On the menu bar
click: Option Æ Customize… and select the “Program/Project Load” tab.
Uncheck “Load Program After Build”.

CCS has a feature that automatically steps over functions without debug information.
This can be useful for accelerating the debug process provided that you are not interested
in debugging the function that is being stepped-over. While single-stepping in this lab
exercise we do not want to step-over any functions. Therefore, select the “Debug
Properties” tab. Uncheck “Step over functions without debug
information when source stepping”, then click OK.

24. Click the “Build” button to generate the Lab.out file to be used with the CCS Flash
Plug-in.

CCS Flash Plug-in

25. Open the Flash Plug-in tool by clicking :

Tools Æ F28xx On-Chip Flash Programmer

26. Notice that the eZdsp™ board uses a 20 MHz oscillator (located on the board near LED
DS2). Confirm the “Clock Configuration” in the upper left corner has the OSCCLK set
to 20 MHz and the PLLCR value is set to 10. Recall that the PLL is divided by two,
which gives a SYSCLKOUT of 100 MHz.

27. Confirm that all boxes are checked in the “Erase Sector Selection” area of the plug-in
window. We want to erase all the flash sectors.

28. We will not be using the plug-in to program the “Code Security Password”. Do not
modify the Code Security Password fields.

29. In the “Operation” block, notice that the “COFF file to Program/Verify” field
automatically defaults to the current .out file. Check to be sure that “Erase, Program,
Verify” is selected. We will be using the default wait states, as shown on the slide in this
module.

30. Click “Execute Operation” to program the flash memory. Watch the programming status
update in the plug-in window.

31. After successfully programming the flash memory, close the programmer window.

TMS320C28x DSP Workshop - System Design 10 - 21

Lab 10: Programming the Flash

Running the Code – Using CCS

32. In order to effectively debug with CCS, we need to load the symbolic debug information
(e.g., symbol and label addresses, source file links, etc.) so that CCS knows where
everything is in your code. Click:

File Æ Load Symbols Æ Load Symbols Only…

and select Lab10.out in the Debug folder.

33. Reset the DSP. The program counter should now be at 0x3FFB50, which is the start of
the bootloader in the Boot ROM.

34. Single-Step <F11> through the bootloader code until you arrive at the beginning of the
codestart section in the CodeStartBranch.asm file. (Be patient, it will take about
65 single-steps). Notice that we have placed some code in CodeStartBranch.asm
to give an option to first disable the watchdog, if selected.

35. Step a few more times until you reach the start of the C-compiler initialization routine at
the symbol _c_int00.

36. Now do Debug Æ Go Main. The code should stop at the beginning of your main()
routine. If you got to that point succesfully, it confirms that the flash has been
programmed properly, and that the bootloader is properly configured for jump to flash
mode, and that the codestart section has been linked to the proper address.

37. You can now RUN the DSP, and you should observe the LED on the board blinking. Try
resetting the DSP and hitting RUN (without doing all the stepping and the Go Main
procedure). The LED should be blinking again.

Running the Code – Stand-alone Operation (No Emulator)

38. Close Code Composer Studio.

39. Disconnect the emulator (USB cable) from the eZdsp™ board.

40. Remove the power from the board.

41. Re-connect the power to the board.

42. The LED should be blinking, showing that the code is now running from flash memory.

10 - 22 TMS320C28x DSP Workshop - System Design

 Lab 10: Programming the Flash

Return Switch SW1 Back to Default Positions

43. Remove the power from the board.

44. Please return the settings of switch SW1 back to the default positions “Jump to
M0SARAM” bootmode (see Appendix A for switch position details):

Position 3 Position 2 Position 1 Boot

GPIO18 GPIO29 GPIO34 Mode

Closed – 0 Open – 1 Closed – 0 MO SARAM

End of Exercise

TMS320C28x DSP Workshop - System Design 10 - 23

Lab 10: Programming the Flash

Lab 10 Reference: Programming the Flash

Flash Memory Section Blocks

base =
0x3E 8000
FLASH
len = 0xFF80
space = code User_10.cmd
SECTIONS
{
0x3F 7F80 codestart :> BEGIN_FLASH, PAGE = 0
CSM_RSVD
len = 0x76 passwords :> PASSWORDS, PAGE = 0
space = code csm_rsvd :> CSM_RSVD, PAGE = 0
0x3F 7FF6
BEGIN_FLASH }
len = 0x2
space = code
0x3F 7FF8 PASSWORDS
len = 0x8
space = code

BIOS Startup Sequence from Flash Memory

BIOS code Sections

0x3E 8000 _c_int00 BIOS_reset( )
FLASH (64Kw) BIOS_init( )
main ( )
4
BIOS_start( )
0x3F 7FF6 LB
7
_c_int00
IDL_run( )
Passwords (8w) 5
0x3F 8000 “rts2800_ml.lib”
H0 SARAM (8Kw)
6
3 “user” code sections
main ( )
0x3F F000 Boot ROM (4Kw) {
Boot Code ……
0x3F FB50
return;
{SCAN GPIO}
2 }
BROM vector (32w)
0x3F FFC0 0x3F FB50
1

RESET

10 - 24 TMS320C28x DSP Workshop - System Design

 Communications

Introduction
The TMS320C28x contains features that allow several methods of communication and data
exchange between the C28x and other devices. Many of the most commonly used
communications techniques are presented in this module.

The intent of this module is not to give exhaustive design details of the communication
peripherals, but rather to provide an overview of the features and capabilities. Once these
features and capabilities are understood, additional information can be obtained from various
resources such as documentation, as needed. This module will cover the basic operation of the
communication peripherals, as well as some basic terms and how they work.

Learning Objectives
Learning Objectives

‹ Serial Peripheral Interface (SPI)

‹ Serial Communication Interface (SCI)
‹ Inter-Integrated Circuit (I2C)
‹ Enhanced Controller Area Network (eCAN)

Note: Up to 4 SPI modules (A/B/C/D), 2 SCI modules (A/B), 1 I2C

modules, and 2 eCAN (A/B) modules are available on the
F280x devices.

TMS320C28x DSP Workshop - Communications 11 - 1

Module Topics

Module Topics
Communications.......................................................................................................................................11-1

Module Topics........................................................................................................................................11-2
Communications Techniques .................................................................................................................11-3
Serial Peripheral Interface (SPI) ...........................................................................................................11-4
SPI Registers .....................................................................................................................................11-7
SPI Summary.....................................................................................................................................11-8
Serial Communications Interface (SCI) .................................................................................................11-9
Multiprocessor Wake-Up Modes.....................................................................................................11-11
SCI Registers ...................................................................................................................................11-14
SCI Summary ..................................................................................................................................11-15
Inter-Integrated Circuit (I2C)..............................................................................................................11-16
I2C Operating Modes and Data Formats .........................................................................................11-17
I2C Summary...................................................................................................................................11-18
Enhanced Controller Area Network (eCAN) .......................................................................................11-19
CAN Bus and Node .........................................................................................................................11-20
Principles of Operation....................................................................................................................11-21
Message Format and Block Diagram...............................................................................................11-22
eCAN Summary ..............................................................................................................................11-23

11 - 2 TMS320C28x DSP Workshop - Communications

 Communications Techniques

Communications Techniques
Several methods of implementing a TMS320C28x communications system are possible. The
method selected for a particular design should reflect the method that meets the required data rate
at the lowest cost. Various categories of interface are available and are summarized in the
learning objective slide. Each will be described in this module.

Synchronous vs. Asynchronous

‹ Synchronous ‹ Asynchronous
Š Short distances (on- Š longer distances
board) Š Lower data rate ( ≈ 1/8 of
SPI)
Š High data rate Š Implied clock (clk/data
Š Explicit clock mixed)
Š Economical with
reasonable performance

C28x C28x

Port U2 Port
Destination

PCB PCB

Serial ports provide a simple, hardware-efficient means of high-level communication between

devices. Like the GPIO pins, they may be used in stand-alone or multiprocessing systems.

In a multiprocessing system, they are an excellent choice when both devices have an available
serial port and the data rate requirement is relatively low. Serial interface is even more desirable
when the devices are physically distant from each other because the inherently low number of
wires provides a simpler interconnection.

Serial ports require separate lines to implement, and they do not interfere in any way with the data
and address lines of the processor. The only overhead they require is to read/write new words
from/to the ports as each word is received/transmitted. This process can be performed as a short
interrupt service routine under hardware control, requiring only a few cycles to maintain.

The C28x family of devices have both synchronous and asynchronous serial ports. Detailed
features and operation will be described next.

TMS320C28x DSP Workshop - Communications 11 - 3

Serial Peripheral Interface (SPI)

Serial Peripheral Interface (SPI)

The SPI module is a synchronous serial I/O port that shifts a serial bit stream of variable length
and data rate between the C28x and other peripheral devices. During data transfers, one SPI
device must be configured as the transfer MASTER, and all other devices configured as
SLAVES. The master drives the transfer clock signal for all SLAVES on the bus. SPI
communications can be implemented in any of three different modes:

• MASTER sends data, SLAVES send dummy data

• MASTER sends data, one SLAVE sends data

• MASTER sends dummy data, one SLAVE sends data

In its simplest form, the SPI can be thought of as a programmable shift register. Data is shifted in
and out of the SPI through the SPIDAT register. Data to be transmitted is written directly to the
SPIDAT register, and received data is latched into the SPIBUF register for reading by the CPU.
This allows for double-buffered receive operation, in that the CPU need not read the current
received data from SPIBUF before a new receive operation can be started. However, the CPU
must read SPIBUF before the new operation is complete of a receiver overrun error will occur. In
addition, double-buffered transmit is not supported: the current transmission must be complete
before the next data character is written to SPIDAT or the current transmission will be corrupted.

The Master can initiate a data transfer at any time because it controls the SPICLK signal. The
software, however, determines how the Master detects when the Slave is ready to broadcast.

SPI Data Flow

‹ Simultaneous transmits and receive

‹ SPI Master provides the clock signal

SPI Device #1 - Master SPI Device #2 - Slave

shift shift

SPI
SPIShift
ShiftRegister
Register SPI
SPIShift
ShiftRegister
Register

clock

11 - 4 TMS320C28x DSP Workshop - Communications

 Serial Peripheral Interface (SPI)

SPI Block Diagram

C28x - SPI Master Mode Shown
SPISIMO
RX FIFO_0

RX FIFO_15
SPIRXBUF.15-0

MSB LSB
SPIDAT.15-0 SPISOMI

SPITXBUF.15-0
TX FIFO_0

TX FIFO_15

LSPCLK baud clock clock SPICLK

rate polarity phase

SPI Transmit / Receive Sequence

1. Slave writes data to be sent to its shift register (SPIDAT)

2. Master writes data to be sent to its shift register (SPIDAT or SPITXBUF)

3. Completing Step 2 automatically starts SPICLK signal of the Master

4. MSB of the Master’s shift register (SPIDAT) is shifted out, and LSB of the Slave’s shift
register (SPIDAT) is loaded

5. Step 4 is repeated until specified number of bits are transmitted

6. SPIDAT register is copied to SPIRXBUF register

7. SPI INT Flag bit is set to 1

8. An interrupt is asserted if SPI INT ENA bit is set to 1

9. If data is in SPITXBUF (either Slave or Master), it is loaded into SPIDAT and transmission
starts again as soon as the Master’s SPIDAT is loaded

TMS320C28x DSP Workshop - Communications 11 - 5

Serial Peripheral Interface (SPI)

Since data is shifted out of the SPIDAT register MSB first, transmission characters of less than 16
bits must be left-justified by the CPU software prior to be written to SPIDAT.

Received data is shifted into SPIDAT from the left, MSB first. However, the entire sixteen bits
of SPIDAT is copied into SPIBUF after the character transmission is complete such that received
characters of less than 16 bits will be right-justified in SPIBUF. The non-utilized higher
significance bits must be masked-off by the CPU software when it interprets the character. For
example, a 9 bit character transmission would require masking-off the 7 MSB’s.

SPI Data Character Justification

‹ Programmable data
length of 1 to 16 bits
‹ Transmitted data of less SPIDAT - Processor #1
than 16 bits must be left 11001001XXXXXXXX
justified 11001001XXXXXXXX
ŠMSB transmitted first

‹ Received data of less

than 16 bits are right
justified SPIDAT - Processor #2
XXXXXXXX11001001
XXXXXXXX11001001
‹ User software must
mask-off unused MSB’s

11 - 6 TMS320C28x DSP Workshop - Communications

 Serial Peripheral Interface (SPI)

SPI Registers
SPI Baud Rate Register
SpixRegs.SPIBRR

Need to set this only when in master mode!

15-7 6-0
reserved SPI BIT RATE

LSPCLK
, SPIBRR = 3 to 127
(SPIBRR + 1)
SPICLK signal =
LSPCLK
, SPIBRR = 0, 1, or 2
4

Baud Rate Determination: The Master specifies the communication baud rate using its baud rate
register (SPIBRR.6-0):

LSPCLK
• For SPIBRR = 3 to 127: SPI Baud Rate = bits/sec
( SPIBRR + 1)

LSPCLK
• For SPIBRR = 0, 1, or 2: SPI Baud Rate = bits/sec
4

From the above equations, one can compute

Maximum data rate = 25 Mbps @ 100 MHz

Character Length Determination: The Master and Slave must be configured for the same
transmission character length. This is done with bits 0, 1, 2 and 3 of the configuration control
register (SPICCR.3-0). These four bits produce a binary number, from which the character length
is computed as binary + 1 (e.g. SPICCR.3-0 = 0010 gives a character length of 3).

TMS320C28x DSP Workshop - Communications 11 - 7

Serial Peripheral Interface (SPI)

Select SPI Registers

‹ Configuration Control SpixRegs.SPICCR
Š Reset, Clock Polarity, Loopback, Character Length

‹ Operation Control SpixRegs.SPICTL

Š Overrun Interrupt Enable, Clock Phase, Interrupt Enable
Š Master / Slave Transmit enable

‹ Status SpixRegs.SPIST
Š RX Overrun Flag, Interrupt Flag, TX Buffer Full Flag

‹ FIFO Transmit SpixRegs.SPIFFTX

FIFO Receive SpixRegs.SPIFFRX
Š FIFO Enable, FIFO Reset
Š FIFO Over-flow flag, Over-flow Clear
Š Number of Words in FIFO (FIFO Status)
Š FIFO Interrupt Enable, Interrupt Status, Interrupt Clear
Š FIFO Interrupt Level (Number of Words in FIFO)

Note: refer to the reference guide for a complete listing of registers

SPI Summary
SPI Summary
‹ Provides synchronous serial
communications
Š Two wire transmit or receive (half duplex)
Š Three wire transmit and receive (full duplex)
‹ Software configurable as master or slave
Š C28x provides clock signal in master mode
‹ Data length programmable from 1-16 bits
‹ 125 different programmable baud rates

11 - 8 TMS320C28x DSP Workshop - Communications

 Serial Communications Interface (SCI)

Serial Communications Interface (SCI)

The SCI module is a serial I/O port that permits Asynchronous communication between the C28x
and other peripheral devices. The SCI transmit and receive registers are both double-buffered to
prevent data collisions and allow for efficient CPU usage. In addition, the C28x SCI is a full
duplex interface which provides for simultaneous data transmit and receive. Parity checking and
data formatting is also designed to be done by the port hardware, further reducing software
overhead.

SCI Pin Connections

(Full Duplex Shown)
TX FIFO_0 TX FIFO_0

TX FIFO_15 TX FIFO_15
Transmitter-data Transmitter-data
buffer register buffer register
8 8

Transmitter SCITXD SCITXD Transmitter

shift register shift register

Receiver SCIRXD SCIRXD Receiver

shift register shift register
8 8
Receiver-data Receiver-data
buffer register buffer register
RX FIFO_0 RX FIFO_0

RX FIFO_15 RX FIFO_15

SCI Device #1 SCI Device #2

TMS320C28x DSP Workshop - Communications 11 - 9

Serial Communications Interface (SCI)

SCI Data Format

NRZ (non-return to zero) format

Addr/
Start LSB 2 3 4 5 6 7 MSB Parity Stop 1 Stop 2
Data

This bit present only in Address-bit mode

Communications Control Register (ScixRegs.SCICCR)

7 6 5 4 3 2 1 0
Stop Even/Odd Parity Loopback Addr/Idle SCI SCI SCI
Bits Parity Enable Enable Mode Char2 Char1 Char0

0 = 1 Stop bit 0 = Disabled 0 = Idle-line mode # of data bits = (binary + 1)

1 = 2 Stop bits 1 = Enabled 1 = Addr-bit mode e.g. 110b gives 7 data bits

0 = Odd 0 = Disabled
1 = Even 1 = Enabled

The basic unit of data is called a character and is 1 to 8 bits in length. Each character of data is
formatted with a start bit, 1 or 2 stop bits, an optional parity bit, and an optional address/data bit.
A character of data along with its formatting bits is called a frame. Frames are organized into
groups called blocks. If more than two serial ports exist on the SCI bus, a block of data will
usually begin with an address frame which specifies the destination port of the data as determined
by the user’s protocol.

The start bit is a low bit at the beginning of each frame which marks the beginning of a frame.
The SCI uses a NRZ (Non-Return-to-Zero) format which means that in an inactive state the
SCIRX and SCITX lines will be held high. Peripherals are expected to pull the SCIRX and
SCITX lines to a high level when they are not receiving or transmitting on their respective lines.

When configuring the SCICCR, the SCI port should first be held in an inactive state. This
is done using the SW RESET bit of the SCI Control Register 1 (SCICTL1.5). Writing a 0 to this
bit initializes and holds the SCI state machines and operating flags at their reset condition. The
SCICCR can then be configured. Afterwards, re-enable the SCI port by writing a 1 to the SW
RESET bit. At system reset, the SW RESET bit equals 0.

11 - 10 TMS320C28x DSP Workshop - Communications

 Serial Communications Interface (SCI)

SCI Data Timing

• Start bit valid if 4 consecutive SCICLK periods of zero bits after falling edge
• Majority vote taken on 4th, 5th, and 6th SCICLK cycles

Majority
Vote

SCICLK
(Internal)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2

SCIRXD

Start Bit LSB of Data

Falling Edge Detected

Note: 8 SCICLK periods per data bit

Multiprocessor Wake-Up Modes

Multiprocessor Wake-Up Modes

‹ Allows numerous processors to be hooked

up to the bus, but transmission occurs
between only two of them
‹ Idle-line or Address-bit modes
‹ Sequence of Operation
1. Potential receivers set SLEEP = 1, which disables RXINT
except when an address frame is received
2. All transmissions begin with an address frame
3. Incoming address frame temporarily wakes up all SCIs on bus
4. CPUs compare incoming SCI address to their SCI address
5. Process following data frames only if address matches

TMS320C28x DSP Workshop - Communications 11 - 11

Serial Communications Interface (SCI)

Idle-Line Wake-Up Mode

‹ Idle time separates blocks of frames
‹ Receiver wakes up when SCIRXD high for 10 or
more bit periods
‹ Two transmit address methods
Š deliberate software delay of 10 or more bits
Š set TXWAKE bit to automatically leave exactly
11 idle bits
Idle periods
of less than Block of Frames
10 bits

SCIRXD/ Last Data SP ST Addr SP ST Data SP ST Last Data SP ST Addr SP

SCITXD

Idle Address frame 1st data frame Idle

Period follows 10 bit Period
10 bits 10 bits
or greater or greater idle or greater

Address-Bit Wake-Up Mode

‹ All frames contain an extra address bit

‹ Receiver wakes up when address bit detected
‹ Automatic setting of Addr/Data bit in frame by
setting TXWAKE = 1 prior to writing address to
SCITXBUF
Block of Frames

SCIRXD/ Last Data 0 SP ST Addr 1 SP ST Data 0 SP ST Last Data 0 SP ST Addr 1 SP

SCITXD

First frame within 1st data frame

no additional
Idle Period block is Address. idle bits needed
length of no ADDR/DATA beyond stop bits
significance bit set to 1

11 - 12 TMS320C28x DSP Workshop - Communications

 Serial Communications Interface (SCI)

The SCI interrupt logic generates interrupt flags when it receives or transmits a complete
character as determined by the SCI character length. This provides a convenient and efficient
way of timing and controlling the operation of the SCI transmitter and receiver. The interrupt
flag for the transmitter is TXRDY (SCICTL2.7), and for the receiver RXRDY (SCIRXST.6).
TXRDY is set when a character is transferred to TXSHF and SCITXBUF is ready to receive the
next character. In addition, when both the SCIBUF and TXSHF registers are empty, the TX
EMPTY flag (SCICTL2.6) is set. When a new character has been received and shifted into
SCIRXBUF, the RXRDY flag is set. In addition, the BRKDT flag is set if a break condition
occurs. A break condition is where the SCIRXD line remains continuously low for at least ten
bits, beginning after a missing stop bit. Each of the above flags can be polled by the CPU to
control SCI operations, or interrupts associated with the flags can be enabled by setting the
RX/BK INT ENA (SCICTL2.1) and/or the TX INT ENA (SCICTL2.0) bits active high.

Additional flag and interrupt capability exists for other receiver errors. The RX ERROR flag is
the logical OR of the break detect (BRKDT), framing error (FE), receiver overrun (OE), and
parity error (PE) bits. RX ERROR high indicates that at least one of these four errors has
occurred during transmission. This will also send an interrupt request to the CPU if the RX ERR
INT ENA (SCICTL1.6) bit is set.

TMS320C28x DSP Workshop - Communications 11 - 13

Serial Communications Interface (SCI)

SCI Registers
SCI Baud Rate Registers
LSPCLK
, BRR = 1 to 65535
(BRR + 1) x 8
SCI baud rate =
LSPCLK
, BRR = 0
16

Baud-Select MSbyte Register (ScixRegs.SCIHBAUD)

7 6 5 4 3 2 1 0
BAUD15
BAUD14 BAUD13 BAUD12 BAUD11 BAUD10 BAUD9 BAUD8
(MSB)

Baud-Select LSbyte Register (ScixRegs.SCILBAUD)

7 6 5 4 3 2 1 0
BAUD0
BAUD7 BAUD6 BAUD5 BAUD4 BAUD3 BAUD2 BAUD1
(LSB)

Baud Rate Determination: The values in the baud-select registers (SCIHBAUD and SCILBAUD)
concatenate to form a 16 bit number that specifies the baud rate for the SCI.

LSPCLK
• For BRR = 1 to 65535: SCI Baud Rate = bits/sec
( BRR + 1) × 8

LSPCLK
• For BRR = 0: SCI Baud Rate = bits/sec
16

Max data rate = 6.25 Mbps @ 100 MHz

Note that the CLKOUT for the SCI module is one-half the CPU clock rate.

11 - 14 TMS320C28x DSP Workshop - Communications

 Serial Communications Interface (SCI)

Select SCI Registers

‹ Control 1 ScixRegs.SCICTL1
Š Reset, Transmitter / Receiver Enable
Š TX Wake-up, Sleep, RX Error Interrupt Enable

‹ Control 2 ScixRegs.SPICTL2
Š TX Buffer Full / Empty Flag, TX Ready Interrupt Enable
Š RX Break Interrupt Enable

‹ Receiver Status ScixRegs.SCIRXST

Š Error Flag, Ready, Flag Break-Detect Flag, Framing Error
Detect Flag, Parity Error Flag, RX Wake-up Detect Flag

‹ FIFO Transmit ScixRegs.SCIFFTX

FIFO Receive ScixRegs.SCIFFRX
Š FIFO Enable, FIFO Reset
Š FIFO Over-flow flag, Over-flow Clear
Š Number of Words in FIFO (FIFO Status)
Š FIFO Interrupt Enable, Interrupt Status, Interrupt Clear
Š FIFO Interrupt Level (Number of Words in FIFO)
Note: refer to the reference guide for a complete listing of registers

SCI Summary
SCI Summary
‹ Asynchronous communications format
‹ 65,000+ different programmable baud rates
‹ Two wake-up multiprocessor modes
Š Idle-line wake-up & Address-bit wake-up
‹ Programmable data word format
Š 1 to 8 bit data word length
Š 1 or 2 stop bits
Š even/odd/no parity
‹ Error Detection Flags
Š Parity error; Framing error; Overrun error; Break detection
‹ Double-buffered transmit and receive
‹ Individual interrupts for transmit and receive

TMS320C28x DSP Workshop - Communications 11 - 15

Inter-Integrated Circuit (I2C)

Inter-Integrated Circuit (I2C)

Inter-Integrated Circuit (I2C)
‹ Philips I2C-bus specification compliant, version 2.1
‹ Data transfer rate from 10 kbps up to 400 kbps
‹ Each device can be considered as a Master or Slave
‹ Master initiates data transfer and generates clock signal
‹ Device addressed by Master is considered a Slave
‹ Multi-Master mode supported
‹ Standard Mode – send exactly n data values (specified in register)
‹ Repeat Mode – keep sending data values (use software to initiate a
stop or new start condition)
VDD ..
Pull-up 28xx I2C
Resisters I2C Controller

Serial Data (SDA)

Serial Clock (SCL)
.. . . . . . . . .
I2C 28xx
EPROM I2C

I2C Block Diagram

I2CXSR I2CDXR

TX FIFO
SDA
RX FIFO

I2CRSR I2CDRR

Clock
SCL
Circuits

11 - 16 TMS320C28x DSP Workshop - Communications

 Inter-Integrated Circuit (I2C)

I2C Operating Modes and Data Formats

I2C Operating Modes

Operating Mode Description

Slave-receiver mode Module is a slave and receives data from a master

(all slaves begin in this mode)

Slave-transmitter mode Module is a slave and transmits data to a master

(can only be entered from slave-master mode)

Master-receiver mode Module is a master and receives data from a slave

(can only be entered from master-transmit mode)

Master-transmitter mode Module is a master and transmits to a slave

(all masters begin in this mode)

I2C Serial Data Formats

7-Bit Addressing Format

1 7 1 1 n 1 n 1 1
S Slave Address R/W ACK Data ACK Data ACK P

10-Bit Addressing Format

1 7 1 1 8 1 n 1 1
S 11110AA R/W ACK AAAAAAAA ACK Data ACK P

Free Data Format

1 n 1 n 1 n 1 1
S Data ACK Data ACK Data ACK P

R/W = 0 – master writes data to addressed slave

R/W = 1 – master reads data from the slave
n = 1 to 8 bits
S = Start (high-to-low transition on SDA while SCL is high)
P = Stop (low-to-high transition on SDA while SCL is high)

TMS320C28x DSP Workshop - Communications 11 - 17

Inter-Integrated Circuit (I2C)

I2C Arbitration
‹ If two or more master-transmitters simultaneously
start transmission, an arbitration procedure is
invoked
Š Procedure uses data presented on serial data bus (SDA) by
competing transmitters
Š First master-transmitter which drives SDA high is overruled
by another master-transmitter that drives SDA low
Š Procedure gives priority to the data stream with the lowest
binary value

SCL
Device #1 lost arbitration
and switches to master-
Data from 1 0 receiver mode
device #1
Data from Device #2
1 0 0 1 0 1 drives SDA
device #2

SDA 1 0 0 1 0 1

I2C Summary
I2C Summary
‹ Compliance with Philips I2C-bus
specification (version 2.1)
‹ Support for 1-bit to 8-bit format
transfers
‹ 7-bit and 10-bit addressing modes
‹ Data transfer rate from 10 kbps up to
400 kbps
‹ 16-bit receive FIFO
‹ 16-bit transmit FIFO
‹ Module enable/disable

11 - 18 TMS320C28x DSP Workshop - Communications

 Enhanced Controller Area Network (eCAN)

Enhanced Controller Area Network (eCAN)

Controller Area Network (CAN)
A Multi-Master Serial Bus System

‹ CAN 2.0B Standard

‹ High speed (up to 1 Mbps)
‹ Add a node without disturbing the bus (number of nodes not
limited by protocol)
‹ Less wires (lower cost, less maintenance, and more reliable)
‹ Redundant error checking (high reliability)
‹ No node addressing (message identifiers)
‹ Broadcast based signaling
A
B
C

D E

CAN does not use physical addresses to address stations. Each message is sent with an identifier
that is recognized by the different nodes. The identifier has two functions – it is used for message
filtering and for message priority. The identifier determines if a transmitted message will be
received by CAN modules and determines the priority of the message when two or more nodes
want to transmit at the same time.

TMS320C28x DSP Workshop - Communications 11 - 19

Enhanced Controller Area Network (eCAN)

CAN Bus and Node

CAN Bus
‹ Two wire differential bus (usually twisted pair)
‹ Max. bus length depend on transmission rate
Š 40 meters @ 1 Mbps

CAN CAN CAN

NODE A NODE B NODE C

CAN_H

120Ω 120Ω
CAN_L

The DSP communicates to the CAN Bus using a transceiver. The CAN bus is a twisted pair wire,
and the transmission rate depends on the bus length. If the bus is less than 40 meters the
transmission rate is capable up to 1 Mbit/second.

CAN Node
Wired-AND Bus Connection
CAN_H

120Ω 120Ω
CAN_L

CAN Transceiver
(e.g. TI SN65HVD23x)

TX RX
CAN Controller
(e.g. TMS320F2808)

11 - 20 TMS320C28x DSP Workshop - Communications

 Enhanced Controller Area Network (eCAN)

Principles of Operation
Principles of Operation
‹ Data messages transmitted are identifier based,
not address based
‹ Content of message is labeled by an identifier that
is unique throughout the network
Š (e.g. rpm, temperature, position, pressure, etc.)
‹ All nodes on network receive the message and
each performs an acceptance test on the identifier
‹ If message is relevant, it is processed (received);
otherwise it is ignored
‹ Unique identifier also determines the priority of the
message
Š (lower the numerical value of the identifier, the higher the
priority)
‹ When two or more nodes attempt to transmit at the
same time, a non-destructive arbitration technique
guarantees messages are sent in order of priority
and no messages are lost

Non-Destructive Bitwise Arbitration

‹ Bus arbitration resolved via arbitration with
wired-AND bus connections
Š Dominate state (logic 0, bus is high)
Š Recessive state (logic 1, bus is low)

Start
Bit
Node A Node A wins
arbitration
Node B
Node C

CAN Bus

Node B loses Node C loses

arbitration arbitration

TMS320C28x DSP Workshop - Communications 11 - 21

Enhanced Controller Area Network (eCAN)

Message Format and Block Diagram

CAN Message Format
‹ Data is transmitted and received using Message Frames
‹ 8 byte data payload per message
‹ Standard and Extended identifier formats

‹ Standard Frame: 11-bit Identifier (CAN v2.0A)

Arbitration Control
Field Field Data Field

S 11-bit R I E
O Identifier T D r0 DLC 0…8 Bytes Data CRC ACK O
F R E F

‹ Extended Frame: 29-bit Identifier (CAN v2.0B)

Control
Arbitration Field Field Data Field

S I R
11-bit S 18-bit E
O R D T r1 r0 DLC 0…8 Bytes Data CRC ACK O
Identifier Identifier
F R E R F

The DSP CAN module is a full CAN Controller. It contains a message handler for transmission
and reception management, and frame storage. The specification is CAN 2.0B Active – that is,
the module can send and accept standard (11-bit identifier) and extended frames (29-bit
identifier).

eCAN Block Diagram

Address Data
eCAN0INT eCAN1INT
32

Memory Management eCAN Memory

Mailbox RAM Unit (512 bytes)
(512 bytes)
CPU Interface, Register and Message
32 Mailboxes 32 Receive Control Unit 32 Object Control
(4 x 32-bit words) Timer Management Unit

A message mailbox
32
Identifier – MID
Control – MCF
Data low – MDL Receive Buffer
Data high - MDH Transmit Buffer
Control Buffer
Status Buffer

SN65HVD23x
3.3-V CAN Transceiver

.
. CAN Bus

11 - 22 TMS320C28x DSP Workshop - Communications

 Enhanced Controller Area Network (eCAN)

The CAN controller module contains 32 mailboxes for objects of 0 to 8-byte data lengths:
• configurable transmit/receive mailboxes
• configurable with standard or extended indentifier

The CAN module mailboxes are divided into several parts:

• MID – contains the identifier of the mailbox
• MCF (Message Control Field) – contains the length of the message (to transmit or
receive) and the RTR bit (Remote Transmission Request – used to send remote
frames)
• MDL and MDH – contains the data

The CAN module contains registers which are divided into five groups. These registers are
located in data memory from 0x006000 to 0x0061FF. The five register groups are:

• Control & Status Registers

• Local Acceptance Masks

• Message Object Time Stamps

• Message Object Timeout

• Mailboxes

eCAN Summary
eCAN Summary
‹ Fully CAN protocol compliant, version 2.0B
‹ Supports data rates up to 1 Mbps
‹ Thirty-two mailboxes
Š Configurable as receive or transmit
Š Configurable with standard or extended identifier
Š Programmable receive mask
Š Uses 32-bit time stamp on messages
Š Programmable interrupt scheme (two levels)
Š Programmable alarm time-out
‹ Programmable wake-up on bus activity
‹ Self-test mode

TMS320C28x DSP Workshop - Communications 11 - 23

Enhanced Controller Area Network (eCAN)

11 - 24 TMS320C28x DSP Workshop - Communications

 Development Support

Introduction
This module contains various references to support the development process.

Learning Objectives
Learning Objectives

‹ Signal Processing Libraries

‹ Additional Resources
Š Internet
Š Product Information Center

TMS320C28x DSP Workshop - Development Support 12 - 1

Module Topics

Module Topics
Development Support ..............................................................................................................................12-1

Module Topics........................................................................................................................................12-2
TI Support Resources.............................................................................................................................12-3

12 - 2 TMS320C28x DSP Workshop - Development Support

 TI Support Resources

TI Support Resources
C28x Signal Processing Libraries
Signal Processing Libraries & Applications Software Literature #
ACI3-1: Control with Constant V/Hz SPRC194
ACI3-3: Sensored Indirect Flux Vector Control SPRC207
ACI3-3: Sensored Indirect Flux Vector Control (simulation) SPRC208
ACI3-4: Sensorless Direct Flux Vector Control SPRC195
ACI3-4: Sensorless Direct Flux Vector Control (simulation) SPRC209
PMSM3-1: Sensored Field Oriented Control using QEP SPRC210
PMSM3-2: Sensorless Field Oriented Control SPRC197
PMSM3-3: Sensored Field Oriented Control using Resolver SPRC211
PMSM3-4: Sensored Position Control using QEP SPRC212
BLDC3-1: Sensored Trapezoidal Control using Hall Sensors SPRC213
BLDC3-2: Sensorless Trapezoidal Drive SPRC196
DCMOTOR: Speed & Position Control using QEP without Index SPRC214
Digital Motor Control Library (F/C280x) SPRC215
Communications Driver Library SPRC183
DSP Fast Fourier Transform (FFT) Library SPRC081
DSP Filter Library SPRC082
DSP Fixed-Point Math Library SPRC085
DSP IQ Math Library SPRC087
DSP Signal Generator Library SPRC083
DSP Software Test Bench (STB) Library SPRC084
C280x C/C++ Header Files and Peripheral Examples SPRC191

Available from TI DSP Website ⇒ http://www.ti.com/c2000

For More Information . . .

Internet
Website: http://www.ti.com

FAQ: http://www-k.ext.ti.com/sc/technical_support/knowledgebase.htm
Š Device information Š my.ti.com
Š Application notes Š News and events
Š Technical documentation Š Training
Enroll in Technical Training: http://www.ti.com/sc/training

USA - Product Information Center ( PIC )

Phone: 800-477-8924 or 972-644-5580
Email: [email protected]
Š Information and support for all TI Semiconductor products/tools
Š Submit suggestions and errata for tools, silicon and documents

TMS320C28x DSP Workshop - Development Support 12 - 3

TI Support Resources

European Product Information Center (EPIC)

Web: http://www-k.ext.ti.com/sc/technical_support/pic/euro.htm

Phone: Language Number

Belgium (English) +32 (0) 27 45 55 32
France +33 (0) 1 30 70 11 64
Germany +49 (0) 8161 80 33 11
Israel (English) 1800 949 0107 (free phone)
Italy 800 79 11 37 (free phone)
Netherlands (English) +31 (0) 546 87 95 45
Spain +34 902 35 40 28
Sweden (English) +46 (0) 8587 555 22
United Kingdom +44 (0) 1604 66 33 99
Finland (English) +358(0) 9 25 17 39 48

Fax: All Languages +49 (0) 8161 80 2045

Email: [email protected]

Š Literature, Sample Requests and Analog EVM Ordering

Š Information, Technical and Design support for all Catalog TI
Semiconductor products/tools
Š Submit suggestions and errata for tools, silicon and documents

12 - 4 TMS320C28x DSP Workshop - Development Support

 Appendix A – eZdsp™ F2808

Note: This appendix only provides a description of the eZdsp™ F2808 interfaces used in this
workshop. For a complete description of all features and details, please see the eZdsp™
F2808 USB Technical Reference manual.

TMS320C28x DSP Workshop - Appendix A - eZdsp F2812 A-1

Appendix

Module Topics
Appendix ....................................................................................................................................................A-1

Module Topics......................................................................................................................................... A-2

eZdsp™ F2808 ........................................................................................................................................ A-3
eZdsp™ F2808 Connector / Header and Pin Diagram ........................................................................A-3
P8 – I/O Interface ...............................................................................................................................A-4
P5 / P9 – Analog Interface..................................................................................................................A-5
SW1 – Switch .....................................................................................................................................A-6
DS1 / DS2 - LEDs ..............................................................................................................................A-7
TP1 / TP2 – Test Points......................................................................................................................A-7

A-2 TMS320C28x DSP Workshop - Appendix A - eZdsp F281208

 Appendix

eZdsp™ F2808
eZdsp™ F2808 Connector / Header and Pin Diagram

TMS320C28x DSP Workshop - Appendix A - eZdsp F281208 A-3

Appendix

P8 – I/O Interface

A-4 TMS320C28x DSP Workshop - Appendix A - eZdsp F281208

 Appendix

P5 / P9 – Analog Interface

TMS320C28x DSP Workshop - Appendix A - eZdsp F281208 A-5

Appendix

SW1 - Switch

A-6 TMS320C28x DSP Workshop - Appendix A - eZdsp F281208

 Appendix

DS1 / DS2 – LEDs

J1 / J2 – Test Points

TMS320C28x DSP Workshop - Appendix A - eZdsp F281208 A-7

Appendix

A-8 TMS320C28x DSP Workshop - Appendix A - eZdsp F281208

 Appendix B – Addressing Modes

Introduction
Appendix B will describe the data addressing modes on the C28x. Immediate addressing allows
for constant expressions which are especially useful in the initialization process. Indirect
addressing uses auxiliary registers as pointers for accessing organized data in arrays. Direct
addressing is used to access general purpose memory. Techniques for managing data pages,
relevant to direct addressing will be covered as well. Finally, register addressing allows for
interchange between CPU registers.

Learning Objectives
Learning Objectives

‹ Explain .sect and .usect assembly directives

‹ Explain assembly addressing modes

‹ Understand instruction formats

‹ Describe options for each addressing mode

TMS320C28x DSP Workshop - Appendix B - Addressing Modes B-1

Module Topics

Module Topics
Appendix B – Addressing Modes .............................................................................................................B-1

Module Topics......................................................................................................................................... B-2

Labels, Mnemonics and Assembly Directives ......................................................................................... B-3
Addressing Modes................................................................................................................................... B-4
Instruction Formats ................................................................................................................................ B-5
Register Addressing ................................................................................................................................ B-6
Immediate Addressing............................................................................................................................. B-7
Direct Addressing ................................................................................................................................... B-8
Indirect Addressing............................................................................................................................... B-10
Review................................................................................................................................................... B-13
Exercise B.........................................................................................................................................B-14
Lab B: Addressing................................................................................................................................. B-15
OPTIONAL Lab B-C: Array Initialization in C .................................................................................... B-17
Solutions................................................................................................................................................ B-18

B-2 TMS320C28x DSP Workshop - Appendix B - Addressing Modes

 Labels, Mnemonics and Assembly Directives

Labels, Mnemonics and Assembly Directives

Labels and Mnemonics
‹ Labels
.ref start
.sect “vectors”
¾ Optional for all assembly ;make reset vector address 'start'
instructions and most reset: .long start
assembler directives
¾ Must begin in column 1 .def start
count .set 9
¾ The “ : ” is not treated as ;create an array x of 10 words
part of the label name x .usect “mydata”, 10
¾ Used as pointers to .sect “code”
memory or instructions start:C28OBJ ;operate in C28x mode
MOV ACC,#1
‹ Mnemonics next: MOVL XAR1,#x
¾ Lines of instructions MOV AR2,#count
loop: MOV *XAR1++,AL
¾ Use upper or lower case
BANZ loop,AR2--
¾ Become components of bump: ADD ACC,#1
program memory SB next,UNC

Assembly Directives
‹ Begin with a period (.) and are
lower case .ref start
.sect “vectors”
¾Used by the linker to locate ;make reset vector address 'start'
code and data into specified reset: .long start
sections
‹ Directives allow you to: .def start
¾ Define a label as global count .set 9
; create an array x of 10 words
¾ Reserve space in memory x .usect “mydata”, 10
for un-initialized variables
.sect “code”
¾ Initialized memory start:C28OBJ ;operate in C28x mode
Directives MOV ACC,#1
initialized section next: MOVL XAR1,#x
.sect “name” MOV AR2,#count
loop: MOV *XAR1++,AL
used for code or constants
BANZ loop,AR2--
uninitialized section bump: ADD ACC,#1
label .usect “name”,5 SB next,UNC
used for variables

TMS320C28x DSP Workshop - Appendix B - Addressing Modes B-3

Addressing Modes

Addressing Modes
Addressing Modes

Mode Symbol Purpose

(register) Register Operate between Registers

(constant) Immediate # Constants and Initialization

(paged) Direct @ General-purpose access to data

(pointer) Indirect * Support for pointers – access arrays,
lists, tables

Four main categories of addressing modes are available on the C28x. Register addressing mode
allows interchange between all CPU registers, convenient for solving intricate equations.
Immediate addressing is helpful for expressing constants easily. Direct addressing mode allows
information in memory to be accessed. Indirect addressing allows pointer support via dedicated
‘auxiliary registers’, and includes the ability to index, or increment through a structure. The C28x
supports a true software stack, desirable for supporting the needs of the C language and other
structured programming environments, and presents a stack-relative addressing mode for
efficiently accessing elements from the stack. Paged direct addressing offers general-purpose
single cycle memory access, but restricts the user to working in any single desired block of
memory at one time.

B-4 TMS320C28x DSP Workshop - Appendix B - Addressing Modes

 Instruction Formats

Instruction Formats
Instruction Formats
INSTR dst ,src Example
INSTR REG NEG AL
INSTR REG,#imm MOV ACC,#1
INSTR REG,mem ADD AL,@x
INSTR mem,REG SUB AL,@AR0
INSTR mem,#imm MOV *XAR0++,#25

‹ What is a “REG”?
‹ 16-bit Access = AR0 through AR7, AH, AL, PH, PL, T and SP
‹ 32-bit Access = XAR0 through XAR7, ACC, P, XT
‹ What is an “#imm”?
‹ an immediate constant stored in the instruction
‹ What is a “mem”?
‹ A directly or indirectly addressed operand from data memory
‹ Or, one of the registers from “REG”!
‹ loc16 or loc32 (for 16-bit or 32-bit data access)

The C28x follows a convention that uses instruction, destination, then source operand order
(INSTR dst, src). Several general formats exist to allow modification of memory or registers
based on constants, memory, or register inputs. Different modes are identifiable by their leading
characters (# for immediate, * for indirect, and @ for direct). Note that registers or data memory
can be selected as a ‘mem’ value.

TMS320C28x DSP Workshop - Appendix B - Addressing Modes B-5

Register Addressing

Register Addressing
Register Addressing
32-bit Registers
XAR0 – XAR7 ACC P XT
16-bit Registers
AR0 – AR7 AH AL PH PL T TL DP SP

‹ Allows for efficient register to register

operation
‹ 16-bit and 32-bit Register Address modes
‹ Reduces code overhead, memory
accesses, and memory overhead

Register addressing allows the exchange of values between registers, and with certain instructions
can be used in conjunction with other addressing modes, yielding a more efficient instruction set.
Remember that any ‘mem’ field allows the use of a register as the operand, and that no special
character (such as @, *, or #) need be used to specify the register mode.

Register Addressing – Example

Format MOV Ax,loc16 MOVL loc32,ACC

Instruction MOV AH,@AL MOVL @XT,ACC

Format MOV loc16,Ax,COND

Instruction MOV @AR1,AL,GT

User Guide & Dis-assembler

use @ for second register

B-6 TMS320C28x DSP Workshop - Appendix B - Addressing Modes

 Immediate Addressing

Immediate Addressing
Immediate Addressing – “#”

one word instruction

OPCODE 8-bit OPERAND

two word instruction

OPCODE
16-bit OPERAND

‹ Fixed value part of program memory

instruction
‹ Supports short (8-bit) and long (16-bit)
immediate constants
‹ Long immediate can include a shift
‹ Used to initialize registers, and operate
with constants

Immediate addressing allows the user to specify a constant within an instruction mnemonic. Short
immediate are single word, and execute in a single cycle. Long (16-bit) immediate allow full
sized values, which become two-word instructions - yet execute in a single instruction cycle.

Immediate Addressing – Example

‹ Short Immediate, 1 Word (ANDB) ‹ Long Immediate, 2 Words (AND)

ANDB Ax,#8Bit AND loc16,#16Bit

ANDB Ax #8Bit AND loc16

#16Bit

AND automatically replaced by

ANDB if IMM value is 8 bits or less AND Ax,loc16,#16Bit
AND Ax loc16
#16Bit

AND ACC,#16Bit,<<0-16
AND ACC shift
#16Bit

TMS320C28x DSP Workshop - Appendix B - Addressing Modes B-7

Direct Addressing

Direct Addressing
Direct addressing allows for access to the full 4-Meg words space in 64 word “page” groups. As
such, a 16-bit Data Page register is used to extend the 6-bit local address in the instruction word.
Programmers should note that poor DP management is a key source of programming errors.
Paged direct addressing is fast and reliable if the above considerations are followed. The watch
operation, recommended for use whenever debugging, extracts the data page and displays it as the
base address currently in use for direct addressing.

Direct Addressing – “@”

Data Page Offset Data Memory
00 0000 0000 0000 00 00 0000
• • • Page 0: 00 0000 – 00 003F
00 0000 0000 0000 00 11 1111
00 0000 0000 0000 01 00 0000
• • • Page 1: 00 0040 – 00 007F
00 0000 0000 0000 01 11 1111
00 0000 0000 0000 10 00 0000
• • • Page 2: 00 0080 – 00 00BF
00 0000 0000 0000 10 11 1111
• • • • •
• • • • •
11 1111 1111 1111 11 00 0000
• • • Page 65,535: 3F FFC0 – 3F FFFF
11 1111 1111 1111 11 11 1111

‹ Data memory space divided into 65,536 pages with

64 words on each page
‹ Data page pointer (DP) used to select active page
‹ 16-bit DP is concatenated with a 6-bit offset from the
instruction to generate an absolute 22-bit address
‹ Access data on a given page in any order

B-8 TMS320C28x DSP Workshop - Appendix B - Addressing Modes

 Direct Addressing

Direct Addressing – Example

0 0 0 1 F F
Z=X+Y 0000 0000 0000 0001 1111 1111
DP offset

Data Memory
x .usect “samp”,3
address data
.sect “code”
Page7[00] 0001C0 0001
MOVW DP,#x … …
64 ...
MOV AL,@x Page7[3D] x: 0001FD 1000
ADD AL,@y Page7[3E] y: 0001FE 0500
MOV @z, AL Page7[3F] z: 0001FF 1500

DP=0007 Accumulator
- - - - - - - -
variations: MOV AL,@x 0 0 0 0 1 0 0 0
¾ MOVW DP,#imm ;2W, 16-bit (4 Meg) ADD AL,@y 0 0 0 0 1 5 0 0
¾ MOVZ DP,#imm ;1W, 10-bit (64K)
¾ MOV DP,#imm ;DP(15:10) unchanged MOV @z,AL

Direct Addressing – Caveats

(X and Y not on the same page)
Z=X+Y Data Memory
address data
DP offset Page7[00] 0001C0 0001
0000 0000 0000 0001 1111 1111 ... … …
Page7[3F] x: 0001FF 1000
0000 0000 0000 0010 0000 0000
Page8[00] y: 000200 0500
… …
DP=0007 Accumulator
0 0 0 7 - - - - - - - - x .usect “samp”,3
0 0 0 7 0 0 0 0 1 0 0 0 .sect “code”
0 0 0 7 0 0 0 0 1 0 0 1 MOVW DP,#x
MOV AL,@x
expecting 1500 ADD AL,@y
MOV @z, AL

Solution: Group and block variables in ASM file:

x .usect “samp”,3,1 ;Force all locations to same data
y .set x+1 ;page (1st hole, else linker error)
z .set x+2 ;Assign vars within block

TMS320C28x DSP Workshop - Appendix B - Addressing Modes B-9

Indirect Addressing

Indirect Addressing
Indirect Addressing – “*”
Data Memory
XAR0
XAR1
XAR2
XAR3
XAR4
XAR5
XAR6
XAR7

ARAU

‹ Auxiliary Registers (XARn) used to access full

data memory space
‹ Address Register Arithmetic Unit (ARAU) used
to modify the XARn
‹ Access data from arrays anywhere in data
memory in an orderly fashion

Any of eight hardware pointers (ARs) may be employed to access values from the first 64K of
data memory. Auto-increment or decrement is supported at no additional cycle cost. XAR register
formats offer larger 32-bit widths, allowing them to access across the full 4-Giga words data
space.

Indirect Addressing Modes

‹ Auto-increment / decrement: *XARn++, *--XARn
Š Post-increment or Pre-decrement
‹ Offset: *+XARn[AR0 or AR1], *+XARn[3bit]
Š Offset by 16-bit AR0 or AR1, or 3-bit constant
‹ Stack Relative: *-SP[6bit]
Š Index by 6-bit offset (optimal for C)
‹ Immediate Direct: *(0:16bit)
Š Access low 64K
‹ Circular: *AR6%++
Š AR1(7:0) is buffer size
Š XAR6 is current address

B - 10 TMS320C28x DSP Workshop - Appendix B - Addressing Modes

 Indirect Addressing

Indirect Addressing – Example

Autoincrement

x .usect “samp”,6 Data

4
y = ∑ xn
y .set (x + 5)
x x0 XAR2
.sect “code” x1
n =0 MOVL XAR2,#x x2
MOV ACC,*XAR2++ x3
ADD ACC,*XAR2++ x4
ADD ACC,*XAR2++ y
ADD ACC,*XAR2++
ADD ACC,*XAR2++ *(0:16bit) - 16 bit label
MOV *(0:y),AL - must be in lower 64K
- 2 word instruction

Fast, efficient access to arrays, lists, tables, etc.

Indexed addressing offers the ability to select operands from within an array without modification
to the base pointer. Stack-based operations are handled with a 16-bit Stack Pointer register, which
operates over the base 64K of data memory. It offers 6-bit non-destructive indexing to access
larger stack-based arrays efficiently.

Indirect Addressing – Example

Offset
Data

XAR2 x x0
x[2] = x[1] + x[3] x1
[3]
x2
x3
x4
x .usect “.samp”,5
.sect “.code”
x .usect “.samp”,5
MOVL XAR2,#x
.sect “.code”
MOV AR0,#1
MOV AR1,#3 MOVL XAR2,#x
MOV ACC,*+XAR2[AR0] MOV ACC,*+XAR2[1]
ADD ACC,*+XAR2[AR1] ADD ACC,*+XAR2[3]
MOV *+XAR2[2],AL
MOV *+XAR2[2],AL
16 bit offset 3 bit offset
Allows offset into arrays with fixed base pointer

TMS320C28x DSP Workshop - Appendix B - Addressing Modes B - 11

Indirect Addressing

Indirect Addressing – Example

Stack Relative

Data Memory
x2 = x1 + x3 0 1 2 0 x3
0
? 3
0 2
? ? x2
5 0
?
0 2 0 0 x1
- SP - empty
empty
Instr. 3
.sect “.code”
Accumulator
MOV AL,*-SP[1]
Instr. 1 0 0 0 0 0 2 0 0
ADD AL,*-SP[3]
MOV *-SP[2],AL Instr. 2 0 0 0 0 0 3 2 0

Useful for stack based operations

Indirect Addressing – Example

Circular
start of buffer Buffer Size N
AAAA … AAAA AAAA AAAA 0000 0000 Element 0
(align on 256 word boundary)

access pointer XAR6 (32) circular

AAAA … AAAA AAAA AAAA xxxx xxxx buffer
range
AR1 Low (16)
end of buffer ---- ---- N-1 Element N-1
(AR1 Low is set to buffer size – 1)

MAC P,*AR6%++,*XAR7++
LINKER.CMD
SECTIONS
{ Buf_Mem: align(256) { } > RAM PAGE 1
. . .
}

B - 12 TMS320C28x DSP Workshop - Appendix B - Addressing Modes

 Review

Review
Addressing Range Review
0x000000

0x00003F
Stack
Addressing
Direct
SP Addressing
64K DP(16+6) Indirect
Addressing
4M
XARn
0x00FFFF
4G

0x3FFFFF

0xFFFFFFFF

Data memory can be accessed in numerous ways:

• Stack Addressing: allows a range to 64K
• Direct Addressing: Offers a 16-bit DP plus a 6-bit offset, allowing a 4M range
• Indirect Addressing: Offers the full 4G range

TMS320C28x DSP Workshop - Appendix B - Addressing Modes B - 13

Review

Exercise B
Exercise B: Addressing
Given: DP = 4000 DP = 4004 DP = 4006
Address/Data (hex) 100030 0025 100100 0105 100180 0100
Fill in the 100031 0120 100101 0060 100181 0030
table below 100032 100102 0020 100182 0040

Src Mode Program ACC DP AR1

XAR1 XAR2
AR2
MOVW DP,#4000h
MOVL XAR1,#100100h
MOVL XAR2,#100180h
MOV AL,@31h
ADD AL,*XAR1++
SUB AL,@30h
ADD AL,*XAR1++
MOVW DP,#4006h
ADD AL,@1
SUB AL,*XAR1
ADD AL,*XAR2
SUB AL,*+XAR2[1]
ADD AL,#32
SUB AL,*+XAR2[2]
MOV @32h,AL
Imm: Immediate; Dir: Direct;
Reg: Register; Idr: Indirect

In the table above, fill in the values for each of the registers for each of the instructions. Three
areas of data memory are displayed at the top of the diagram, showing both their addresses and
contents in hexadecimal. Watch out for surprises along the way. First, you should answer the
addressing mode for the source operand. Then, fill in the change values as the result of the in-
struction operation.

B - 14 TMS320C28x DSP Workshop - Appendix B - Addressing Modes

 Lab B: Addressing

Lab B: Addressing
Note: The lab linker command file is based on the F2812 memory map – modify as needed, if
using a different F28xx device memory map.

¾ Objective

The objective of this lab is to practice and verify the mechanics of addressing. In this process we
will expand upon the ASM file from the previous lab to include new functions. Additionally, we
learn how to run and observe the operation of code using Code Composer Studio.

In this lab, we will initialize the “vars” arrays allocated in the previous lab with the contents of
the “const” table. How is this best accomplished? Consider the process of loading the first
“const” value into the accumulator and then storing this value to the first “vars” location,
and repeating this process for each of the succeeding values.
• What forms of addressing could be used for this purpose?
• Which addressing mode would be best in this case? Why?
• What problems could arise with using another mode?

¾ Procedure

Copy Files, Create Project File

1. Create a new project called LabB.pjt in C:\C28x\Labs\Appendix\LabB and add
LabB.asm, and LabB.cmd to it. Check your file list to make sure all the files are there.
Be sure to setup the Build Options by clicking: Project Æ Build Options on the
menu bar. Select the Linker tab. In the middle of the screen select “No
Autoinitialization” under “Autoinit Model:”. Create a map file by typing
.\Debug\LabB.map in the Map Filename [-m] field. Enter start in the
“Code Entry Point (-e):” field. Next, select the Compiler tab. Note that “Full
Symbolic Debug (-g)” under “Generate Debug Info:” is selected. Then
select OK to save the Build Options.

Initialize Allocated RAM Array from ROM Initialization Table

2. Edit LabB.asm and modify it to copy table[9] to data[9] using indirect addressing. (Note:
data[9] consists of the allocated arrays of data, coeff, and result). Initialize the allocated
RAM array from the ROM initialization table:
• Delete the NOP operations from the “code” section.
• Initialize pointers to the beginning of the “const” and “vars” arrays.
• Transfer the first value from “const” to the “vars” array.
• Repeat the process for all values to be initialized.
To perform the copy, consider using a load/store method via the accumulator. Which part of an
accumulator (low or high) should be used? Use the following when writing your copy routine:
- use AR1 to hold the address of table
- use AR2 to hold the address of data

TMS320C28x DSP Workshop - Appendix B - Addressing Modes B - 15

Lab B: Addressing

3. It is good practice to trap the end of the program (i.e. use either “end: B end,UNC” or
“end: B start,UNC”). Save your work.

Build and Load

4. Click the “Rebuild All” button and watch the tools run in the build window. Debug as
necessary. To open up more space, close any open files or windows that you do not need.
5. Load the output file onto the target. Click:
File Æ Load Program…

If you wish, right click on the LabB.asm source window and select Mixed Mode to
debug using both source and assembly.

Note: Code Composer Studio can automatically load the output file after a successful build. On
the menu bar click: Option Æ Customize… and select the “Program Load
Options” tab, check “Load Program After Build”, then click OK.

6. Single-step your routine. While single-stepping, it is helpful to see the values located in
table[9] and data[9] at the same time. Open two memory windows by using the “View
Memory” button on the vertical toolbar and using the address labels table and data.
Setting the properties filed to “Hex – TI style” will give you more viewable data in the
window. Additionally, it is useful to watch the CPU core (and status) registers. Open the
CPU core (and status) registers by using the “View Æ CPU Registers”. Deselect
“Allow Docking” and move/resize the window as needed. Check to see if the program is
working as expected.
You might want to use your workspace from the previous lab. Look under File Æ Recent
Workspaces on the menu bar to select your saved workspace quickly. If needed, reload your
project.

End of Exercise

B - 16 TMS320C28x DSP Workshop - Appendix B - Addressing Modes

 OPTIONAL Lab B-C: Array Initialization in C

OPTIONAL Lab B-C: Array Initialization in C

Note: The lab linker command file is based on the F2812 memory map – modify as needed, if
using a different F28xx device memory map.

¾ Objective

The objective of this lab is to practice and verify the mechanics of initialization using C.
Additionally, we learn how to run and observe the operation of C code using Code Composer
Studio. In this lab, we will initialize the “vars” arrays with the contents of the “const” table.

¾ Procedure

Create Project File

1. In Code Composer Studio create a new project called LabB-C.pjt in
C:\C28x\Labs\Appendix\LabB\LabB-C and add LabB-C.c, LabB-C.cmd and
C:\ti\c2000\cgtools\lib\rts2800_ml.lib to it. Check your file list to make
sure all the files are there. Do not setup any Build Options. The default values will be used.
In Appendix Lab D exercise, we will experiment and explore the various build options when
working with C.

Initialize Allocated RAM Array from ROM Initialization Table

2. Edit LabB-C.c and modify the “main” routine to copy table[9] to the allocated arrays of
data[4], coeff[4], and result[1]. (Note: data[9] consists of the allocated arrays of data, coeff,
and result).

Build and Load

3. Click the “Rebuild All” button and watch the tools run in the build window. Debug as
necessary.

Note: Have Code Composer Studio automatically load the output file after a successful build. On
the menu bar click: Option Æ Customize… and select the “Program Load Options”
tab, check “Load Program After Build”, then click OK.

4. Under Debug on the menu bar click “Go Main”. Single-step your routine. While single-
stepping, it is helpful to see the values located in table[9] and data[9] at the same time. Open
two memory windows by using the “View Memory” button on the vertical toolbar and
using the address labels table and data. Setting the properties filed to “Hex – TI style”
will give you more viewable data in the window. Additionally, you can watch the CPU (and
Status) registers. Open the CPU core and status registers by using the “View Æ CPU
Registers”. Deselect “Allow Docking” and move/resize the window as needed.
Check to see if the program is working as expected.

End of Exercise

TMS320C28x DSP Workshop - Appendix B - Addressing Modes B - 17

Solutions

Solutions

Exercise B: Addressing - Solution

Given: DP = 4000 DP = 4004 DP = 4006
Address/Data (hex) 100030 0025 100100 0105 100180 0100
Fill in the 100031 0120 100101 0060 100181 0030
table below 100032 100102 0020 100182 0040

Src Mode Program ACC DP XAR1 XAR2

Imm MOVW DP,#4000h 4000
Imm MOVL XAR1,#100100h 100100
Imm MOVL XAR2,#100180h 100180
Dir MOV AL,@31h 120
Idr ADD AL,*XAR1++ 225 100101
Dir SUB AL,@30h 200
Idr ADD AL,*XAR1++ 260 100102
Imm MOVW DP,#4006h 4006
Dir ADD AL,@1 290
Idr SUB AL,*XAR1 270
Idr ADD AL,*XAR2 370
Idr SUB AL,*+XAR2[1] 340 100180
Imm ADD AL,#32 360
Idr SUB AL,*+XAR2[2] 320 100180
Dir MOV @32h,AL 1001B2 0320
Imm: Immediate; Dir: Direct;
Reg: Register; Idr: Indirect

B - 18 TMS320C28x DSP Workshop - Appendix B - Addressing Modes

 Appendix C – Assembly Programming

Introduction
Appendix C discusses the details of programming in assembly. It shows you how to use
different instructions that further utilize the advantage of the architecture data paths. It gives
you the ability to analyze the instruction set and pick the best instruction for the application.

Learning Objectives
Learning Objectives
‹ Perform simple program control using
branch and conditional codes
‹ Write C28x code to perform basic
arithmetic
‹ Use the multiplier to implement
sum-of-products equations
‹ Use the RPT instruction (repeat) to
optimize loops
‹ Use MAC for long sum-of-products
‹ Efficiently transfer the contents of one
area of memory to another
‹ Examine read-modify-write operations

TMS320C28x DSP Workshop - Appendix C - Assembly Programming C-1

Module Topics

Module Topics
Appendix C – Assembly Programming ...................................................................................................C-1

Module Topics.........................................................................................................................................C-2
Program Control.....................................................................................................................................C-3
Branches .............................................................................................................................................C-3
Program Control Instructions .............................................................................................................C-4
ALU and Accumulator Operations..........................................................................................................C-6
Simple Math & Shift...........................................................................................................................C-7
Multiplier ................................................................................................................................................C-9
Basic Multiplier ................................................................................................................................C-10
Repeat Instruction.............................................................................................................................C-11
MAC Instruction...............................................................................................................................C-12
Data Move.............................................................................................................................................C-13
Logical Operations ...............................................................................................................................C-15
Byte Operations and Addressing ......................................................................................................C-15
Test and Change Memory Instructions.............................................................................................C-16
Min/Max Operations.........................................................................................................................C-17
Read Modify Write Operations .............................................................................................................C-18
Lab C: Assembly Programming............................................................................................................C-20
OPTIONAL Lab C-C: Sum-of-Products in C........................................................................................C-22

C-2 TMS320C28x DSP Workshop - Appendix C - Assembly Programming

 Program Control

Program Control
The program control logic and program address generation logic work together to provide proper
program flow. Normally, the flow of a program is sequential: the CPU executes instructions at
consecutive program memory addresses. At times, a discontinuity is required; that is, a program
must branch to a nonsequential address and then execute instructions sequentially at that new
location. For this purpose, the C28x supports interrupts, branches, calls, returns, and repeats.
Proper program flow also requires smooth flow at the instruction level. To meet this need, the
C28x has a protected pipeline and an instruction-fetch mechanism that attempts to keep the
pipeline full.

Branches
Branch Types and Range
¾ 3 Branch Types
0x000000

Long
Short Branch Branch
offset +127/- Branch
Program 128
offset +/-32K
absolute 4M
Memory 1-word 2-word
instruction instruction 2-word
instruction

PC

0x3FFFFF

The PC can access the entire 4M words (8M bytes) range. Some branching operations offer 8-
and 16-bit relative jumps, while long branches, calls, and returns provide a full 22-bit absolute
address. Dynamic branching allows a run-time calculated destination. The C28x provides the fa-
miliar arithmetic results status bits (Zero, oVerflow, Negative, Carry) plus a Test Control bit
which holds the result of a binary test. The states of these bits in various combinations allow a
range of signed, unsigned, and binary branching conditions offered.

TMS320C28x DSP Workshop - Appendix C - Assembly Programming C-3

Program Control

Program Control Instructions

Program Control - Branches
Function Instruction Cycles T/F Size

Short Branch SB 8bit,cond 7/4 1

Fast Short Branch SBF 8bit,EQ|NEQ|TC|NTC 4/4 1
Fast Relative Branch B 16bit,cond 7/4 2
Fast Branch BF 16bit,cond 4/4 2
Absolute Branch LB 22bit 4 2
Dynamic Branch LB *XAR7 4 1
Branch on AR BANZ 16bit,ARn-- 4/2 2
Branch on compare BAR 16bit,ARn,ARn,EQ|NEQ 4/2 2

Condition Code
NEQ LT LO (NC) NTC ‹ Condition flags are set on
EQ LEQ LOS TC the prior use of the ALU
GT HI NOV UNC
GEQ ‹ The assembler will optimize
HIS (C) OV NBIO
B to SB if possible

Program Control - Call/Return

Function Call Code Cycles Return code Cycles

Call LCR 22bit 4 LRETR 4

Dynamic Call LCR *XARn 4 LRETR 4
Interrupt Return IRET 8

‹ More Call variations LCR Func Stack

in the user guide are LRETR Local
for code backward Var
compatibility RPC Old RPC 22-bit old
New RPC Ret Addr RPC

Func
PC
Ret Addr

C-4 TMS320C28x DSP Workshop - Appendix C - Assembly Programming

 Program Control

BANZ Loop Control Example

‹ Auxliary register used as loop counter
‹ Branch if Auxilary Register not zero
‹ Test performed on lower 16-bits of XARx only

4
y = ∑ xn len .set 5
n =0 Data x .usect “samp”,6
y .set (x+len)
x x0 XAR2
x1
.sect “code”
x2
MOVL XAR2,#x
x3
MOV AR3,#len-2
x4
y MOV AL,*XAR2++
sum: ADD AL,*XAR2++
BANZ sum,AR3--
AR3
MOV *(0:y),AL
COUNT

TMS320C28x DSP Workshop - Appendix C - Assembly Programming C-5

ALU and Accumulator Operations

ALU and Accumulator Operations

ALU and Accumulator
16/32 data mem,
Product (32) 16/32 bit registers

MUX 8/16 Imm

ALU and Barrel Shifter ST0, ST1

ACC
AH (31-16) AL (15-0)
AH.MSB AH.LSB AL.MSB AL.LSB

One of the major components in the execution unit is the Arithmetic-Logical-Unit (ALU). To
support the traditional Digital Signal Processing (DSP) operation, the ALU also has the zero
cycle barrel shifter and the Accumulator. The enhancement that the C28x has is the additional
data paths added form the ALU to all internal CPU registers and data memory. The connection to
all internal registers helps the compiler to generate efficient C code. The data path to memory
allows the C28x performs single atomic instructions read-modify-write to the memory.

The following slides introduce you to various instructions that use the ALU hardware. Word,
byte, and long word 32-bit operation are supported.

C-6 TMS320C28x DSP Workshop - Appendix C - Assembly Programming

 ALU and Accumulator Operations

Simple Math & Shift

Accumulator - Basic Math Instructions

Format
xxx Ax, #16b ;word xxx = instruction: MOV, ADD, SUB, ...
xxxB Ax, #8b ;byte Ax = AH, or AL
Assembler will automatically convert to 1
xxxL ACC, #32b ;long word instruction.

ADD ACC, #01234h<<4 Two word instructions with shift option

Ex

ADDB AL, #34h One word instruction, no shift

Ax = AH or AL Operations
ACC Operations MOV Ax, loc16
MOV ACC,loc16<<shift ADD Ax, loc16

}
Variation

ADD SUB Ax, loc16

from memory (left shift
SUB optional) AND Ax, loc16
OR Ax, loc16
MOV ACC,#16b<<shift
ADD
SUB
} 16-bit constant (left shift
optional)
XOR
AND
NOT
Ax, loc16
Ax,loc16,#16b
Ax
MOV loc16,ACC <<shift ;AL NEG Ax
MOVH loc16,ACC <<shift ;AH MOV loc16,Ax

Shift the Accumulator

Shift full ACC 31 ……… 0
LSL
LSL ACC <<shift C ACC 0
(1-16)
SFR ACC >>shift
LSL ACC <<T (0-15) 31 ……… 0
SFR ACC >>T SXM ACC C SFR

15 ……… 0
LSL
Shift AL or AH C Ax 0
LSL AX <<shift
LSR AX <<shift 15 ……… 0
ASR AX >>shift SXM Ax C ASR
LSL AX <<T
LSR AX <<T 15 ……… 0
ASR AX >>T 0 Ax C LSR

TMS320C28x DSP Workshop - Appendix C - Assembly Programming C-7

ALU and Accumulator Operations

32 Bit Shift Operations [ACC]

31 ……… 0
C ACC 0
Examples:
Logical Shift Left – Long: LSLL LSLL ACC, T
LSRL ACC, T
31 ……… 0
0 ACC C
ASRL ACC, T

Note: T(4:0) are used;

Logical Shift Right – Long: LSRL
other bits are ignored
31 ……… 0
0 or 1 ACC C
based on SXM

Arithmetic Shift Right – Long: ASRL

C-8 TMS320C28x DSP Workshop - Appendix C - Assembly Programming

 Multiplier

Multiplier
Multiply Unit
XT Register Data Mem
or Register
T Register

32x32 Multiply Unit

MUX
16x16 Prog Mem (16)
or
Immed (8,16)

P Register (32)

Shift (PM)

ACC (32)

Digital signal processors require many multiply and add math intensive operations. The single
cycle multiplier is the second major component in the execution unit. The C28x has the
traditional 16-bit-by-16-bit multiplier as previous TI DSP families. In-addition, the C28x has a
single cycle 32-bit-by-32-bit multiplier to perform extended precision math operations. The large
multiplier allows the C28x to support higher performance control systems requirement while
maintaining small or reduce code.

The following slides introduce instructions that use the 16-bit-by-16-bit multiplier and multiply
and add (MAC) operations. The 32-bit-by-32-bit multiplication will be covered in the appendix.

TMS320C28x DSP Workshop - Appendix C - Assembly Programming C-9

Multiplier

Basic Multiplier
Multiplier Instructions
Instruction Execution Purpose
MOV T,loc16 T = loc16 Get first operand
MPY ACC,T,loc16 ACC = T*loc16 For single or first product
MPY P,T,loc16 P = T*loc16 For nth product
MPYB ACC,T,#8bu ACC = T*8bu Using 8-bit unsigned const
MPYB P,T,#8bu P = T*8bu Using 8-bit unsigned const
MOV ACC,P ACC = P Move 1st product<<PM to ACC
ADD ACC,P ACC += P Add nth product<<PM to ACC
SUB ACC,P ACC -= P Sub nth product<<PM fr. ACC
Instruction Execution
MOVP T, loc16 ACC = P<<PM T = loc16
MOVA T, loc16 ACC += P<<PM T = loc16
MOVS T, loc16 ACC - = P<<PM T = loc16
MPYA P, T, #16b ACC += P<<PM then P = T*#16b
MPYA P, T, loc16 ACC += P<<PM then P = T*loc16
MPYS P, T, loc16 ACC - = P<<PM then P = T*loc16

Sum-of-Products
Y = A*X1 + B*X2 + C*X3 + D*X4

ZAPA ;ACC = P = OVC = 0

MOV T,@X1 ;T = X1
MPY P,T,@A ;P = A*X1
MOVA T,@X2 ;T = X2 ;ACC = A*X1
MPY P,T,@B ;P = B*X2
MOVA T,@X3 ;T = X3 ;ACC = A*X1 + B*X2
MPY P,T,@C ;P = C*X3
MOVA T,@X4 ;T = X4;ACC = A*X1 + B*X2 + C*X3
MPY P,T,@D ;P = D*X4
ADDL ACC,P<<PM ;ACC = Y
MOVL @y,ACC

C - 10 TMS320C28x DSP Workshop - Appendix C - Assembly Programming

 Multiplier

32x32 Long Multiplication

X
X Y
Integer long multiplication
XO * Y0
u(long) = u(long) * u(long)
Fraction long multiplication:
Y1 * X1 (long) = (long) * (long)
Z3 Z2 Z1 Z0 (long) 64 = (long) 32 * (long) 32
Accumulator P-register

IMPYAL P,XT,loc32 P = u(XT)*u(loc32)

QMPYAL ACC,XT,loc32 ACC = (XT)*(loc32)

IMACL P,loc32,*XAR7 ACC += P; P = u(loc32)*u(loc32)

QMACL P,loc32,*XAR7 ACC += P; P = (loc32)*(loc32)

Repeat Instruction
Repeat Next: RPT
‹ Options:
¾ RPT #8bit up to 256 iterations
¾ RPT loc16 location “loc16” holds count value

‹ Features: Example :
¾ Next instruction iterated N+1 times int x[5]={0,0,0,0,0};
¾ Saves code space - 1 word
¾ Low overhead - 1 cycle
x .usect “samp”,5
MOV AR1,#x
¾ Easy to use
RPT #4
¾ Non-interruptible
|| MOV *XAR1++,#0
¾ Requires use of | | before next line
¾ May be nested within BANZ loops
Instruction Cycles
RPT 1
BANZ 4 .N
Refer to User Guide for more repeatable instructions

TMS320C28x DSP Workshop - Appendix C - Assembly Programming C - 11

Multiplier

Single repeat instruction (RPT) is used to reduce code size and speed up many operations in the
DSP application. Some of the most popular operations that use the RPT instruction to perform
multiple taps digital filters or perform block of data transfer.

MAC Instruction
Sum-of-Products: RPT / MAC
x .usect “sample”,20
19
y = ∑ xn an
y .usect “result”,2
.sect “coefficient”
a0: .word 0x0101
n =0 .word 0x0202
• • •
XAR1++ X0 .word 0x2020
X1 .sect “code”
SOP: SPM 0
... MOVW DP,#y
MOVL XAR1,#x
X19 MOVL XAR7,#a0
ZAPA Zero ACC & P
XAR7++ A0 RPT #19 Repeat single
Second operand || MAC P,*XAR1++,*XAR7++ Dual operand
must use XAR7 A1
ADDL ACC,P<<PM last ADD
... MOVL @y,ACC
A19 B SOP,UNC

MOV
ADD
T,loc16
ACC,P
MOVA T,loc16
MPY P,T,loc16
MAC { ACC+=P
T=*ARn++
P=T*(*ARn++)

C - 12 TMS320C28x DSP Workshop - Appendix C - Assembly Programming

 Data Move

Data Move
Data Move Instructions
DATA ↔ DATA (4G ↔ 64K) DATA ↔ PGM (4G ↔ 4M)
MOV loc16, *(0:16bit) PREAD loc16 ,*XAR7
MOV *(0:16bit), loc16 PWRITE *XAR7, loc16

16-bit address concatenated 32-bit address memory pointer with a 22-bit

with 16 leading zeros location program memory address

.sect “.code”
START: MOVL XAR5,#x
MOVL XAR7,#TBL
RPT #len-1
|| PREAD *XAR5++,*XAR7
...
x .usect “.samp”,4
.sect “.coeff”
TBL: .word 1,2,3,4
len .set $-TBL

‹ Optimal with RPT (speed and code size) ‹ Faster than Load / Store, avoids
‹ In RPT, non-mem address is auto- accumulator
incremented in PC ‹ Allows access to program memory

Conditional Moves
Instruction Execution (if COND is met)
MOV loc16,AX,COND [loc16] = AX
MOVB loc16,#8bit,COND [loc16] = 8bit
Instruction Execution (if COND is met)
MOVL loc32,ACC,COND [loc32] = AX
Example
If A<B, Then B=A
Accumulator
A .usect “var”,2,1 0 0 0 0 0 1 2 0
B .set A+1
.sect “code”
Data Memory Data Memory
MOVW DP, #A
MOV AL, @A 0 1 2 0 A 0 1 2 0 A
CMP AL, @B 0 3 2 0 B 0 1 2 0B
MOV @B, AL, LT Before After

The conditional move instruction is an excellent way to avoid a discontinuity (branch or call)
based upon a condition code set prior to the instruction. In the above example, the 1st step is to

TMS320C28x DSP Workshop - Appendix C - Assembly Programming C - 13

Data Move

place the contents of A into the accumulator. Once the Ax content is tested, by using the CMP
instruction, the conditional move can be executed.

If the specified condition being tested is true, then the location pointed to by the “loc16” address-
ing mode or the 8–bit zero extended constant will be loaded with the contents of the specified AX
register (AH or AL): if (COND == true) [loc16] = AX or 0:8bit;

Note: Addressing modes are not conditionally executed. Hence, if an addressing mode performs a
pre or post modification, it will execute regardless if the condition is true or not. This instruction
is not repeatable. If this instruction follows the RPT instruction, it resets the repeat counter
(RPTC) and executes only once.
Flags and Modes
N - If the condition is true, then after the move, AX is tested for a negative condition. The nega-
tive flag bit is set if bit 15 of AX is 1, otherwise it is cleared.
Z - If the condition then after the move, AX is tested for a zero condition. The zero flag bit is set
if AX = 0, otherwise it is cleared.
V - If the V flag is tested by the condition, then V is cleared.

C-Example
; if ( VarA > 20 )
; VarA = 0;

CMP @VarA,#20 ; Set flags on (VarA – 20)

MOVB @VarA,#0,GT ; Zero VarA if greater then

C - 14 TMS320C28x DSP Workshop - Appendix C - Assembly Programming

 Logical Operations

Logical Operations
Byte Operations and Addressing
Byte Operations

MOVB AX.LSB,loc16 0000 0000 Byte AX

MOVB AX.MSB,loc16 Byte No change AX

MOVB loc16, AX.LSB No change Byte loc16

MOVB loc16, AX.MSB No change Byte loc16

Byte = 1. Low byte for register addressing

2. Low byte for direct addressing
3. Selected byte for offset indirect addressing

For loc16 = *+XARn[Offset] Odd Offset Even Offset loc16

Byte Addressing
AH.MSB AH.LSB AL.MSB AL.LSB
12 34 56 78

16 bit memory
01
78 00 AR2
03 02
56
05
34 04
07 06
12

Example of Byte Un-Packing Example of Byte Packing

MOVL XAR2, #MemA MOVL XAR2, #MemA
MOVB *+XAR2[1], AL.LSB MOVB AL.LSB,*+XAR2[1]
MOVB *+XAR2[2], AL.MSB MOVB AL.MSB,*+XAR2[2]
MOVB *+XAR2[5], AH.LSB MOVB AH.LSB,*+XAR2[4]
MOVB *+XAR2[6], AH.MSB MOVB AH.MSB,*+XAR2[7]

TMS320C28x DSP Workshop - Appendix C - Assembly Programming C - 15

Logical Operations

Test and Change Memory Instructions

The compare (CMPx) and test (Txxx) instructions allow the ability to test values in memory. The
results of these operations can then trigger subsequent conditional branches. The CMPx instruc-
tion allows comparison of memory with respect to a specified constant value, while the Txxx in-
structions allow any single bit to be extracted to the test control (TC) field of status register 0.
The contents of the accumulator can also be non-destructively analyzed to establish branching
conditions, as seen below.

Test and Change Memory

Instruction Execution Affects

TBIT loc16,#(0-15) ST0(TC) = loc16(bit_no) TC
TSET loc16,#(0-15) Test (loc16(bit)) then set bit TC
TCLR loc16,#(0-15) Test (loc16(bit)) then clr bit TC
CMPB AX, #8bit Test (AX - 8bit unsigned) C,N,Z
CMP AX, loc16 Test (AX – loc16) C,N,Z
CMP loc16,#16b Test (loc16 - #16bit signed) C,N,Z
CMPL ACC, @P Test (ACC - P << PM) C,N,Z

C - 16 TMS320C28x DSP Workshop - Appendix C - Assembly Programming

 Logical Operations

Min/Max Operations
MIN/MAX Operations
Instruction Execution
MAX ACC,loc16 if ACC < loc16, ACC = loc16
if ACC >= loc16, do nothing
MIN ACC,loc16 if ACC > loc16, ACC = loc16
if ACC <= loc16, do nothing
MAXL ACC,loc32 if ACC < loc32, ACC = loc32
if ACC >= loc32, do nothing
MINL ACC,loc32 if ACC > loc32, ACC = loc32
if ACC <= loc32, do nothing
MAXCUL P,loc32 if P < loc32, P = loc32
(for 64 bit math) if P >= loc32, do nothing
MINCUL P,loc32 if P > loc32, P = loc32
(for 64 bit math) if P <= loc32, do nothing

Find the maximum 32-bit number in a table:

MOVL ACC,#0
MOVL XAR1,#table
RPT #(table_length – 1)
|| MAXL ACC,*XAR1++

TMS320C28x DSP Workshop - Appendix C - Assembly Programming C - 17

Read Modify Write Operations

Read Modify Write Operations

The accumulator (ACC) is the main working register for the C28x. It is the destination of all
ALU operations except those, which operate directly on memory or registers. The accumulator
supports single-cycle move, add, subtract and compare operations from 32-bit-wide data memory.
It can also accept the 32-bit result of a multiplication operation. These one or two cycle
operations are referred to as read-modify-write operations, or as atomic instructions.

Read-Modify-Write Instructions

‹ Work directly on memory – bypass ACC

‹ Atomic Operations – protected from interrupts

AND loc16,AX AND loc16,#16b

OR loc16,AX OR loc16,#16b
XOR loc16,AX AH, XOR loc16,#16b 16- bit
AL constant
ADD loc16,AX ADD loc16,#16b
SUB loc16,AX SUBR loc16,#16b
SUBR loc16,AX
INC loc16 TSET loc16,#bit
DEC loc16 TCLR loc16,#bit

C - 18 TMS320C28x DSP Workshop - Appendix C - Assembly Programming

 Read Modify Write Operations

Read-Modify-Write Examples
update with a mem update with a constant update by 1

VarA += VarB VarA += 100 VarA += 1

SETC INTM SETC INTM SETC INTM
MOV AL, @VarB MOV AL, @VarA MOV AL, @VarA
ADD AL, @VarA ADD AL, #100 ADD AL, #1
MOV @VarA, AL MOV @VarA, AL MOV @VarA, AL
CLRC INTM CLRC INTM CLRC INTM

MOV AL, @VarB ADD @VarA,#100 INC @VarA

ADD @VarA, AL

Benefits of Read-Modify-Write Instructions

TMS320C28x DSP Workshop - Appendix C - Assembly Programming C - 19

Lab C: Assembly Programming

Lab C: Assembly Programming

Note: The lab linker command file is based on the F2812 memory map – modify as needed, if
using a different F28xx device memory map.

¾ Objective

The objective of this lab is to practice and verify the mechanics of performing assembly language
programming arithmetic on the TMS320C28x. In this process we will expand upon the .asm file
from the previous lab to include new functions. Code will be to added to obtain the sum of the
products of the values from each array.
Perform the sum of products using a MAC-based implementation. In a real system application,
the coeff array may well be constant (values do not change), therefore one can modify the
initialization routine to skip the transfer of this arrays, thus reducing the amount of data RAM and
cycles required for initialization. Also, there is no need to copy the zero to clear the result
location. The initialization routine from the previous lab using the load/store operation will be
replaced with a looped BANZ implementation.

As in previous lab, consider which addressing modes are optimal for the tasks to be performed.
You may perform the lab based on this information alone, or may refer to the following
procedure.

¾ Procedure

Copy Files, Create Project File

1. Create a new project called LabC.pjt in C:\C28x\Labs\Appendix\LabC and
add LabC.asm, and LabC.cmd to it. Check your file list to make sure all the files are
there. Be sure to setup the Build Options by clicking: Project Æ Build
Options on the menu bar. Select the Linker tab. In the middle of the screen select
“No Autoinitialization” under “Autoinit Model:”. Create a map file by
typing .\Debug\LabC.map in the Map Filename [-m] field. Enter start
in the “Code Entry Point (-e):” field. Next, select the Compiler tab. Note that
“Full Symbolic Debug (-g)” under “Generate Debug Info:” is
selected. Then select OK to save the Build Options.

Initialization Routine using BANZ

2. Edit LabC.asm and modify it by replacing the initialization routine using the load/store
operation with a BANZ process. Remember, it is only necessary to copy the first four
values (i.e. initialize the data array). Do you still need the coeff array in the vars section?

3. Save your work. If you would like, you can use Code Composer Studio to verify the
correct operation of the block initialization before moving to the next step.

C - 20 TMS320C28x DSP Workshop - Appendix C - Assembly Programming

 Lab C: Assembly Programming

Sum of Products using a RPT/MAC-based Implementation

4. Edit LabC.asm to add a RPT/MAC-based implementation to multiply the coeff array by
the data array and storing the final sum-of-product value to result.

Build and Load

5. Click the “Rebuild All” button and watch the tools run in the build window. Debug
as necessary. To open up more space, close any open files or windows that you do not
need.

6. If the “Load program after build” option was not selected in Code Composer
Studio, load the output file onto the target. Click: File Æ Load Program…

If you wish, right click on the source window and select Mixed Mode to debug using
both source and assembly.
7. Single-step your routine. While single-stepping, open memory windows to see the values
located in table [9] and data [9] . Open the CPU Registers. Check to see if the program is
working as expected. Debug and modify, if needed.

Optional Exercise
After completing the above, edit LabC.asm and modify it to perform the initialization
process using a RTP/PREAD rather than a load/store/BANZ.

End of Exercise

TMS320C28x DSP Workshop - Appendix C - Assembly Programming C - 21

OPTIONAL Lab C-C: Sum-of-Products in C

OPTIONAL Lab C-C: Sum-of-Products in C

Note: The lab linker command file is based on the F2812 memory map – modify as needed, if
using a different F28xx device memory map.

¾ Objective

The objective of this lab is to practice and verify the mechanics of performing C programming
arithmetic on the TMS320C28x. The objective will be to add the code necessary to obtain the
sum of the products of the n-th values from each array.

¾ Procedure

Create Project File

1. In Code Composer Studio create a new project called LabC-C.pjt in
C:\C28x\Labs\Appendix\LabC\LabC-C and add LabC-C.c, LabC-C.cmd
and C:\ti\c2000\cgtools\lib\rts2800_ml.lib to it. Check your file list to
make sure all the files are there. Do not setup any Build Options. The default values will
be used. In Appendix Lab D exercise, we will experiement and explore the various build
options when working with C.

Sum of Products using a MAC-based Implementation

2. Edit LabC-C.c and modify the “main” routine to perform a MAC-based
implementation in C. Since the MAC operation requires one array to be in program
memory, the initialization routine can skip the transfer of one of the arrays, thus reducing
the amount of data RAM and cycles required for initialization.

Build and Load

3. Click the “Rebuild All” button and watch the tools run in the build window. Debug
as necessary.

Note: Have Code Composer Studio automatically load the output file after a successful build. On
the menu bar click: Option Æ Customize… and select the “Program Load Options”
tab, check “Load Program After Build”, then click OK.

4. Under Debug on the menu bar click “Go Main”. Single-step your routine. While
single-stepping, open memory windows to see the values located in table [9] and data
[9] . (Note: data[9] consists of the allocated arrays of data, coeff, and result). Open the
CPU Registers. Check to see if the program is working as expected. Debug and modify,
if needed.

End of Exercise

C - 22 TMS320C28x DSP Workshop - Appendix C - Assembly Programming

 Appendix D – C Programming

Introduction
The C28x architecture, hardware, and compiler has been designed to efficiently support C code
programming.

Appendix D will focus on how to program in C for an embedded system. Issues related to
programming in C and how C behaves in the C28x environment will be discussed. Also, the C
compiler optimization features will be explained.

Learning Objectives
Learning Objectives

‹ Learn the basic C environment for

the C28x family
‹ How to control the C environment
‹ How to use the C-compiler optimizer
‹ Discuss the importance of volatile
‹ Explain optimization tips

TMS320C28x DSP Workshop – Appendix D – C Programming D- 1

Module Topics

Module Topics
Appendix D – C Programming.................................................................................................................D-1

Module Topics.........................................................................................................................................D-2
Linking Boot code from RTS2800.lib ......................................................................................................D-3
Set up the Stack .......................................................................................................................................D-4
C28x Data Types.....................................................................................................................................D-5
Accessing Interrupts / Status Register.....................................................................................................D-6
Using Embedded Assembly .....................................................................................................................D-7
Using Pragma .........................................................................................................................................D-8
Optimization Levels ................................................................................................................................D-9
Volatile Usage ..................................................................................................................................D-11
Compiler Advanced Options ............................................................................................................D-12
Optimization Tips Summary.............................................................................................................D-13
Lab D: C Optimization..........................................................................................................................D-14
OPTIONAL Lab D2: C Callable Assembly...........................................................................................D-17
Solutions................................................................................................................................................D-20

D- 2 TMS320C28x DSP Workshop – Appendix D – C Programming

 Linking Boot code from RTS2800.lib

Linking Boot code from RTS2800.lib

Boot.ASM - Invoked With “-C”

Reset : PC <- *0x3F FFC0

vectors.asm
.ref _c_int00
Reset:
.long _c_int00
_c_int00
1. Allocate stack
2. Init SP to top of stack
3. Initialize status bits
4. Copy .cinit to .bss (skip if “-cr”)
5. Call “_main”

_main ...

The boot routine is used to establish the environment for C before launching main. The boot
routine begins with the label _c_int00 and the reset vector should contain a ".long" to this address
to make boot.asm the reset routine. The contents of the boot routine have been extracted and
copied on the following page so they may be inspected. Note the various functions performed by
the boot routine, including the allocation and setup of the stack, setting of various C-requisite
statuses, the initialization of global and static variables, and the call to main. Note that if the link
was performed using the "–cr" option instead of the "–c" option that the global/static variable
initialization is not performed. This is useful on RAM-based C28x systems that were initialized
during reset by some external host processor, making transfer of initialization values unnecessary.
Later on in this chapter, there is an example on how to do the vectors in C code rather than
assembly.

TMS320C28x DSP Workshop – Appendix D – C Programming D-3

Set up the Stack

Set up the Stack

Data Memory
The Stack
The C/C++ compiler uses a
stack to:
‹ Allocate local variables
SP 0x400 Caller’s
(reset) local vars ‹ Pass arguments to
Arguments functions
passed on
stack ‹ Save the processor status
Return ‹ Save the function return
address .stack
address
Function
return addr ‹ Save temporary results
Temp results
The compiler uses the hardware
stack pointer (SP) to
64K manage the stack.
SP defaults to 0x400 at reset.
4M The run-time stack grows from
low addresses to higher
addresses.
The C28x has a 16-bit stack pointer (SP) allowing accesses to the base 64K of memory. The stack
grows from low to high memory and always points to the first unused location. The compiler
uses the hardware stack pointer (SP) to manage the stack. The stack size is set by the linker.

Setting Up the Stack

‹ Boot.asm sets up SP to
point at .stack
Linker command file: ‹ The .stack section has to
SECTIONS { be linked into the low 64k
.stack :> RAM align=2 of data memory. The SP is
... } a 16-bit register and cannot
access addresses beyond
64K.
‹ Stack size is set by the
linker. The linker creates a
Note: The compiler provides no global symbol,
means to check for stack --STACK-SIZE, and assigns
overflow during compilation or at it a value equal to the size
runtime. A stack overflow of the stack in bytes.
disrupts the run-time (default 1K words)
environment, causing your
‹ You can change stack size
program to fail. Be sure to allow
at link time by using the
enough space for the stack to
-stack linker command
grow.
option.

In order to allocate the stack the linker command file needs to have “align = 2.”

D- 4 TMS320C28x DSP Workshop – Appendix D – C Programming

 C28x Data Types

C28x Data Types

C28x C-Language Data Types
Type Bit Value Range
char 16 Usually 0 .. 255, but can hold 16 bits
int (natural size CPU word) 16 -32K .. 32K, 16 bits signed
unsigned int 16 0 .. 64K, 16 bits unsigned
short (same as int or smaller) 16 same as int
unsigned short 16 same as unsigned int
long (same as int or larger) 32 -2M .. 2M, 32 bits signed
unsigned long 32 0 .. 4M, 32 bits unsigned
float 32 IEEE single precision
double 64 IEEE double precision
long double 64 IEEE double precision
Suggestion: Group all longs together, group all pointers together
Data which is 32-bits wide, such as longs, must begin on even word-addresses (i.e. 0x0,
0x2, etc). This can result in “holes” in structures allocated on the stack.

TMS320C28x DSP Workshop – Appendix D – C Programming D-5

Accessing Interrupts / Status Register

Accessing Interrupts / Status Register

Accessing Interrupts / Status Register
Initialize via C :
extern cregister volatile unsigned int IFR;
extern cregister volatile unsigned int IER;
. . .
IER &= ~Mask; //clear desired bits
IER |= Mask; //set desired bits
IFR = 0x0000; //clear prior interrupts

‹ Interrupt Enable & Interrupt Flag Registers (IER, IFR) are not
memory mapped
‹ Only limited instructions can access IER & IFR (more in interrupt
chapter)
‹ The compiler provides extern variables for accessing the IER & IFR

D- 6 TMS320C28x DSP Workshop – Appendix D – C Programming

 Using Embedded Assembly

Using Embedded Assembly

Embedding Assembly in C
‹ Allows direct access to assembly language from C
‹ Useful for operating on components not used by C, ex:

asm ( “ CLRC INTM ; enable global interrupt” );

#define EINT asm ( “ CLRC INTM”)

‹ Note: first column after leading quote is label field - if no label,
should be blank space.
‹ Avoid modifying registers used by C
‹ Lengthy code should be written in ASM and called from C
¾ main C file retains portability
¾ yields more easily maintained structures
¾ eliminates risk of interfering with registers in use by C

The assembly function allows for C files to contain 28x assembly code. Care should be taken not
to modify registers in use by C, and to consider the label field with the assembly function. Also,
any significant amounts of assembly code should be written in an assembly file and called from
C.
There are two examples in this slide – the first one shows how to embed a single assembly
language instruction into the C code flow. The second example shows how to define a C term that
will invoke the assembly language instruction.

TMS320C28x DSP Workshop – Appendix D – C Programming D-7

Using Pragma

Using Pragma
Pragma is a preprocessor directive that provides directions to the compiler about how to treat a
particular statement. The following example shows how the DATA_SECTION pragma is used
to put a specific buffer into a different section of RAM than other buffers.

The example shows two buffers, bufferA and bufferB. The first buffer, bufferA is treated
normally by the C compiler by placing the buffer (512 words) into the ".bss" section. The second,
bufferB is specifically directed to go into the “my_sect” portion of data memory. Global
variables, normally ".bss", can be redirected as desired.

When using CODE_SECTION, code that is normally linked as ".text", can be identified
otherwise by using the code section pragma (like .sect in assembly).

Pragma Examples
‹ User defined sections from C :
#pragma CODE_SECTION (func, ”section name”)
#pragma DATA_SECTION (symbol, “section name”)

‹ Example - using the DATA_SECTION Pragma

‹ C source file
char bufferA[512];
#pragma DATA_SECTION(bufferB, ”my_sect”)
char bufferB[512];

‹ Resulting assembly file

.global _bufferA, _bufferB
.bss _bufferA,512
_bufferB: .usect “my_sect”,512

More #pragma are defined in the C compiler UG

D- 8 TMS320C28x DSP Workshop – Appendix D – C Programming

 Optimization Levels

Optimization Levels
Optimization Scope
FILE1.C
-o0, -o1 -o2 -o3 -pm -o3
{
{
SESE
} LOCAL
single block
{ FUNCTION
... across FILE
} SESE: Single Entry, Single Exit blocks across
} functions PROGRAM
across files
{
. . .
}

FILE2.C
{
. . .
}

Optimizations fall into 4 categories. This is also a methodology that should be used to invoke the
optimizations. It is recommended that optimization be invoked in steps, and that code be verified
before advancing to the next step. Intermediate steps offer the gradual transition from fully sym-
bolic to fully optimized compilation. Compiler switched may be invoked in a variety of ways.

Here are 4 steps that could be considered:

1st: use –g
By starting out with –g, you do no optimization at all and keep symbols for debug.

2nd: use –g –o3

The option –o3 might be too big a jump, but it adds the optimizer and keeps symbols.

3rd: use –g –o3 –mn

This is a full optimization, but keeps some symbols

4th: use –o3

Full optimization, symbols are not kept.

TMS320C28x DSP Workshop – Appendix D – C Programming D-9

Optimization Levels

Optimization Performance
–o0 Performs control-flow-graph simplification
Allocates variables to registers
LOCAL Performs loop rotation
Eliminates unused code
Simplifies expressions and statements
Expands calls to functions declared inline
–o1 Performs local copy/constant propagation
Removes unused assignments
Eliminates local common expressions
–o2 Default (-o)
FUNCTION Performs loop optimizations
Eliminates global common sub-expressions
Eliminates global unused assignments
–o3 Removes all functions that are never called
FILE Simplifies functions with return values that are never used
Inlines calls to small functions
Identifies file-level variable characteristics
PROGRAM –o3 –pm

Optimizer levels zero through three, offer an increasing array of actions, as seen above. Higher
levels include all the functions of the lower ones. Increasing optimizer levels also increase the
scope of optimization, from considering the elements of single entry, single-exit functions only,
through all the elements in a file. The “-pm” option directs the optimizer to view numerous input
files as one large single file, so that optimization can be performed across the whole system.

D- 10 TMS320C28x DSP Workshop – Appendix D – C Programming

 Optimization Levels

Volatile Usage
Optimization Issue: “Volatile” Variables
Problem: The compiler does not know that this pointer may refer to a
hardware register that may change outside the scope of the C program.
Hence it may be eliminated (optimized out of existence!)

Wrong: Wait loop for a hardware signal Optimizer removes

unsigned int *CTRL empty loop
while (*CTRL !=1); No
CTRL empty
Solution: = 1? loop
volatile unsigned int *CTRL
while (*CTRL !=1); Yes
‹ When using optimization, it is important to declare variables as
volatile when:
¾ The memory location may be modifed by something other than the
compiler (e.g. it’s a memory-mapped peripheral register).
¾ The order of operations should not be rearranged by the compiler
‹ Define the pointer as “volatile” to prevent the optimizer from optimizing

TMS320C28x DSP Workshop – Appendix D – C Programming D - 11

Optimization Levels

Compiler Advanced Options

To get to these options, go to Project Æ Build Options in Code Composer Studio.

In the category, pick Advanced.

The first thing to notice under advanced options is the Auto Inlining Threshold.

- Used with –o3 option

- Functions > size are not auto inlined

Note: To prevent code size increases when using –o3, disable auto inlining with -oi0

The next point we will cover is the Normal Optimization with Debug (-mn).

- Re-enables optimizations disabled by “–g” option (symbolic debug)

- Used for maximum optimization

Note: Some symbolic debug labels will be lost when –mn option is used.

Optimizer should be invoked incrementally:

-g test Symbols kept for debug

-g -o3 test Add optimizer, keep symbols

-g -o3 -mn test More optimize, some symbols

-o3 test Final rev: Full optimize, no symbols

[-mf] : Optimize for speed instead of the default optimization for code size

[-mi] : Avoid RPT instruction. Prevent compiler from generating RPT instruction. RPT instruc-
tion is not interruptible

[-mt] : Unified memory model. Use this switch with the unified memory map of the 281x &
280x. Allows compiler to generate the following:
-RPT PREAD for memory copy routines or structure assignments
-MAC instructions
-Improves efficiency of switch tables

D- 12 TMS320C28x DSP Workshop – Appendix D – C Programming

 Optimization Levels

Optimization Tips Summary

Summary: Optimization Tips
‹ Within C functions :
¾ Use const with variables for parameter constants
¾ Minimize mixing signed & unsigned ops : SXM changes
¾ Keep frames <= 64 (locals + parameters + PC) : *-SP[6bit]
¾ Use structures <= 8 words : use 3 bit index mode
¾ Declare longs first, then declare ints : minimize stack holes
¾ Avoid: long = (int * int) : yields unpredictable results
‹ Optimizing : Use -o0, -o1, -o2, -o3 when compiling
¾ Inline short/key functions
¾ Pass inlines between files : static inlines in header files
¾ Invoke automatic inlining : -o3 -oi
¾ Give compiler project visibility : use -pm and -o3
‹ Tune memory map via linker command file
‹ Re-write key code segments to use intrinsics or in assembly
App notes 3rd Parties

The list above documents the steps that can be taken to achieve increasingly higher coding effi-
ciency. It is recommended that users first get their code to work with no optimization, and then
add optimizations until the required performance is obtained.

TMS320C28x DSP Workshop – Appendix D – C Programming D - 13

Lab D: C Optimization

Lab D: C Optimization
Note: The lab linker command file is based on the F2812 memory map – modify as needed, if
using a different F28xx device memory map.

¾ Objective

The objective of this lab is to practice and verify the mechanics of optimizing C programs. Using
Code Composer Studio profile capabilities, different routines in a project will be benchmarked.
This will allow you to analyze the performance of different functions. This lab will highlight the
profiler and the clock tools in CCS.

¾ Procedure

Create Project File

1. Create a new project in C:\C28x\Labs\Appendix\LabD called LabD.pjt and
add LabD.c, LabD.cmd, and sop-c.c to it. (Note that sop-asm.asm will be used
in the next part of the lab, and should not be added now). Also, add the compiler run-
time support library to the project
(C:\ti\c2000\cgtools\lib\rts2800_ml.lib).

2. Setup the Build Options. Select the Linker tab and in the middle of the screen select
“Run-time Autoinitialization” under “Autoinit Model:”. Create a
map file by typing .\Debug\LabD.map in the Map Filename [-m] field. Do
not enter anything in the “Code Entry Point (-e):” field (leave it blank). Set
the stack size to 0x400. Next, select the Compiler tab. Note that “Full Symbolic
Debug (-g)” under “Generate Debug Info:” in the Basic Category is
selected. On the Feedback Category pull down the interlisting options and select “C
and ASM (-ss)”. On the Assembly Category check the Keep generated .asm
Files (-k), Keep Labels as Symbols(-as) and Generate Assembly
Listing Files (-al). The –as will allow you to see symbols in the memory
window and the –al will generate an assembly listing file (.lst file). The listing file has
limited uses, but is sometime helpful to view opcode values and instruction sizes. (The
.lst file can be viewed with the editor). Both of these options will help with debugging.
Then select OK to save the Build Options.

Build and Load

3. Click the “Rebuild All” button and watch the tools run in the build window. Be
sure the “Load program after build” option is selected in Code Composer
Studio. The output file should automatically load. The Program Counter should be
pointing to _c_int00 in the Disassembly Window.

D- 14 TMS320C28x DSP Workshop – Appendix D – C Programming

 Lab D: C Optimization

Set Up the Profile Session

4. Restart the DSP (debug Æ restart) and then “Go Main”. This will run
through the C initialization routine in Boot.asm and stop at the main routine in
LabD.c.

5. Set a breakpoint on the NOP in the while(1) loop at the end of main() in LabD.c.

6. Set up the profile session by selecting Profiler Æ Start New Session.

Enter a session name of your choice (i.e. LabD).
7. In the profiler window, hover the mouse over the icons on the left region of the window
and select the icon for Profile All Functions. Click on the “+” to expand the
functions. Record the “Code Size” of the function sop C code in the table at the end of
this lab. Note: If you do not see a “+” beside the .out file, press “Profile All Functions”
on the horizontal tool bar. (You can close the build window to make the profiler window
easier to view by right clicking on the build window and selecting “hide”).

8. Select F5 or the run icon. Observe the values present in the profiling window. What do
the numbers mean? Click on each tab to determine what each displays.

Benchmarking Code
9. Let’s benchmark (i.e.count the cycles need by) only a portion of the code. This requires
you to set a breakpoint pair on the starting and ending points of the benchmark. Open the
file sop-c.c and set a breakpoint on the “for” statement and the “return”
statement.

10. In CCS, select profiler Æ enable clock (must be checked). Then select
profiler Æ view clock.

11. Now “Restart” the program and then “Run” the program. The program should be
stopped at the first breakpoint in sop. Double click on the clock window to set the clock
to zero. Now you are ready to benchmark the code. “Run” to the second breakpoint.
The number of cycles are displayed in the clock window. Record this value in the table
at the end of the lab under “C Code - Cycles”.

C Optimization
12. To optimize C code to the highest level, we must set up new Build Options for our
Project. Select the Compiler tab. In the Basic Category Panel, under “Opt Level”
select File (-o3). Then select OK to save the Build Options.

13. Now “Rebuild” the program and then “Run” the program. The program should be
stopped at the first breakpoint in sop. Double click on the clock window to set the clock
to zero. Now you are ready to benchmark the code. “Run” to the second breakpoint.
The number of cycles are displayed in the clock window. Record this value in the table
at the end of the lab under “Optimized C (-o3) - Cycles”.
14. Look in your profile window at the code size of sop. Record this value in the table at the
end of this lab.

TMS320C28x DSP Workshop – Appendix D – C Programming D - 15

Lab D: C Optimization

Benchmarking Assembly Code

15. Remove sop-c.c from your project and replace it with sop-asm.asm. Rebuild and
set breakpoints at the beginning and end of the assembly code (MOVL & LRETR).

16. Start a new profile session and set it to profile all functions. Run to the first breakpoint
and study the profiler window. Record the code size of the assembly code in the table.
17. Double Click on the clock to reset it. Run to the last breakpoint. Record the number of
cycles the assembly code ran.
18. How does assembly, C code, and oprimized C code compare on the C28x?

C Code Optimized C Code (-o3) Assembly Code

Code Size

Cycles

End of Exercise

D- 16 TMS320C28x DSP Workshop – Appendix D – C Programming

 OPTIONAL Lab D2: C Callable Assembly

OPTIONAL Lab D2: C Callable Assembly

Note: The lab linker command file is based on the F2812 memory map – modify as needed, if
using a different F28xx device memory map.

¾ Objective

The objective of this lab is to practice and verify the mechanics of implementing a C callable
assembly programming. In this lab, a C file will be used to call the sum-of-products (from the
previous Appendix LabC exercise) by the “main” routine. Additionally, we will learn how to use
Code Composer Studio to configure the C build options and add the run-time support library to
the project. As in previous labs, you may perform the lab based on this information alone, or may
refer to the following procedure.

¾ Procedure

Copy Files, Create Project File

1. Create a new project in C:\C28x\Labs\Appendix\LabD2 called LabD2.pjt and
add LabD2.c, LabD2.cmd, and sop-c.c to it. Also, add the compiler run-time
support library to the project (C:\ti\c2000\cgtools\lib\rts2800_ml.lib).

2. Do not add LabC.asm to the project (copy of file from Appendix Lab C). It is only
placed here for easy access. Parts of this file will be used later during this lab exercise.
3. Setup the Build Options. Select the Linker tab and in the middle of the screen select
“Run-time Autoinitialization” under “Autoinit Model:”. Create a
map file by typing .\Debug\LabD2.map in the Map Filename [-m] field.
Do not enter anything in the “Code Entry Point (-e):” field (leave it blank).
Set the stack size to 0x400. Next, select the Compiler tab. Note that “Full
Symbolic Debug (-g)” under “Generate Debug Info:” in the Basic
Category is selected. On the Feedback Category pull down the interlisting options and
select “C and ASM (-ss)”. On the Assembly Category check the Keep
generated .asm Files (-k), Keep Labels as Symbols(-as) and
Generate Assembly Listing Files (-al). The –as will allow you to see
symbols in the memory window and the –al will generate an assembly listing file (.lst
file). The listing file has limited uses, but is sometime helpful to view opcode values and
instruction sizes. (The .lst file can be viewed with the editor). Both of these options will
help with debugging. Then select OK to save the Build Options.

Build and Load

4. Click the “Rebuild All” button and watch the tools run in the build window. Be
sure the “Load program after build” option is selected in Code Composer
Studio. The output file should automatically load. The Program Counter should be
pointing to _c_int00 in the Disassembly Window.

5. Under Debug on the menu bar click “Go Main”. This will run through the C
initialization routine in Boot.asm and stop at the main routine in LabD2.c.

TMS320C28x DSP Workshop – Appendix D – C Programming D - 17

OPTIONAL Lab D2: C Callable Assembly

Verify C Sum of Products Routine

6. Debug using both source and assembly (by right clicking on the window and select
Mixed Mode or using View → Mixed Source/ASM).

7. Open a memory window to view result and data.

8. Single-step through the C code to verify that the C sum-of-products routine produces the
results as your assembly version.

Viewing Interlisted Files and Creating Assembly File

9. Using File → Open view the LabD2.asm and sop-c.asm generated files. The
compiler adds many items to the generated assembly file, most are not needed in the C-
callable assembly file. Some of the unneeded items are .func / .endfunc. .sym, and .line.

10. Look for the _sop function that is generated by the compiler. This code is the basis for
the C-callable assembly routine that is developed in this lab. Notice the comments
generated by the compiler on which registers are used for passing parameters. Also,
notice the C code is kept as comments in the interlisted file.

11. Create a new file (File → New, or clicking on the left most button on the horizontal
toolbar “New”) and save it as an assembly source file with the name sop-asm.asm.
Next copy ONLY the sum of products function from LabC.asm into this file. Add a
_sop label to the function and make it visible to the linker (.def). Also, be sure to add a
.sect directive to place this code in the “code” section. Finally, add the following
instruction to the end:

LRETR ; return statement

12. Next, we need to add code to initialize the sum-of-products parameters properly, based
on the passed parameters. Add the following code to the first few lines after entering the
_sop routine: (Note that the two pointers are passed in AR4 and AR5, but one needs to
be placed in AR7. The loop counter is the third argument, and it is passed in the
accumulator.)

MOVL XAR7,XAR5 ;XAR7 points to coeff [0]

MOV AR5,AL ;move n from ACC to AR5 (loop counter)

SUBB XAR5,#1 ;subtract 1 to make loop counter = n-1

Before beginning the MAC loop, add statements to set the sign extension mode, set the
SPM to zero, and a ZAPA instruction. Use the same MAC statement as in Lab 4, but use
XAR4 in place of XAR2. Make the repeat statement use the passed value of n-1 (i.e.
AR5).

RPT AR5 ;repeat next instruction AR5 times

D- 18 TMS320C28x DSP Workshop – Appendix D – C Programming

 OPTIONAL Lab D2: C Callable Assembly

Now we need to return the result. To return a value to the calling routine you will need to
place your 32-bit value in the ACC. What register is the result currently in? Adjust your
code, if necessary.

13. Save the assembly file as sop-asm.asm. (Do not name it LabD2.asm because the
compiler has already created with that name from the original LabD2.c code).

Defining the Function Prototype as External

14. Note in LabD2.c an “extern” modifier is placed in front of the sum-of-products function
prototype:

extern int sop(int*,int*,int); //sop function prototype

Verify Assembly Sum of Products Routine

15. Remove the sop-c.c file from the project and add the new sop-asm.asm assembly
file to the project.

16. Rebuild and verify that the new assembly sum-of-products routine produces the same
results as the C function.

End of Exercise

TMS320C28x DSP Workshop – Appendix D – C Programming D - 19

Solutions

Solutions
Lab D Solutions

C Code Optimized Assembly

C Code Code
(-o3)
Code Size 27 12 11

Cycles 118 32 22

D- 20 TMS320C28x DSP Workshop – Appendix D – C Programming