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Uart Basys3

UART Introduction

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devansh saxena
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17 views14 pages

Uart Basys3

UART Introduction

Uploaded by

devansh saxena
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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UART

●
Universal asynchronous receiver-transmitter :
Asynchronous serial communication
●
Data format and transmission speeds are configurable
●
Used in microcontrollers, automobiles, smart cards etc
●
Two wires to transmit data between devices: Tx. Rx

Parallel to Serial to
serial parallel
Transmit data LSB --> to MSB
Data sent in bytes (LSB first)

https://projectfpga.com/uart/
Convert to
frame

Parallel to serial

Serial to parallel

Transmit serially (LSB


first)
Configurable parameters
●
Baud rate – This is the number of bits sent per
second. Reads incoming data at that rate
– 300bps, 1200bps, 2400bps, 4800bps, 9600bps,
19200bps, 38400bps, 576bps, 115200bps.
●
Number of data bits – size of each data frame: 5
to 8 bits
●
Parity bit – Parity bit is used to check for single bit
error or errors of odd number of bits. On/Off. If
off, max data bits can be 9
UARTto USB bridge
or connector on
Basys3

This needs to be
mapped
Adding two bytes
Data1 + data 2
start=0 stop=1

0 0 1 1 0 1 0 0

LSB is
transmitted
first
start=0 stop=1

1 0 1 1 0 0 1 0

LSB is
transmitted
first
start=0
Sum is trasmitted stop=1
Back from uart
LSB first

1 0 0 1 1 1 1 0 1 1
●
115200 bits are transmitted per second
– 1/115200 is the transmission time per bit = 8680ns
●
Bpsclk period is 8680ns
●
Bit count decrements once per clock period of
bpsclock
●
Uart module and adder module in PL need to communicate and
synchronise
●
When m_axis_tvalid=1, adder reads valid data from the uart module
●
m_axis_tvalid is made high by rx module
– when rxd_reg or rxd goes high, (which is made high in the tb in the
fsm), tvalid is made high to indicate end of the data byte. this is
done when bit count reaches 0. rxd_reg=1 indicates end of the
frame
– This is when data=44 is sampled by the data (although rxd has
gone high earlier, it waits for some time before making tvalid go
high)
●
Prescale_reg is initially 0 and bit_cnt=0.
●
When rxd_reg=0, valid data is present
– prescale_reg is initialised to 430 (i.e 108*4) and bit count to A (if
data width=8)
--> 108 is 100M/(115200*8)
●
Then Prescale is counted down every clk till it becomes 0
– Now, check bitcount. If it is A--> count bitcount down, re-initialise
prescale to 108*8.
– Append the data bits when bit count is 8, 7, 6...0--> bit count
reaches 0--> capturing the 8 bits of data from rxd_reg into
data_reg
●
Once bitcnt reaches 0, (and rxd=1 already), data has
ended. Tvalid can go high, and the data_reg can be
captured by the adder
– data_reg=44
– Similarly for 2nd data
●
Finally when s_axis_tvalid in tx is high (made in
topcontroller.v FSM state 2), data from adder (sum) is
sent on the tx to the PC
●
To summarise, the bit-cnt, prescale and the if-else logic are used to
make sure that a valid data bit is captured once every 8680ns,
appended to data_reg and sent to the adder module (when tvalid=1)
●
The if-else blocks also make sure we do not capture the start and stop
bits- but just the 8bits of data
●
bpsclk’s neg edge co-incides with the valid data bit being captured. (this is
also when prescale is supposed to hit a max value)
●
Data width is set using DATA_width and parameterised

Valid data bits

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