PLC HW & Programming
PLC HW & Programming
Amit Nevase
Lecturer,
Department of Electronics & Telecommunication Engineering,
Karmaveer Bhaurao Patil Polytechnic, Satara
Objectives
PAPER
TH TU PR TH PR OR TW TOTAL
HRS
system.
Input modules serve as the link between field devices and the
PLC’s CPU.
AC or DC.
24 VAC 24 V dc
48 VAC 48 V dc
Input Input
Module Module
24 Volts
Common Common
230 Volts
Common Common
120 Volts
LED
module has.
+
Input Power Noise & Threshold Optical Input
Signal Conversion Debounce Detector Isolation Logic CPU Status
- Filter Table
LED
an OFF state.
Input
Device
+ +
Input Input
Module Module
- -
Input
Device
(a) (b)
Output Output
Module Module
- +
Output Output
Load Load
(c) (d)
230 V dc
24 V dc, sink
24 V dc, source
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Typical Wiring Details of Output Module
Output
Module
Output 2
Output 3
Output 4
Output 5
Load
120 VAC
Signal From
CPU operates switch COM
User supplied
Power for
Field devices
Fuse
Signal Latch Triac Controlled
Optical Filter
From Logic Switching Device
Isolation
CPU Circuit Circuit
LED
ON or OFF
Signal from
Output status
table
Fuse
Relay
Switching
Device
Power Fuse
Signal Latch Transistor Controlled
Optical Filter
From Logic Switching Device
Isolation
CPU Circuit Circuit
LED
Number of Outputs 16
ON= 0.1 ms
Maximum Signal Delay
OFF= 1.0 ms
User
Connection
+
User
Connection
+
COM
I=Input Module
O=Output Number
X :X X X / X X
Terminal
Number
Rack
Number
1 I:012
I:012
04
Instruction is TRUE
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 I:012
I:012
04
Instruction is FALSE
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Examine If Closed (XIC) Instruction
0 I:012
I:012
04
Instruction is TRUE
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 I:012
I:012
04
Instruction is FALSE
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Examine If Open (XIO) Instructions
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 O:013
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 I:012
01 04 01
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 O:013
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 I:012
01 04 01
Sr.
Instruction Name Description
No.
Counts time-based intervals when
1 TON On Delay Timer the instruction is true.
True
TON
TIMER ON DELAY
EN
Timer T4:0
Time Base 1:0 DN
Preset 15
Accumulated 0
Time base —The time base (which is always expressed in seconds) may be
either 1.0 s or 0.01 s. In the example shown, the time base is 1.0 s.
Preset value —In the example shown, the preset value is 15. The timer
preset value can range from 0 through 32,767.
Accumulated value —In the example shown, the accumulated value is 0. The
timer’s accumulated value normally is entered as 0, although it is possible to
enter a value from 0 through 32,767. Regardless of the value that is
preloaded, the timer value will become 0 whenever the timer is reset.
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TON Instruction – Control Word
Timer Element
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word
EN TT DN Internal Use 0
timer instruction is true. When the timer instruction is false, the enable bit is
timing. When the timer is not timing, the accumulated value is not changing,
Done (DN) bit —The done bit changes state whenever the accumulated
value reaches the preset value. Its state depends on the type of timer being
used.
True
Time base —The time base (which is always expressed in seconds) may be
either 1.0 s or 0.01 s. In the example shown, the time base is 1.0 s.
Preset value —In the example shown, the preset value is 15. The timer
preset value can range from 0 through 32,767.
Accumulated value —In the example shown, the accumulated value is 0. The
timer’s accumulated value normally is entered as 0, although it is possible to
enter a value from 0 through 32,767. Regardless of the value that is
preloaded, the timer value will become 0 whenever the timer is reset.
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TOF Instruction – Control Word
Timer Element
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Word
EN TT DN Internal Use 0
timer instruction is true. When the timer instruction is false, the enable bit is
timing. When the timer is not timing, the accumulated value is not changing,
Done (DN) bit —The done bit changes state whenever the accumulated
value reaches the preset value. Its state depends on the type of timer being
used.
PB1 RTO
RETENTIVE TIMER ON
EN
Timer T4:0
Time Base 1:0 DN
Preset 7
Accumulated 0
T4:2 PL
DN
------------------------------------------------------------------------------------
Acc Value = Pre Value
------------------------------------------------------------------------------------
7
6
5
4
------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------
3
RTO – Timer Sequence
2
1
When rung condition goes false
0
Accumulated Value retained
------------------------------------------------------------------------------------
True
False
Off
Off
Off
On
On
On
Accumulated
PL Output
Timer T4:2
Time Input
Timer T4:2
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Enable Bit
Done Bit
Value
RES – Reset Instruction
Reset T4:2
RES
Sr.
Instruction Name Description
No.
Increments the accumulated value at
each false-to-true transition and
1 CTU Up counter retains the accumulated value when
an off/on power cycle occurs.
Decrements the accumulated value at
each false-to-true transition and
2 CTD Down counter retains the accumulated value when
an on/off power cycle occurs.
Counter
Value
+4
ON
Accumulated Value= preset = output
OFF
C5:0/CU C5:0/OV
Counter Enable Bit Overflow Status Bit
C5:0/DN C5:0
Counter Reset
RES
Counter Done Bit Instruction
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
PRE Value =7
7
------------------------------------------------------------------------------------
7
6
6
5
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5
CTU – Up Counter Sequence
4
4
3
3
2
2
TRUE 1
------------------------------------------------------------------------------------
FALSE
1
Accumulated
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Count Up
DN Bit of
Counter
Reset
Input
Value
CTU – UP Counter Instruction
Counter Number —This number must come from the counter fi le. In
the example shown, the counter number is C5:0, which represents
counter file 5, counter 0 in that file. The address for this counter
should not be used for any other count-up counter.
Preset Value —The preset value can range from 232,768 to 132,767.
In the example shown, the preset value is 10.
C5:N Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Word
C5:N:0 CU CD DN OV UN UA INTERNAL USE (not addressable)
0
Word
C5:N:1 PRESET VALUE
1
Word
C5:N:2 ACCUMULATED VALUE
2
Counter
Value
-5
ON
Accumulated Value= Preset = output
OFF
C5:0/CD C5:0/UN
Counter Enable Bit Underflow Status Bit
C5:0/DN C5:0
Counter Reset
RES
Counter Done Bit Instruction
------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
7
------------------------------------------------------------------------------------
PRE Value
1
6
2
5
CTD – Down Counter Sequence
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3
4
4
3
5
2
6
TRUE 1
7
------------------------------------------------------------------------------------
FALSE
Count Down
Accumulated
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DN Bit of
Counter
Reset
Input
Value
CTD – Down Counter Instruction
Counter Number —This number must come from the counter fi le. In
the example shown, the counter number is C5:0, which represents
counter file 5, counter 0 in that file. The address for this counter
should not be used for any other count-up counter.
Preset Value —The preset value can range from 232,768 to 132,767.
In the example shown, the preset value is 10.
C5:N Bit 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Word
C5:N:0 CU CD DN OV UN UA INTERNAL USE (not addressable)
0
Word
C5:N:1 PRESET VALUE
1
Word
C5:N:2 ACCUMULATED VALUE
2
down counter.
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CTU – UP Counter Instruction Control Word
Sr.
Instruction Name Description
No.
MOV
MOVE
Source N7:30
Destination N7:20
Destination N7:20
N7:20
When the rung is true, input switch A closed, the value stored at the
source address, N7:30, is copied into the destination address, N7:20.
When the rung goes false, input switch A opened, the destination
address will retain the value unless it is changed elsewhere in the
program.
The source value remains unchanged and no data conversion occurs.
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MVM Instruction
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Source B3:0
1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 Mask FF0F
Perform Bitwise OR
2 OR Logical OR
operation
Perform inversion of
4 NOT Inversion
given source
B3:0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0
B3:1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0
B3:2 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0
B3:0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0
B3:1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0
B3:2 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0
B3:0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0
B3:1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0
B3:2 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0
Source B3:0
Destination B3:1
The NOT instruction is used to perform the NOT logic on the value in
the source, bit by bit. The output logic value returned in the
destination is the one's complement or opposite of the value in the
source.
B3:0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0
B3:1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1
CLEAR
Destination B3:1
B3:1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Source B N7:40
Source B 25
Source B 200
Source B 350
Source B N7:12
Source B 457
Applied
Voltage
(a)
Input
A
Input Input Output
Input
A B
B
Output
(b)
(c)
B
Input B
Applied
Voltage (c)
(a)
Input
Output A
Input A
Input
B
Input B
Output
(b) (d)
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Ladder Diagram for NOT Gate
A
Applied
Voltage
(a)
Input
A
Input
Output
A
Output
(b)
(c)
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Ladder Diagram for NAND Gate
Output Input
Input A A
Input
Input B B
Output
(a) (b)
Input
A
Output Input
Input A Input B
B
Output
(a) (b)
Input
A
Output Input
Input A Input B
B
Output
Input A Input B
(b)
(a)
Input
A
Output Input
Input A Input B
B
Output
Input A Input B
(b)
(a)
Output
A
Output B
Output
B
Input
A
Input
Output A
A
Input
B
Output B Output
A
Input B Output
B
A
Y
B C
A C Y
C
D
A C Y
B D
A
Y
B
C
A B Y
C
D
A B Y
C D
B
Y
A
A B Y
A
Y
B
A C Y
A B C Y
C D A Y
Y AB C
A B Y
A C D Y
A B C Y
D E F
A B C Y
A B C Y
A B C
A B
A B
1 1
0 0
SW Lamp
0 1
1 0
SW Lamp
0 0 1 0
0 1 0 0
1 0 0 0
SW1 SW2 Lamp 1 1 1 0 1
0 0 0 0
0 1 1 0
1 0 0 1
SW1 SW2 Lamp 1 1 1 0 0
0 0 0 0
0 1 1 1
1 0 1 1
SW1 SW2 Lamp 1 1 1 0 0
0 1 0 1 0 0
SW1 SW2 Lamp 2
1 0 0 0 1 0
1 1 0 0 0 1
SW1 SW2 Lamp 3
TOF
EN
TIMER OFF DELAY
Timer T4:2
Time Base 1:0
Example 21 Preset
Accumulated
10
0
DN
TOF
EN
TIMER OFF DELAY
Timer T4:3
Time Base 1:0
Preset 15 DN
Accumulated 0
T4:1/DN M1
T4:2/DN M2
T4:3/DN M3
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Example 22
TOF
TIMER OFF DELAY EN
Timer T4:1
Time Base 1:0
O:0/0 Preset 10 DN
Accumulated 0
T4:1/DN M2
O:0/1
Example 22
Exit SW CTD
COUNT DOWN COUNTER CD
Counter C5:2
I:0/1 Preset 150
DN
Accumulated 0
C5:1/DN
Lot Full Light
O:0/0
Reset C5:1
RES
Example 23
O:0/0
I:0/0 I:0/1
TON
TIMER ON DELAY EN
Timer T4:1
Time Base 1:0
O:0/0 Preset 20 DN
Accumulated 0
T4:1/DN
Example 24 M2
O:0/1
T4:1/DN TON
TIMER ON DELAY EN
Timer T4:2
Time Base 1:0
Preset 20 DN
Accumulated 0
T4:2/DN M3
O:0/0
I:0/0 I:0/1
T4:2/DN M2
Example 25
TON
TIMER ON DELAY EN
Timer T4:1
Time Base 1:0
O:0/0 Preset 10 DN
Accumulated 0
T4:1/DN TON
TIMER ON DELAY EN
Timer T4:2
Time Base 1:0
Preset 15 DN
Accumulated 0
O:0/0
I:0/0 I:0/1
TON
TIMER ON DELAY EN
Timer T4:1
Time Base 1:0
O:0/0 Preset 10 DN
Accumulated 0
T4:1/DN T4:2/DN
M2
O:0/1
TOF
TIMER OFF DELAY EN
Timer T4:2
Time Base 1:0
O:0/0 Preset 15 DN
Accumulated 0
Example 26
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Example 27
O:0/0
I:0/0 I:0/1
TON
TIMER ON DELAY EN
Timer T4:1
Time Base 1:0
O:0/0 Preset 300 DN
Accumulated 0
T4:1/DN T4:2/DN
M2
Example 27 O:0/1
TON
TIMER ON DELAY EN
Timer T4:2
Time Base 1:0
O:0/1 Preset 600 DN
Accumulated 0
T4:2/DN Stop M3
Programmable Logic
Controllers – F. D. Petruzella
Introduction to Programmable
Logic Controllers – Gary
Dunning
Programmable Logic
Controllers – Jhon Hackworth,
Federic Hackworth
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Online Tutorials
https://www.courses.ps
u.edu/e_met/e_met430
_jar14/cgroup.html