UNIT-1

Intzoduction to HP:
Tntzoduc hion, Application, Basic BlooK Diagram
Speed, oDzd size, MeMoIEy Capacily, classiticahiog ot HP:Men iorn
t dlheuent Ps used
P BLS5eatutes. AzchitechuE,- BlucK Diagtan, Ceneial Puzpt5e
Hegiskrs Kcgislou Palzs. Flags, StacK Piinou, Pubgzanm Counier, lypes ot
BuSes, 1ultiplexed addrcess ared Data Bus eneratiin o Conhol
6ignals, Pin Desczipho b 9165 4P, Basic intezlacing conceps
Maoy mapped 1/0 a0d 1/D mapped 10.

MICROPRCESSURS
A micuolrocessurc is cn cincuit (1c) which intonporcale
Tnhegzalked
me corte þunckions bta compLlerz's CPD.
Fi6 a pIrogrammable, mMulkipuszposc, clocK duiven,zegislkz baisce
elchzonic device dbak veads binazy insuchioas huom a skozzge
deviLt cALd mEmorzy, LLEpls binazy dalt as input aLDIzing to

ht inshzuclions and pzovidzs ZEsult cs ouwlput

Preaessci
HP is he lakesh and upgunded vension e CPU
Hzecesor is capabl6 pezozal Kinds of Coipuing Cind vsilhmel
p

tuochions ohilt yP deals in B105 an4 memouy tizuils in addiliog

Peizhomina all CPU FLunchonb
 ()
Applicnt iuts bf Micrul'tucessod
Ic wide vange of opplicetons bt P con be. bruondl1y classikie
mh 2 (nleqveies.
Ccneal Hurpose. Applicahon.
speciat Puepusc Applicnkico.

L4EICalupse Applicahions
S1gle B0ad dlics(0 compulOLS
Thes6 rute Simple and chtap. hey have oininnLiM possible sotheu
ar4 havzducant (onkiquZdlion, usedo traün Shudals, bwld small
Compulti beise Sysleat

2 PeusD1al Copuleous
These ade madé up tt a G bit P, ustd uz plagjing gantes
lenning Siiple Hrsonzams
6 bit toApLulevLS Sed jiu vo0 VroceSSINg payccl, business
ALLOunt, el

8Sulperc Minis Avnd CAD

hcic
32 bit YrocESScuS ustd iv buil4 powenul mieo(oMpuriorcs.
and inicompuhets
peujtamanIG 15 beka han mainFizame
ThSe axc used m Engintezing Side as Conmpulot aied design
q1achints
 5pecial Puzpose Applications.

InsktLinmérntatior prüguaommabibly
inshtumment con be inhelligent using keakue
HP based als0
Contollens in vavtious inshtumenls. Thty
ae

APCAO be uised a
tEmpenzbuae GP
Us inmtdical inslzumentakion tp
meASLUZE

Contrzol 51Ich as iiCLOOWC

awailable m home appliances
P COnollezs cutE N0LO
irndLislicie, wá£4 n conl1olling
OvEn Ashing machine
SLIch a5 specd teMp, piLeSSwLe mDiSlLuLE
VAUZiOuS przoces5 az.ameleus

8 ConintLmicatipn-
indushzits, yPs ace_used in digital telephone seis,
lelephane
telephon_ exchangE and mBAem at Narisnal lkvel.
Iheyate use4 in Railway Resezvation Syslen
also
at inkznahional level
A11d Aiz Resenhon Syskan
Phones ama TV aze AlSD_1Sing
SakEit CODImLi)icalipn Syshkm, mebilE

Hiblicakion-
DHice Aukonnakitn and
oith heAvailability inexpenSive ancd usen hziendy micTOCOmpuleS
b
wide zmge 50 Fuoarze paoAges bttice OoKs _At
,
alorguailh
in otpice To péz{uzM WCnA rrecessing,
COmpukorzised HPs aNe use
5preadshtels operzakion, stuungE and
uehieval huge infiZviahion.
to maKe auHmahc Phuln lepies
1 Peiblishing houseS, HPs asL use
in pizinhing
based Lase zinkrs sEd to achlevt. gutd 5peL
P
 0ate

BASIC BLUCK DIAGRAM OF MICRoPRUCESSOR

Tput Devite Miczo oCess oz. Dukput Device

ALU
CU
Register Aruriay

MiccPoces5o4 15 a_Cmtrzclling unit oa n1ic0- Compultiz, ab7iccked

Dn a SMell chip eapoble to pezfozm_ALU opeZakions and
ConMoMLIniGaking oim Dhen devices conDEcked o it
MiczoPDLLS50rZ onsisks t An ALU, Zeqishn
Azzy and a Lonhsl.
Unit
ALU ptrzt zms_Uz1kim6.rical and lugical
opezations on he daka
LELeived tCm_memo DIZ_1n inpuk Zeuize

Kegishez Arzay Consisls t aegisherts

BC D, E, HL and aLLumul atozs
idenikied by letens
Acra mpozzurzily usEdprzimazily to 6hont
duzing Proguzm ejCtukiin and
a
Ho userz tarzough in9 tuze_aGcts iblt
htuclions
Control Lit controls -the
daka Flow and nshzucions wilhin ht
Compulcr
 FreauenHly used letms in a Micrzoluwcessa.

Inshrzuctiorn Set - it is dhe set ot inshauchions Ahat a HP LAn underzshand

Banduidm- nuombert of bits przocessed in a single inshzuchion

locK 5peed-it qchemines he n0 oh openarions ped second he

Peocessor can ptruhpram npruesed in megaheulz CM1Z) D
gigaheutz . GHz)I is alsD talled CloeK Ralc.

5pecd how meny biks o qeia pieocessec pen se tond Cin

c locK ptilse Expressed in bils per Second
pne

worzd sizenoo bits oh dala extcukeel by yP in ont dyele of

EXELuion Forz 208, wond Size is a bit aod orz eD8b, it is
16bit
6 Memorzy Capaciy-lptal amoLunt ot memoray aLessed by.a pazicula
HP
no nMemurzy 1oLation= 2-Mmorzy cpacihy,
n is no b AddZESS ines in a HP
 FzEaently used TetMs in a Micrzofrocessat

Insrzuction 5et - it is the set ot inshtuchions that a HP wn undenshana

inskrzuchipn.
6aridwidh- numbert o biks przocessed in a Single

dhe-
Lloc speed-it dchuumines he no bt opeuarions peu setond
Meocessorn (Anpehprzrn tupruessed in megahezhz CMHZ, on
IF is aluD talltd CloeK Ralt.
gigahtalz lGHz)
one
46pecd how mony biks o qela picoGesste ptu SeLondCin
c lDeK pulSe Exprcessed in bils peu seconed

wird size- no_ o birs ot dala extluked by J4P in onE Cyele c

bit a04 orz 2D2b,it ic
ExELuion Forz 2085 worLd size is

1b bit

MaiDray Capacity-lotal amoint memory ALLeSse bya paniculas

HP
no Mtmory focahion 2-Mem0rzy capaci,
n is no: b addreSs ines in a HP.
3085 MICROPROCESSDR.

as 'edniy-eighty- bive micuoPaocesspd.Th is

3085 is pronounced
designed by INTEL in 1177 using riMo
an 8085 ticotraocessDrE

Technoiogy adduessing byk

geOeEal pupose qP tApable o
t
8 bit
T is 0
ona single
isa 40 pin l . paiha4 habticaked
Mamora Powe supply and
15T chip IzcqLuineS a t5V dc 5ingle can

Singlc phase clocK

opezak with a BMHz
T has 4hc hollouoing Congiguiation
8 bit deha bub
1b bit adduess bus, uohich can adduess upho GH KB
b i t Kzogzam Counk.

lb bit Shacs Poink.

3-bit zEqiskIs avtLengedin pairzs : B , DE, HL
6cqines +5V Supplyco opezale at 3:2 MHz single Phas
clDcK

u s e 4 in washing mozhine nuizIZDOANEDVen, mobile Phones

Anchitecburze t 085 MlrcKzsLessuz

Ine initmol auchikthute of 8085 1P includes ALU,

Timing cn Conuol Voit ushzuzhion zegisle a DeLodtr,
Rrgish Anzay nteviaupt Conizol and Sevuial TID
conbveo
 Intecrdupt Contuol
-bi Serlal I/0 Conol.
intertnal Dara Bus. t Arz.chibectuze ot 3085 MP

Inshzudrion
Temportasuy Regise () Multiplexert
Regis
(8)
Temp. Reg ToMp Rg
AcGLmmtt-
1ator F1ag
Flip-Flops Rigiset

Insuhon
A Deoder and
() L
L Machine
Cyele dntoeing
Stack Poinkert
Pr0grranm Counterd
14)
Inencnhcnb/ Detruimcnt
+5V AAdues5 Lakch
Powtu Suppy L qd

Contrz pl Vnit (1)Data/AA4ELS5 )

Timing and Addres5
Bus
AD1-Abe AAd- 5u6
As-As add bus
O ALU
a5 h e name suggEshs, it pézozms azihmeic tnd logical
0pezatio05 line addition,6Lubstzackion, ÅND, DR ch on s bit
dala

Tinming AND COntzol Unit

it provides tinib1g and conkuol signals d0 he IP Ao pevrtoizm
operLatio0s. Fotlowing aie he tiing and Conkuol signals vohich
Conhzol eutemal and iokecnal cidcuils..
Conbuol SignalsREADY, RD, WR ALE ,

5talus S1gnals 3CD 51), 10/M

DMA 6iguals HOLD HLDA.
RESET 5iqnals RESET IN, RESET DLT.

InstZuchiun Recgister and Decudet

t is S bit ztgiski when A) nshiuckion is jehzbed hizon
MC1o dh ît 1S S:01Cin ibt islzuclio) HEqisleu
skiucliDn Decodeu doco4ts he inlozmeikion prrésent in.
inskzudicn ztgisle

TnteLAgk Cunbztl
As name S1ggebhs, it Lonluols the inkerriupls duzing a p:oLc4s
ohcntven a HP is _eNeLuhing a main Proguam Cunc ohentve
4n inkeZupt uctuts, yP shi15 dhe Lontrol
Z0M main Puoguam

Alez a t zesucs is Complcked, ht tonlTzol gpes bacx t0 Ah

iin 0gzA01
hene ntE5inkertzupt siginls in 8Dg5 P
INTR RST 7, RST65 RST 55. TRAP
Serial I/0 Conkreol
t
(onkeols he SeZial
S1D (Seuiad dala tommunicahion
by S tng 1hest 2
oput Dala) and $0D inshaclious
(Seuial Dulput Daa)
Address Bus and Data Bus
Dala BuS CaZIeS
he doka to be
Address Bus Caies he shoL.ee Th is
bidivecht nal.
And il is
lotahion do whenC.it should be dhoucd
nidiutclional T is ISed to tuansten dola
1/0 devices and addness

Kegiskens ir 8U85
Ragisks in 8085 P Can be
depending biznadly classijied ino 2 typts
on
egisl unchons
CtEnEZal Yurzpose Kegislcusate in
6.C, D,E. 2085 HP 1t
Hand L
Cich Regishu LAn hold an 3 bit
lhEse LEgislcES Can LCDICK n pairs tu lntld 16 bit cala eiala.
Paiging Combinalion s tnd hcit
B- E,HL
5pEzial Yuzpose Kegisku- std tu
apaszk rTG dala Sluzage
Prztzm Sptcial unchit ns

FLas
itis an s bit cgislci having 5 1-bit flip tLops, which hnld
Cihen D 0 4cpending upo 1ht 1t5ult 5houed in ALumIlator.

5tan Fla-10s 6igniticant bit ot 4ht zesult available. at ALU

is ne\lecléd as sig) Flag. The
flag schs lo 1i ucsull bh an oped
15 Ve clse 0.

Zeno Flag-i rzesult ot an au ibnnchiz ut logit ppetahion 15 Zero,

Ahen Zouo Flag is set ckt KCSet
 Pag

FLuaill ay Cauuy Fla4 whilc peiconunA an avcilhvic¥ic gpéuiiO

1A Cavey is geneualcd trzo 3ne bib Ho 41h bit, dhc tuX1llCuy

CUy Lag uoil be sel oc eset

avzily Flag- tzesull conlains tveN no oh 1s, hen Yavily

Flag set else Esel

|Cany lag- i dheze is a calwy orz bwoou huon) an

uzillhmeli 0pevcakio. he cauy Flag is Sol

AccAmulatoz
it 16 ) 8 hit ucAislau LISCA 10 pez\o1z aszithnclicail, Log1cal
0 and LDAD/6T9RE Dperznhions i s conneched inéund
data bus an4 ALU

05taLK_ Yointen
it is 4$ tit ncg1skz wozKS linz SkatK, ohith is cluoa1s
inzrCmenked decucMcnked by 2 duuing push And pip
opeizaion

JO Pztazam Counberz
itis A 16 bit e4iskern_ ust to shoze memDIZy adduess
lDcakion
b ncxtinshzuchion o be exteuked
HP inoLemenls the pzogzana whenevt tn inshtichon is beng
ttLukedS0 Hoak dh6 przaAZA1_CCLuNnkz poins Au me8z
aclduess tnex inshuchtit q0ng u be
exttuke4.
2epLrLarzy Kcgisterns
2 Tempo.zAszs Regiskzs W_nel Z uscd to hold &bit delz
dung he EXBtubit) t St inshzudicns
 PIN CONFIGURATIO OF 30S5 MICRDPROCESSOR

CiK um 40 cc- *5V Ponoer suply

5ignal. L 3 HOLD
3 HLDA
RESET OUT 31 CLK DUT -Clh Pzea Signdl
50D RESET IN
51D 35 READY
TRAP 10/M Shatus
Inen- RST15
Cup
33 Signal
RST65 32 RD Contcol Signall
Sign
RST 55 D
31
INTR ALE
indeeupr ach:5 TA 2 Stahus
24
ADD 13 28
As Signal
AD 211 AM
Data AD2 2 Ag Address
Bus AD3 25 BuS
AD4 24 Au
AD 23 Ao
ADg 22
AD1 20 21 Ag
Povoet '6s
Suppy
indizaks CqrD Stgna

lhepin5 t 8165 micIolLLESSIZ is classifieZ inh_b groups

O Addrzess Bus
Ais-Ag,it Coits me MDst igmicant 8 bits t memoy
L/ nddress
 0ote
) pag

2 Data Bus
AD7ADo .it carziEs he 1ezsh signitican 6 bit odduuss
ADT
114 daln bus

Contzol and Status Signals

hese 5ignals arne used o identity hé nnkuc 0 opezeikion
ue aue 3 Conbeol Signals and 3 shalus 31ene'5.

3 Coolzol Signals aLc RD , WK And Al

KDS1gnal indicales lhat he selcehed 10_0vu mCwIDIy dcvicc isHo

be uCad n 1tady 1o acccpt dala availablc o0 dala bus.

106ignal indicales dala bus ic -1o be uiHen i o a Sclccheq

1MCmDy 0t 1D 1DLki0n

ALEAvc gong pulse genaualed when A nco Dpeuaion is shauled

by 3P vihen he pulse goes high, it indicales addue
when Low O gpe loud, indicals 4ala

3 6lalus Signals aut 10/M, S0, S.

10/M siqnal wcA lo diljcLentialc behuoeen 1D_And mEmo1a4

opeLalionb_ie whtn il is ligh, indicalcs 10 oprualion Aue vhtn
Lod, wdiLales A MemDIy 1Dcalion

1 nd 0 Signals uscd-lo incolijy lype o twouueak

optulion
Povoen Supply-
heut turt 2 poLoev supply ignals Vtt d Vss
VCL imdicehes tsv powen supply md Ves ivdicoles Gud
5igyil

Zlo Frauenay Signals

DesE i 1c.lue|e 3 Signals 1X2CLK DUT
XX2 a y slal is coneched at hebc 2 pir)s. hc Frueaec
is iltunly divided by 2 Thccoue, lo openzilc a SysheM at 3MHz
he cuyskal should haue A fruca ot 6 uyHz.

CLK OUT-Signal used A6 Syshe clook tuz chez deyicts

Exkernmally Initiated signals and Tntevaupis

Interm.upts aze the Signals qenerzzared by exheunal devies to
TZeALestdhe P Ho pevlpizm a tasn
5 inltzuupt 6ienals- TRAP, INTR , RST 75, R5T 4:5, BST 55

INTA1otznupk ACkntuledgement signel

RESET IN-wed to zesét dhe HP ty Seting the Yaog Conerz to0
RESET ÚUT- wbz4 ti zesek al tonnectd devize5 ohtn P is ntset

KEADY 5ignal indicakes hat the deuitt. is Edy Send t

Zective daa: KEADY is lou0, CP will wwt az KEADY tgu high.

HOLD 5ignal inditalts Ahat mbheiz ashrt is meAuEsling dhe use o

addrussad l a bus

HLDA ndicates CPU has netcivca HOLD ZEancst and it will

clinauiish dht bus in next Clocs cycle HLDA is Sch to low

at o HOLD Signal is rc»101¬
 Oate

RST 7-5, RST 5, RST 55- aun. meslruzt intemzupls.

hey Cuse ag inznal tTEstruzt to be tuuhmikically nSezked
hese ve_vEchze4 in henzLpls dhet dzzns het Jatg: Ce NIzol
to specic mantey 1ocakitns-

5ezial 1/t Signals

Seulal sigals- SOD did 51D, used 1oz souial cCiminicakitn.

50D oulpuu: SDD 1s set /szcset as specijicd by 5iM

inslzucli0n5

SID=dala D ehis tine s loaded into aecumailalorz uoheaeon

a Si inshauchion is
cxccuied

TyPES DF BUSES
A1s ADDRE33 BUS

808S McMDZy Teput 0utput

HP

D1
DATA BUS3

LOTROL BUS

3095 Bus StrZucture

Adduess Bus-
1 1
gDup tt 16 Lines qeneailly idenFitied as Au to A1s.
Adduess Br1s is uiclircccioal ic h¢ tils Jlou in oe ediuCzkion yeo
MPU A0 Peciplieul deviccs
he MPU uses he addrtess bus Ao perzhorzm the finsh opernakion
identiying a Perciphenal on a mempdy locakion
Data Bus
it is agroup o} 6 uiyes used forz qeilz Hod .htse lines are
bidizec tional dalz lone in boh disncohos behceen MPU and niGmoZy
and perzipheral deviees.
MPU sES Dala Buus o trnsler binazy nrzmalb).

Contzol Bus
ConprziseS o vazidus Single lines hat tauzray Synchonisalio) 6ignals
My SES Such tines to przovide timing signals

MPUMizrucesStZ Uni
nteczuphs in 8085
interacupts are. me Signals geneualtd by exteanal devices to
Treeuest he microproresorn to perzprn a ask
Thede are 5 inkerrupt slgnals TRAP, RST 75, RST 65,
R5T 5:5 and INTR

Jnheugupls are classijied inw pllouoing groups based on dheir

paszamchons

OVectoz Intenmupt
in his ypz ot inkerszupt, dhe inhewuph address is. Knoun do he
processorae4 RST 75, RST6:5, RST 5:5,TRAP

Non-vectun TnherTzupt
in dhis inkenzuupt, dhe ineozupk oddues5 not KnooN do ne pzoces0r7
50, inkeenupk dddaesis no Kanouon tp the Peocessord), nceds be
5ent eeznally by tn deviZe o pezpZM inlerIupls
e INTR

3MasKatle ntCuruupt-
in Ahis inteznuph, 0£ Lan disable fhe in zaupk by wziking Some
inGhzucions inho he przogram
E4 RST75, RST 65 BST 55

Hon- Mashable Intezzup's

here oE caonoh_disable ht inteuaupt by wrziking 50me
inshruchions inn dhe progaAM 4: TRAP

5utaTt Lokezrupe-
here progrianea has o add the inshmchHions into he progam
p cneCult he intérdtupt:

RSTO, RST1 RS72 RST7

Hazduwasee Inteunupt
a5 hascauoae mférr upt
integrupis pin n 8085 wsed
INTA.
TRAP R6T 7:5, L5, 5:5 ,