ECE 270 Introduction to Digital System Design Spring 2019

Homework 6
Due at the beginning of your scheduled lab period

Last Name (Printed): ______________________________________ Lab Div: _____ Date: ____________

E‐mail: __ __ __ __ __ __ __ __ @purdue.edu Signature: __________________________________________

Printed copies of these pages along with your original (hand-annotated, not photocopied) written solution in the
space provided (unless otherwise indicated) are required in order to receive credit. NOTE: The purpose of homework
is to provide an opportunity for practicing the kinds of problems you will be asked to solve on quizzes and exams –
copying the work of someone else does not accomplish this.

1. [6 pts] Simplify the function mapped below in terms of XOR or XNOR operators, draw a circuit
realization, and compare the cost of this “simplified” version with minimal SoP (NAND-NAND) and
PoS (NOR-NOR) realizations.

W W
1 1 0 0 Z
Y d 1 0 0
Z
0 1 d 1
Y
1 0 1 d Z
X X X

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ECE 270 Introduction to Digital System Design Spring 2019

2. [8 pts] Assuming the availability of both true and complemented variables, find the simplest (lowest
cost) realization of the function mapped below. Solution can be two‐level NAND, two‐level
NOR, single‐level open‐drain NAND/wired‐AND, or a “mixed” simplification that utilizes
XOR/XNOR gates. Justify your choice based on a cost comparison among all potential options.
Show the circuit for your final answer.

W W

0 d 1 0 Z
Y
d 0 d 1
Z
1 d 0 0
Y
0 1 d 0 Z

X X X

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ECE 270 Introduction to Digital System Design Spring 2019

3. [4 pts] Assume a hypothetical PLD has macrocells of the following configuration:

Determine the following:

(a) [1 pt] the maximum number of P‐terms available for a function realized by the macrocell if
D=0 and E=1

(b) [1 pt] the maximum number of P‐terms available for the tri‐state enable function if D=1, E=0,
A=0, and B=0

(c) [1 pt] the maximum number of literals that each P‐term can have

(d) [1 pt]the settings for A, B, C needed to realize a positive polarity equation with an active low
output

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 ECE 270 Introduction to Digital System Design Spring 2019

4. [6 pts] Demonstrate that you can implement any arbitrary 3‐variable Boolean function using just a
3:8 decoder with active low outputs and a single 4‐input NAND gate (plus some resistors and an LED).

HINT: The LED may be connected in either a sourcing or a sinking configuration.

(a) [3 pts] Complete the schematic to implement the function F(X,Y,Z) = X·Z + X·Y·Z


(b) [3 pts] Complete the schematic to implement the function F(X,Y,Z) = X·Y·Z+ Y·Z+ X·Z


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ECE 270 Introduction to Digital System Design Spring 2019

5. [4 pts] Demonstrate you can implement any arbitrary 3‐variable Boolean function using only an 8:1
multiplexer by determining the data input settings (D0‐D7) required to implement the function
F(X,Y,Z) = X·Z + X(YZ)

Derivation:

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ECE 270 Introduction to Digital System Design Spring 2019

6. [14 pts] Given the ispLever Reduced Equation and Chip Reports on the page which follows,
determine the following (note – derivatory work must be shown for full credit):

(a) [1 pt] which set of equations (circle one: positive polarity ‐or‐ reverse polarity) the fitter chose
to burn into the PLD

(b) [1 pt] the pin numbers the fitter assigned to the X and Y outputs

(c) [1 pt] the number of P‐terms needed to realize the X (positive polarity) equation

(d) [1 pt] the number of P‐terms needed to realize the !X (reverse polarity) equation

(e) [1 pt] the number of P‐terms needed to realize the Y (positive polarity) equation

(f) [1 pt] the number of P‐terms needed to realize the !Y (reverse polarity) equation

(g) [2 pts] Verilog Dataflow equation for X based on XOR/XNOR operators

(h) [2 pts] Verilog Dataflow equation for Y based on XOR/XNOR operators

(i) [2 pts] the ON set for the function realized by the equation for X

(j) [2 pts] the ON set for the function realized by the equation for Y

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ECE 270 Introduction to Digital System Design Spring 2019

NOTE: Operator Representation: & AND, # OR, ! NOT, $ XOR

REDUCED EQUATION REPORT:

P-Terms Fan-in Fan-out Type Name (attributes)

--------- ------ ------- ---- -----------------
4/4 4 1 Pin X
4/4 4 1 Pin Y
=========
8/8 Best P-Term Total: 8
Total Pins: 6
Total Nodes: 0
Average P-Term/Output: 4

Positive-Polarity Equations:

X = !A & !B # A & B # C & !D # !C & D;

Y = A & !B & !C & !D # !A & B & !C & !D # A & !B & C & D # !A & B & C & D;

Reverse-Polarity Equations:

!X = A & !B & !C & !D # !A & B & !C & !D # A & !B & C & D # !A & B & C & D;

!Y = (!A & !B # A & B # C & !D # !C & D;

CHIP REPORT:

X = A & B # !A & !B # !C & D # C & !D;

Y = !A & B & C & D # A & !B & C & D # !A & B & !C & !D # A & !B & !C & !D;

P22V10G
+---------\ /---------+
| \ / |
| ----- |
A | 1 24 | Vcc
| |
B | 2 23 | Y
| |
C | 3 22 |
| |
D | 4 21 |
| |
| 5 20 |
| |
| 6 19 |
| |
| 7 18 |
| |
| 8 17 |
| |
| 9 16 |
| |
| 10 15 |
| |
| 11 14 | X
| |
GND | 12 13 |
| |
| |
`---------------------------'
Determithe following: Score: ______ / 42