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LHW8

Homework exercises Digital Systems design

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Vignesh Ramachandran
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11 views3 pages

LHW8

Homework exercises Digital Systems design

Uploaded by

Vignesh Ramachandran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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ECE 270 Introduction to Digital System Design Spring 2019

Homework 8
Due at the beginning of your scheduled lab period

Last Name (Printed): ______________________________________ Lab Div: _____ Date: ____________

E‐mail: __ __ __ __ __ __ __ __ @purdue.edu Signature: __________________________________________

Printed copies of these pages along with your original (hand-annotated, not photocopied) written solution in the
space provided (unless otherwise indicated) are required in order to receive credit. NOTE: The purpose of
homework is to provide an opportunity for practicing the kinds of problems you will be asked to solve on quizzes
and exams – copying the work of someone else does not accomplish this.

1. [4 pts] Given the following state transition diagram, complete the timing chart below.

1d

00 10
0d AB
dd
XY
d1
10

11
d0
01 11

01
00

1
ECE 270 Introduction to Digital System Design Spring 2019

2. [6 pts] Given the following state transition diagram, determine the next state equations it
represents in minimum sum-of-products form.

0d

00 01
1d AB
dd
XY
10

11
d1
10 11

01
00
d0

X Y A B X* Y* X* and Y* are “shorthand” for the next state of X and Y


0 0 0 0
0 0 0 1
X X X X
0 0 1 0
0 0 1 1 B B
0 1 0 0 A A
0 1 0 1
B B
0 1 1 0
0 1 1 1 A A
1 0 0 0 B B
1 0 0 1
Y Y Y Y Y Y
1 0 1 0
1 0 1 1
1 1 0 0
X* = ________________________________________
1 1 0 1
1 1 1 0 Y* = ________________________________________
1 1 1 1

2
ECE 270 Introduction to Digital System Design Spring 2019

3. [4 pts] Write a Verilog code module that implements the following circuit:

module bounceless_switch(NC,NO,BQ);

input wire NC,NO;


output wire BQ;

endmodule

4. [6 pts] Write a Verilog code module that implements the following circuit:

module master_latch(SM,RM,CM,QM,QM_N);

input wire SM,RM,CM;


output wire QM,QM_N;

endmodule

Score: ______ / 20 3

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