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A - B - C - D .: Answer

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41 views7 pages

A - B - C - D .: Answer

Uploaded by

nithya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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The difference between a PLA and a PAL is:

A The PLA has a programmable OR plane and a programmable AND plane, while the PAL only has
. a programmable AND plane.
B The PAL has a programmable OR plane and a programmable AND plane, while the PLA only has
. a programmable AND plane.
C
The PAL has more possible product terms than the PLA.
.
D
PALs and PLAs are the same thing.
.
Answer: Option A

2. ALM is the acronym for ________.


A.Array Logic Matrix
B.Arithmetic Logic Module
C.Asynchronous Local Modulator
D.Adaptive Logic Module
Answer: Option D

3. The GAL16V8 has:


A.16 dedicated inputs.
B.8 special function pins.
C.8 pins that are used as inputs or outputs.
D.All of the above
Answer: Option C

4. PALs tend to execute ________ logic.


A.SAP
B.SOP
C.PLA
D.SPD
Answer: Option B

5. How many pins are in an EDF10K70 package?


A.70
B.140
C.240
D.532
Answer: Option C
GAL is essentially a ________.
A
non-reprogrammable PAL
.
B
PAL that is programmed only by the manufacturer
.
C
very large PAL
.
D
reprogrammable PAL
.
Answer: Option D

7. What is an OTP device?


A.Optical transporting port
B.Octal transmitting pixel
C.Operational topical portable
D.One-time programmable
Answer: Option D

8. How many product terms can a MAX+Plus II compiler borrow from adjacent macrocells in the
same LAB?
A.0
B.5
C.10
D.20
Answer: Option B

9. Each programmable array logic (PAL) gate product is applied to an OR gate and, if
combinational logic is desired, the product is ORed and then:
A.the polarity fuse is restored
B.sent to an inverter for output
C.sent immediately to an output pin
D.passed to the AND function for output
Answer: Option B

10. ________ are used at the inputs of PAL/GAL devices in order to prevent input loading from a
large number of AND gates.
A.Simplified AND gates
B.Fuses
C.Buffers
D.Latches
Answer: Option C

12. What is another name for digital circuitry called sequential logic?
A.logic macrocell
B.logic array
C.flip-flop memory circuitry
D.inverter
Answer: Option C

13. When did the first PLD appear?


A.More than 10 years ago
B.More than 20 years ago
C.More than 30 years ago
D.More than 40 years ago
Answer: Option C

14. SPLDs, CPLDs, and FPGAs are all which type of device?
A.PAL
B.PLD
C.EPROM
D.SRAM
Answer: Option B

15. Cascade chains are closely associated with ________.


A.CLBs
B.SOP functions
C.logic expansion
D.all of the above
Answer: Option D
FPLA is:
A
a nonmemory programmable device.
.
B
a programmable AND array.
.
C
a programmable OR array.
.
D
All of the above
.
Answer: Option D

17. A(n) ________ is a section of embedded logic that is commonly found in FPGAs.
A.LUT
B.core
C.DSP
D.PI
Answer: Option B

18. In a FLEX10K, what two outputs will the LE produce?


A.The LAB and the fast track
B.ON and OFF
C.Hi-Z and ON
D.Hi-Z and OFF
Answer: Option A

25. Why have PLDs taken over so much of the market?


A.One PLD does the work of many ICs.
B.The PLDs are cheaper.
C.Less power is required.
D.All of the above
Answer: Option D
CLB is the acronym for ________.
A
Configurable Logic Block
.
B
Configurable Logic Buffer
.
C
Critical Logic Buffer
.
D
Constant Logic Buffer
.
Answer: Option A

27. What can the GAL22V10 do that the GAL16V8 cannot?


A.It has an extra-large array.
B.It is in-system programmable.
C.It has twice the special function pins.
D.All of the above
Answer: Option B

28. The output of this circuit is always ________.


A.1
B.0
C.A
D.A
Answer: Option D

29. A circuit that implements a combinational logic function by storing a list of output values that
correspond to all possible input combinations is a(n) ________.
A.output logic macrocell
B.look-up table
C.parallel logic expander
D.logic element
Answer: Option B

30. By adding an OR gate to a simple programmable logic device (SPLD) the foundation for a(n)
________ is made possible.
A.PAL
B.PLA
C.CPLD
D.EEPROM
Answer: Option A
What does the Altera FLEX10K PLD use in place of AND and OR arrays?
A.Nothing, it uses AND and OR arrays.
B.Look-up tables
C.SRAM-based memory
D.HPLD architecture
Answer: Option B

32. PIA is an acronym for ________.


A.Programmable Interface Array
B.Post Integrated Array
C.Programmable Input Array
D.Programmable Interconnect Array
Answer: Option D

33. Which one of the following is an embedded function of the Stratix II FPGA?
A.AND-OR logic
B.Programmable SOP
C.Digital signal processing
D.None of the above
Answer: Option C

34. In an OLMC, where does the FMUX signal go?


A.OMUX
B.D flip-flop
C.Matrix
D.PAL
Answer: Option C
35. Which of the following testing procedures has one or more external moving parts?
A.Bed-of-nails
B.Flying probe
C.EXTEST
D.Boundary scan
Answer: Option B
Field-programmable gate arrays (FGPAs) use ________ memory technology, which is
________.
A.DRAM, nonvolatile
B.SRAM, nonvolatile
C.SRAM, volatile
D.RAM, volatile
Answer: Option C

37. A PAL16L8 has:


A.10 inputs and 8 outputs.
B.8 inputs and 8 outputs.
C.16 inputs and 16 outputs.
D.16 inputs and 8 outputs.
Answer: Option A

38. Now many times can a GAL be erased and reprogrammed?


A.0
B.At least 100
C.At least 1000
D.Over 10,000
Answer: Option B

39. MPGA stands for:


A.mass produced gated array.
B.Morgan-Phillips gated array.
C.memory programmed ROM.
D.mask programmed ROM.
Answer: Option D

40. Which of the following increases the number of product terms by borrowing unused product from
other macrocells?
A.Shared expander
B.Parallel expander
C.Series expander
D.Slice expander
Answer: Option B
Which is a mode of operation of the GAL16V8?
A.Simple mode
B.Complex mode
C.Registered mode
D.All of the above
Answer: Option D

43. The macrocells in a PAL/GAL are located ________.


A.after the programmable AND arrays
B.ahead of the programmable AND arrays
C.at the input terminals
D.at the output terminals
Answer: Option A

44. The content of a simple programmable logic device (PLD) consists of:
A.fuse-link arrays
B.thousands of basic logic gates
C.advanced sequential logic functions
D.thousands of basic logic gates and advanced sequential logic functions
Answer: Option D

45. Which is a major digital system category?


A.Standard logic devices
B.ASICs
C.Microprocessor/DSP devices
D.All of the above
Answer: Option D

What is the input/output pin configuration of the GAL22V10?


A
10 output pins and 12 input pins
.
B
2 special-purpose pins
.
C
8 pins that are either inputs or outputs
.
D
All of the above
.
Answer: Option A

47. The output of this circuit is always ________.

A.1
B.0
C.A
D.A
Answer: Option C

48. What does a dot mean when placed on a PLD circuit diagram?
A.A point that is programmable
B.A point that cannot change
C.An intersection of logic blocks
D.An input or output point
Answer: Option B

49. FPGA is the acronym for ________.


A.Flexible Programming [of] Generic Assemblies
B.Field Programmable Generic Array
C.Field Programmable Gate Array
D.Field Programmer's Gate Assembly
Answer: Option C

50. How many combinations are handled in an LUT?


A.4
B.8
C.16
D.32
Answer: Option C

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