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Synthesis Doc ???

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27 views17 pages

Synthesis Doc ???

Uploaded by

Akash
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SYNTHESIS

BY
sindhu valleturi
What is a synthesis?
• Synthesis is a process of transferring higher level of abstraction (RTL)
to gate level netlist(.v).

Synthesis =Translation + Logic optimization + Mapping.

HDL > Generic Boolean Logic > Optimize > Mapping > Netlist
EXAMPLE FOR SYNTHESIS

Example for synthesis


Difference between rtl and
netlist
Tools we use to do synthesis
• Depending up on the tools the steps of synthesis
changes.There are two tools to implement synthesis.

• GENUS BY CADENCE .
• DESIGN COMPILER BY SYNOPSYS.
TYPES OF SYNTHESIS

• LOGIC AWARE SYN THESIS


• PHYSICAL AWARE SYNTHESIS
• POWER AWARE SYNTHESIS
• LOW POWER SYNTHESIS
read lib and read rtl
• Cells , delay , PVT , power information is present in the library file

• The functional description of a product is written in the Verilog or


VHDL languages.
• These are the inputs given to the tool.
ELABORATE
• Elaboration is a process of converting all the sub modules in to a single module
called TOP
• It also converts RTL in to generic netlist.
• All the codes and arithmetic operators will be converted in to GTECH cells and
DW (Design ware) components.
• Analyses the design hierarchy
• ISSUES
• Elaboration issues are linking issues.These issues are occurred when module
definitions are missing and mismatch of lib file and RTL Iib called Unresolved
references.
check_design
• In order to validate the HDL file we do check _design after elaboration. In this
step we check whether the design consistent or not. It checks the quality of
generic netlist and identifies
• Floating input pins
• Multi driven nets
• Black box
• Tri state buffers
• Combinational loops
• Empty module
• Unloaded output
read SDC
• Clock definitions
• I/O delays
• Timing exceptions
• Design rule constraints
Check_timing
• Check_timing is a command used for SDC checks.
• If any unconstrained path exist in the design then PNR tool will not
optimize that path.So these checks are used to report un constrained
paths.
• Checks weather the clock is reaching to all the clock pin of the flip
flop
• Checks if multiple clocks are driving same registers.
• Check unconstrained end points.
• Ports missing slew constraints.
Syn_gen {RTL Optimization}
• In syn_gen stage generic cells will form convert RTL to netlist and it is
technology independent.
• In this stage the optimizations are

Auto ungrouping
Boundary optimization
Resource sharing
Sequential merge
Syn_map {logic level optimization}
• Technology independent generic cells will be mapped to technology
specific lib cells.
• This process adds intermediate variables and logic structure to a
design which can result in reduced design area.
Structuring
Flattening
redundancy
Syn_opt {Gate level optimization}
• Syn_opt will be performed to improve timing , area and fixing .then
tool will do splitting ,buffering and sizing and timing optimizations
• Delay optimization
• Area optimization
• Timing optimization
Timing optimization
• If timing is met in syn_map stage then there is no need to go for next
syn_opt stage. we can share the netlist to do LEC.
• Some timing optimizations are
• Incremental optimization
• Path grouping
• Retiming
• Pipe lining
output
• it is logic aware synthesis so we get netlist (.v) and
updated sdc file (.sdc)
• If it is low power we will get CPF and UPF as output.
THE END

SINDHU VALLETURI
signing off ………

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