SVKM’s NMIMS

Mukesh Patel School of Technology Management and

Engineering, Vile Parle, Mumbai- 400056

Department of Electronics & Telecommunication

Lab Manual

Academic Year-2023-24

Programme: B Tech EXTC

B Tech/MBA Tech Information Technology
B Tech/MBA Tech Computer
B Tech CSE -Cyber Security

Semester – III

Course: - Digital Logic Design

Code: 702EX0C014
 SVKM’S NMIMS
Mukesh Patel School of Technology Management & Engineering

Department of Electronics &Telecommunication Engineering

Digital Electronics Lab

Course: Digital Design

Course Objectives:

This course introduces the fundamental concepts and techniques underlying the construction
of digital systems. It further provides insight into designing digital logic circuits using basic
building blocks and necessary techniques required in computer hardware design.

Course Outcomes:

After the successful completion of this course, the student will be able to

1. Explain the concept of digital system and logic simplification

2. Develop combinational circuits for various applications
3. Design sequential circuits for various application
4. Implement basic digital logic circuits using EDA tools with the help of VHDL
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

Programme: - B Tech EXTC, B Tech/MBA Tech Information Technology

B Tech/MBA Tech Computer, B Tech CSE -Cyber Security SEMESTER: - III

SUB: DIGITAL LOGIC DESIGN

LIST OF EXPERIMENTS

Sr. Page
Name of the Experiments
No. No
a. To verify the behavior of all basic logic gates and universal gates using
truth table and familiarization with digital integrated circuits.
1 2
b. Realization of logic expression using basic logic gates and universal
gates.
To implement and verify NAND and NOR gate as Universal Gates.
2 10
a. Implement NOT, AND, OR and X-OR using NAND gate
b. Implement NOT, AND, OR and X-OR using NOR gate
To implement and verify following DeMorgan’s Theorems using Bread
Board and components-

3 15
1.

2.

a. Implement a binary to gray code converter, for a given binary number

4 19
b. Implement a gray to binary code converter, for a given gray code
To design and analyze adder and subtractor circuits-
a. Implement a full adder using minimum number of basic gates.
5 23
b. Implement a full subtractor using minimum number of gates

a. Study of 74XX… MSI digital multiplexers.

6 b. Realize a given function using an appropriate MUX. 27

a. Implementation and verification of the following flip flops using logic

gates and ICs:
7 31
SR FF/ D FF/T FF
b. Develop D FF using SR FF (Conversion of FF)
Design and implement an asynchronous binary counter using T FF.
8 34
 Write a VHDL Code to implement the following gates using Vivado-
a. AND Gate
b. OR Gate
9 37
c. NAND Gate
d. X-OR Gate

Write a VHDL Code to implement Half and Full Adder using Vivado.
10 40

LAB ASSISTANT SUBJECT FACULTY HEAD OF DEPARTMENT

Ms. Neeta Patil Dr. Sonal Parmar Dr. Avinash More

Mapping of Experiments to Course Outcomes

Experiment. CO1 CO2 CO3 CO4 CO5 CO6

No.
1 √
2 √
3 √
4 √
5 √
6 √
7 √
8 √
9 √
10 √

1
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 1

STUDY OF LOGIC GATES

Aim: - Implementation of logic gates with the help of integrated circuits

Apparatus: - Power Supply, Multi-meter

Components:- Wires, Breadboard, , LED, resistor, Gates IC’S: - IC 7400-NAND,

IC7402-NOR, IC 7404-NOT, 7408-AND, 7486- XOR, 7432-OR Gate

Theory: - A logic gate is an idealized or physical device implementing

a Boolean function, that is, it performs a logical operation on one or more
logical inputs, and produces a single logical output.
AND Gate: -
The AND gate is a basic digital logic gate that implements logical
conjunction. A HIGH output results only if both the inputs to the AND
gate are HIGH. If neither or only one input to the AND gate is HIGH, a
LOW output results.
Symbol: - Truth Table:-

Input Input Output

A B Y
0 0 0
0 1 0
1 0 0
1 1 1

2
OR Gate: -
The OR gate is a digital logic gate that implements logical disjunction.
A HIGH output results if one or both the inputs to the gate are HIGH. If
neither input is HIGH, a LOW output results.
Symbol: - Truth Table: -
Input Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1

NOT Gate: -
In digital logic, an inverter or NOT gate is a logic gate which
implements logical negation. A HIGH output results if input to the gate is
LOW. If input is HIGH output is LOW.
Symbol: - Truth Table: -

Input Output
A Y
0 1
1 0

NAND Gate: -
In digital electronics, a NAND gate (Negated AND or NOT AND) is
a logic gate which produces an output that is false only if all its inputs are
true. A LOW output results only if both the inputs to the gate are HIGH; if
one or both inputs are LOW, a HIGH output results.
Symbol: - Truth Table: -

Input Input Output

A B Y
0 0 1
0 1 1
1 0 1
1 1 0

3
NOR Gate: -
The NOR gate is a digital logic gate that implements the negation of
the OR operator. A HIGH output results if both the inputs to the gate are
LOW; if one or both input is HIGH, a LOW output results.

Symbol: - Truth Table: -

Input Input Output

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

XOR Gate: -
The XOR gate (sometimes EOR gate or EXOR gate) is a digital logic
gate that implements an exclusive or; that is, a HIGH output results if one,
and only one, of the inputs to the gate is HIGH. If both inputs are LOW
and both are HIGH, a LOW output results.

Symbol: - Truth Table: -

Input Input Output

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

4
Circuit
diagram: - AND GATE (IC 7408): -
Symbol: - Pin Configuration: -

Truth Table: -

Input A Input B Output Y

0 0 0
0 1 0
1 0 0
1 1 1

OR GATE (IC 7432): -

Symbol: - Pin Configuration: -

Truth Table: -
Input A Input B Output Y
0 0 0
0 1 1
1 0 1
1 1 1

5
NOT GATE (IC 7404): -
Symbol: - Pin Configuration: -

Truth Table: -

Input A Output Y
0 1
0 0

NAND GATE (IC 7400): -

Symbol: - Pin Configuration: -

Truth Table: -

Input A Input B Output Y

0 0 1
0 1 1
1 0 1
1 1 0

6
NOR GATE (IC 7402): -
Symbol: - Pin Configuration: -

Truth Table: -

Input A Input B Output Y

0 0 1
0 1 0
1 0 0
1 1 0

XOR GATE (IC 7486): -

Symbol: - Pin Configuration: -

Truth Table: -
Input A Input B Output Y
0 0 0
0 1 1
1 0 1
1 1 0

7
Procedure: - 1. Draw the following Pin Diagram, Truth Table, Symbol of IC’S on the
blank sheet & attach with the main sheet
2. Place the IC- 74XX series in the socket of the breadboard in proper
position
3. Connect the circuit as shown in the figure
4. Switch on the Power Supply. (Set power supply to 5v Dc)
5. Verify the Truth Table of this IC by giving all the combinations of the
input and recording the corresponding output.

Result: - Input Input LED Input Input LED

A(v) B(v) (v) A(v) B(v) (v)
0 0 0 0 0 4.98
0 5 0 0 5 4.98
5 0 0 5 0 4.98
5 5 4.97 5 5 0

AND GATE NAND GATE

Input Input LED Input Input LED

A(v) B(v) (v) A(v) B(v) (v)
0 0 4.98 0 0 0
0 5 0 0 5 4.98
5 0 0 5 0 4.98
5 5 0 5 5 0

NOR GATE X-OR GATE

Input Input LED

A(v) B(v) (v) Input LED
0 0 0 A(v) (v)
0 5 4.98 0 4.96
5 0 4.98 5 0
5 5 4.98 NOT GATE
OR GATE

8
Conclusion: - All the logic gates were successfully implemented and their working
verified.

9
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 2

STUDY OF UNIVERSAL GATES

Aim: - Implementation of NAND gate and NOR gate as Universal gates.

Apparatus: - Power Supply, Multi-meter

Components:- Wires, Breadboard, LED, resistor, Gates IC’S: - 7400-NAND Gate,

IC7402-NOR Gate.

Theory: - A universal gate is a gate which can implement any Boolean function
without need to use any other gate type. The NAND and NOR gates are
universal gates.
In practice, this is advantageous since NAND and NOR gates are
economical and easier to fabricate and are the basic gates used in all IC
digital logic families.
An AND gate is typically implemented as a NAND gate followed by an
inverter. An OR gate is typically implemented as a NOR gate followed by
an inverter.
NAND Gate as Universal gate: -
Implement NOT gate using NAND gate: -
All NAND input pins connect to the input signal A gives an output A’.

10
 Implement AND gate using NAND gate: -
An AND gate can be replaced by NAND gates as shown in the figure
The AND is replaced by a NAND gate with its output complemented by a
NAND gate inverter.

Implement OR gate using NAND gate: -

An OR gate can be replaced by NAND gates as shown in the figure.
The OR gate is replaced by a NAND gate with all its inputs complemented
by NAND gate inverters.

NOR Gate as Universal gate: -

Implement NOT gate using NOR gate: -
All NOR input pins connect to the input signal A gives an output A’.

Implement AND gate using NOR gate: -

An AND gate can be replaced by NOR gates as shown in the figure.
The AND gate is replaced by a NOR gate with all its inputs complemented
by NOR gate inverters.

11
 Implement OR gate using NOR gate: -
The OR is replaced by a NOR gate with its output complemented by a
NOR gate inverter.

Circuit
Diagram:- NAND Gate as Universal gate: -
Implement NOT gate using NAND gate: -

Implement AND gate using NAND gate: -

Implement OR gate using NAND gate: -

NOR Gate as Universal gate: -

Implement NOT gate using NOR gate: -

Implement AND gate using NOR gate: -

12
 Implement OR gate using NOR gate: -

Procedure: - 1. Place the IC- 74XX series in the socket of the breadboard in proper
position
2. Connect the circuit as shown in the figure
3. Switch on the Power Supply. (Set power supply to 5v Dc)
4. Verify the Truth Table for all circuits by giving all the combinations of
the input and recording the corresponding output.

13
Result: - Input Input LED Input Input
LED
A(v) B(v) (v) A B
0 0 0 0 0 0
0 5 0 0 5 4.89
5 0 0 5 0 4.89
5 5 4.95 5 5 4.89

AND GATE OR GATE

Input LED
A(v) (v)
0 4.92
5 0

NOT GATE

Conclusion: - Basic logic gates AND, OR and NOT were implemented using the
universal logic gates NAND and NOR and their output was verified.

14
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 3

STUDY OF DE-MORGAN’S THEOREM

Aim: - Implement and verify De-Morgan’s theorem using logic gates.

Apparatus: - Power Supply, Multi-meter

Components:- Wires, Breadboard, LED, resistor, Gates IC’S: - 7408-AND Gate, IC7404-
NOT Gate, IC7432- OR Gate.

Theory: - De-Morgan’s First Theorem: -

It states that “Complement of the product is equal to sum of the
complement.”
A.B=A + B
L.H.S of this theorem consists of AND gate followed by NOT gate (or
NAND gate), while R.H.S is OR gate with its input Inverted.

De-Morgan’s Second Theorem: -

It states that “Complement of the sum is equal to product of the

15
 complement.”
A+B= A . B
L.H.S of this theorem consists of OR gate followed by NOT gate (or
NOR gate), while R.H.S is AND gate with its input Inverted.

Circuit De-Morgan’s First Law: -

Diagram:-

De-Morgan’s Second Law: -

16
Procedure: - 1. Place the IC- 74XX series in the socket of the breadboard in proper
position
2. Connect the circuit as shown in the figure
3. Switch on the Power Supply. (Set power supply to 5v Dc)
4. Verify the Truth Table for all circuits by giving all the combinations of
the input and recording the corresponding output.

17
Result: - De-Morgan’s First Theorem: -

LED LED
Input Input ̅̅̅̅̅̅
𝐴 .𝐵 𝐴̅ + 𝐵̅
A(v) B(v)
(v) (v)
0 0 4.98 4.98
0 5 4.98 4.98
5 0 4.98 4.98
5 5 0 0
De-Morgan’s Second Law: -

Input Input LED LED

A B ̅̅̅̅̅̅̅̅
𝐴 + 𝐵 𝐴̅. 𝐵̅
(v) (v) (v) (v)
0 0 4.97 4.97
0 5 0 0
5 0 0 0
5 5 0 0

Conclusion: - De-Morgan’s laws were implemented using logic gates and verified the
two statement
“Complement of the product is equal to sum of the complement.”
“Complement of the sum is equal to product of the complement.”

18
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 4

STUDY OF GRAY CODE

Aim: - To Design & implement binary to gray and gray to binary code
converter

Apparatus: - Power Supply, Multi-meter

Components:- Wires, Breadboard, LED, resistor, Gates IC’S: - 7486-EX-OR Gate.

Theory: - The reflected binary code, also known as Gray code, is a binary numeral
system where two successive values differ in only one bit. It is a non-
weighted code. Gray codes are widely used to facilitate error correction in
digital communications such as digital terrestrial television and some cable
TV systems.
Conversion from Binary to Gray code: -
1. The left most significant bit of a given binary code number is same as the
most left significant bit of the gray code number.
2. To obtain the successive gray bits to produce the equivalent gray number
for the given binary code number, add the first bit of binary number to the
second one and write down the result next to the first bit, add the second
binary number bit to third one and write down the result and so on next to
the second bit and repeat the same operation until the last bit.
Conversion from Gray to Binary code: -
1. The left most significant bit of a given grey code number is same as the
most left significant bit of the binary number.
2. To obtain the successive binary bits to produce the equivalent binary

19
 number for the given grey code number, add the first bit of grey code to the
second one and write down the result next to the first bit, add the second
grey code bit to third one and write down the result and so on next to the
second bit and repeat the same operation until the last bit

Circuit Conversion from Binary to Gray code: -

Diagram:-

Conversion from Gray to Binary code: -

Procedure: - Binary to Gray code Conversion: -

1. Write truth table for Binary to gray code conversion.

20
2. Prepare K-maps for all the four bits.
3. Obtain the logical expression from K-maps.
4. List out the number and type of the gates required.
5. Design a combinational circuit using the expressions.
6. Implement the combinational circuit.
7. Verify the truth-table with all combinations of inputs.
Gray to Binary Code Conversion
1. Write truth –table for gray to binary code conversion.
2. Prepare K-maps for all the four bits.
3. Obtain the logical expression from K-maps.
4. List out the number and type of the gates required.
5. Design a combinational circuit using the expressions.
6. Implement the combinational circuit.
7. Verify the truth table with all the combinations of input.

Gray Code Table-

21
Result: - BINARY TO GRAY CODE
BINARY CODE GRAY CODE
(v) (v)
0 0 0 0 0 0 0 0
0 0 0 5 0 0 0 5
0 0 5 0 0 0 5 5
0 0 5 5 0 0 5 0
0 5 0 0 0 5 5 0
0 5 0 5 0 5 5 5
0 5 5 0 0 5 0 5
0 5 5 5 0 5 0 0
5 0 0 0 5 5 0 0
5 0 0 5 5 5 0 5
5 0 5 0 5 5 5 5
5 0 5 5 5 5 5 0
5 5 0 0 5 0 5 0
5 5 0 5 5 0 5 5
5 5 5 0 5 0 0 5
5 5 5 5 5 0 0 0

GRAY TO BINARY CODE

GRAY CODE BINARY CODE
0 0 0 0 0 0 0 0
0 0 0 5 0 0 0 5
0 0 5 5 0 0 5 0
0 0 5 0 0 0 5 5
0 5 5 0 0 5 0 0
0 5 5 5 0 5 0 5
0 5 0 5 0 5 5 0
0 5 0 0 0 5 5 5
5 5 0 0 5 0 0 0
5 5 0 5 5 0 0 5
5 5 5 5 5 0 5 0
5 5 5 0 5 0 5 5
5 0 5 0 5 5 0 0
5 0 5 5 5 5 0 5
5 0 0 5 5 5 5 0
5 0 0 0 5 5 5 5

Conclusion: - A digital logic circuit which converts gray code to binary and binary code to
gray code was implemented and the outputs verified.

22
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 5

STUDY OF HALF AND FULL ADDER

Aim: - To Design & implement Half Adder and Full Adder using logic gates.

Apparatus: - Power Supply, Multi-meter

Components:- Wires, Breadboard, LED, resistor, Gates IC’S: - 7486-EX-OR Gate, 7408-
AND Gate.
Theory: - In electronics, an adder or summer is a digital circuit that
performs addition of numbers. In many computers and other kinds of
processors, adders are used not only in the arithmetic logic unit, but also in
other parts of the processor, where they are used to calculate addresses,
table indices, and similar operations.
Half Adder: -
The half adder adds two single binary digits A and B. It has two outputs,
sum (S) and carry (C). The carry signal represents an overflow into the next
digit of a multi-digit addition. The value of the sum addition of bits. The
simplest half-adder design, incorporates an XOR gate for S and an AND
gate for C. With the addition of an OR gate to combine their carry outputs,
two half adders can be combined to make a full adder.

A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

23
 Full Adder: -
A full adder adds binary numbers and accounts for values carried in as
well as out. A one-bit full adder adds three one-bit numbers, often written
as A, B, and Cin; A and B are the operands, and Cin is a bit carried in from
the next less significant stage. The full-adder is usually a component in a
cascade of adders, which add 8, 16, 32, etc. bit wide binary numbers. The
circuit produces a two-bit output, output carry and sum typically
represented by the signals Cout and S
A B Cin Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Circuit Half Adder: -

Diagram:-

Full Adder: -

24
Procedure: - Half Adder:
1. Write the Truth Table for half Adder.
2. Prepare K maps.
3. Obtain the logical expression from K-maps.
4. List out the number and type of the gates required.
5. Design a combinational circuit using the expressions.
6. Implement the combinational circuit using bread-board, ICs.
7. Connect LED for output indication (sum, carry).
8. Verify the Truth Table for all the combinations of inputs.

Full Adder:
1. Write the Truth Table for Full Adder.
2. Prepare K maps.
3. Obtain the logical expression from K-maps.
4. List out the number and type of the gates required.
5. Design a combinational circuit using the expressions.
6. Implement the combinational circuit using bread-board, ICs.
7. Connect LED for output indication (sum, carry).
8. Verify the Truth Table for all the combinations of inputs.

Result: - HALF ADDER: -

A B Sum Carry
(v) (v) (v) (v)
0 0 0 0
0 5 4.99 0
5 0 4.99 0
5 5 0 4.98

25
 FULL ADDER: -
A B Cin Sum Carry
(v) (v) (v) (v) (v)
0 0 0 0 0
0 0 5 4.98 0
0 5 0 4.98 0
0 5 5 0 4.97
5 0 0 4.98 0
5 0 5 0 4.97
5 5 0 0 4.98
5 5 5 4.98 4.98

Conclusion: - A half adder circuit was designed and implemented and verified.
A full adder circuit was designed and implemented and verified.

26
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 6

STUDY OF MULTIPLEXER

Aim: - To implement given Boolean expression using 8:1 multiplexer.

Apparatus: - Power Supply, Multi-meter

Components: Wires, Breadboard, LED, resistor, Gates IC’S: - 74151 – 8:1 Multiplexer
-

Theory: - In electronics, a multiplexer (or mux) is a device that selects one of

several analog or digital input signals and forwards the selected input into a
single line. A multiplexer of 2n inputs has n select lines, which are used to
select which input line to send to the output. Multiplexers are mainly used to
increase the amount of data that can be sent over the network within a
certain amount of time and bandwidth. A multiplexer is also called a data
selector.
IC 74151 8-bit Multiplexer: -
The TTL/MSI SN54/74LS151 is a high speed 8-input Digital
Multiplexer. It provides, in one package, the ability to select one bit of data
from up to eight sources. The LS151 can be used as a universal function
generator to generate any logic function of four variables. Both assertion and
negation outputs are provided.

27
Design: - Sr. No. A B C D Y
0 0 0 0 0 0
𝑫𝟎 = 𝑫
1 0 0 0 1 1
2 0 0 1 0 1 ̅
𝑫𝟏 = 𝑫
3 0 0 1 1 0
4 0 1 0 0 0
𝑫𝟐 = 𝟎
5 0 1 0 1 0
6 0 1 1 0 1 ̅
𝑫𝟑 = 𝑫
7 0 1 1 1 0
8 1 0 0 0 1
𝑫𝟒 = 𝟏
9 1 0 0 1 1
10 1 0 1 0 0
𝑫𝟓 = 𝑫
11 1 0 1 1 1
12 1 1 0 0 1
𝑫𝟔 = 𝟏
13 1 1 0 1 1
14 1 1 1 0 0
𝑫𝟕 = 𝟎
15 1 1 1 1 0

Circuit
Diagram:- Y = ∑ m (1, 2, 6, 8, 9, 10, 11, 12, 13)

28
Procedure: - 1. Place the IC 74151 in the socket of the breadboard in proper position
and switch
2. Connect the wires as shown in the figure
3. Switch On the power supply.
4. Connect the pin16 and 8 to Vcc and ground respectively.
5. Connect the circuit output lines according to SOP equation.
6. Verify the Truth table of this IC by giving all the combinations of the
input and recording the corresponding output.

29
Result: - Sr. No. A B C D Y
0 0 0 0 0 0
1 0 0 0 5 4.98
2 0 0 5 0 4.98
3 0 0 5 5 0
4 0 5 0 0 0
5 0 5 0 5 0
6 0 5 5 0 4.98
7 0 5 5 5 0
8 5 0 0 0 4.98
9 5 0 0 5 4.98
10 5 0 5 0 0
11 5 0 5 5 4.98
12 5 5 0 0 4.98
13 5 5 0 5 4.98
14 5 5 5 0 0
15 5 5 5 5 0

Conclusion: - A multiplexer is a circuit which selects one input from many inputs. A
Boolean expression was implemented using a 8:1 Multiplexer.

30
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 7

STUDY ALL GATES IN VHDL USING BEAHVIOURAL

MODELING.

Aim: - To design and implement OR /NOR / XOR GATE in VHDL using behavioral
modelling.

Appar
Computer, VHDL software, hardware board.
atus:

Theory: VHDL (VHSIC-HDL) (Very High Speed Integrated Circuit Hardware Description
- Language) is a hardware description language used in electronic design automation to
describe digital and mixed-signal systems such as field-programmable gate
arrays and integrated circuits. VHDL can also be used as a general purpose parallel
programming language. The key advantage of VHDL, when used for systems design, is
that it allows the behavior of the required system to be described (modeled) and verified
(simulated) before synthesis tools translate the design into real hardware. Another benefit
is that VHDL allows the description of a concurrent system. VHDL is a dataflow
language, unlike procedural computing languages such as BASIC, C, and assembly code,
which all run sequentially, one instruction at a time. A VHDL project is multipurpose.
Being created once, a calculation block can be used in many other projects. However,
many formational and functional block parameters can be tuned (capacity parameters,
memory size, element base, block composition and interconnection structure).
DESIGN CODE for OR gate:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

31
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity or_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end or_gate;

architecture Behavioral of or_gate is

begin
y <= a or b;

end Behavioral;

DESIGN CODE for NOR gate:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity nor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end nor_gate;

architecture Behavioral of nor_gate is

begin
y <= a nor b;

32
end Behavioral;

DESIGN CODE for XOR:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity exor_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);
end exor_gate;

architecture Behavioral of exor_gate is

begin
y <= a xor b;

end Behavioral;

TESTBENCH CODE for OR gate:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity or_gate_tb is
end;

architecture bench of or_gate_tb is

component or_gate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;

33
 y : out STD_LOGIC);
end component;

signal a: STD_LOGIC := '0';

signal b: STD_LOGIC := '0';
signal y: STD_LOGIC;

begin

uut: or_gate port map ( a => a,

b => b,
y => y );

stimulus1: process
begin

a <= not a;
wait for 10 ns;

end process;

stimulus2: process
begin

b <= not b;
wait for 20 ns;

end process;

end;

TESTBENCH CODE for NOR gate:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity nor_gate_tb is
end;

architecture bench of nor_gate_tb is

component nor_gate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;

34
 y : out STD_LOGIC);
end component;

signal a: STD_LOGIC :='0';

signal b: STD_LOGIC :='0';
signal y: STD_LOGIC;

begin

uut: nor_gate port map ( a => a,

b => b,
y => y );

stimulus1: process
begin

a <= not a;
wait for 10 ns;

end process;

stimulus2: process
begin

b <= not b;
wait for 20 ns;

end process;

end;

TESTBENCH CODE for XOR gate:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity exor_gate_tb is
end;

architecture bench of exor_gate_tb is

component exor_gate
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
y : out STD_LOGIC);

35
 end component;

signal a: STD_LOGIC := '0';

signal b: STD_LOGIC := '0';
signal y: STD_LOGIC;

begin

uut: exor_gate port map ( a => a,

b => b,
y => y );

stimulus1: process
begin
a <= not a;
wait for 10 ns ;

end process;

stimulus2: process
begin
b <= not b;
wait for 20 ns ;

end process;

end;

SCHEMETIC RTL SYNTHESIS:

36
TIME GRAPH:

37
38
CONCLUSION:
Hence using VHDL codes, we can make different gates and simulate its properties before
performing practically.

39
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 8

BINARY TO GRAY IN VHDL

Aim: - To design and implement binary to gray in VHDL using behavioral

modeling.
Apparatus: - Computer, VHDL software, hardware.

Theory: VHDL (VHSIC-HDL) (Very High Speed Integrated Circuit Hardware Description
Language) is a hardware description language used in electronic design automation to
describe digital and mixed-signal systems such as field-programmable gate
arrays and integrated circuits. VHDL can also be used as a general purpose parallel
programming language. The key advantage of VHDL, when used for systems design, is that
it allows the behavior of the required system to be described (modeled) and verified
(simulated) before synthesis tools translate the design into real hardware. Another benefit is
that VHDL allows the description of a concurrent system. VHDL is a dataflow language,
unlike procedural computing languages such as BASIC, C, and assembly code, which all run
sequentially, one instruction at a time. A VHDL project is multipurpose. Being created once,
a calculation block can be used in many other projects. However, many formational and
functional block parameters can be tuned (capacity parameters, memory size, element base,
block composition and interconnection structure).
logic code:

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09/03/2019 12:39:17 PM
-- Design Name:
-- Module Name: btg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:

40
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity btg is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
p : out STD_LOGIC;
q : out STD_LOGIC;
r : out STD_LOGIC);
end btg;

architecture Behavioral of btg is

begin
p<=a;
q<=a xor b;
r<=b xor c;

end Behavioral;

Testbench:

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

41
entity btg_tb is
end;

architecture bench of btg_tb is

component btg
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
p : out STD_LOGIC;
q : out STD_LOGIC;
r : out STD_LOGIC);
end component;

signal a: STD_LOGIC:='0';
signal b: STD_LOGIC:='0';
signal c: STD_LOGIC:='0';
signal p: STD_LOGIC;
signal q: STD_LOGIC;
signal r: STD_LOGIC;

begin

uut: btg port map ( a => a,

b => b,
c => c,
p => p,
q => q,
r => r );

stimulus: process
begin
a<=not a;
wait for 40 ns;
b<=not b;
wait for 20 ns;
c<=not c;
wait for 10 ns;
end process;

end;

42
schematic diagram:

TIME GRAPH:

43
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 9

HALF ADDER IN VHDL

Aim: - To design and implement HALF ADDER in VHDL using behavioral
modelling.

Apparatus
Computer, VHDL software, hardware.
:

Theory: - VHDL (VHSIC-HDL) (Very High Speed Integrated Circuit Hardware

Description Language) is a hardware description language used in electronic
design automation to describe digital and mixed-signal systems such as field-
programmable gate arrays and integrated circuits. VHDL can also be used as a
general purpose parallel programming language. The key advantage of VHDL,
when used for systems design, is that it allows the behavior of the required
system to be described (modeled) and verified (simulated) before synthesis
tools translate the design into real hardware. Another benefit is that VHDL
allows the description of a concurrent system. VHDL is a dataflow language,
unlike procedural computing languages such as BASIC, C, and assembly code,
which all run sequentially, one instruction at a time. A VHDL project is
multipurpose. Being created once, a calculation block can be used in many
other projects. However, many formational and functional block parameters can
be tuned (capacity parameters, memory size, element base, block composition
and interconnection structure).

LOGIC CODE:

library IEEE;

44
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx leaf cells in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity half_adder is

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

s : out STD_LOGIC;

c : out STD_LOGIC);

end half_adder;

architecture Behavioral of half_adder is

begin
s <= a xor b;
c <= a and b;

end Behavioral;
TEST BENCH CODE:

library IEEE;

use IEEE.Std_logic_1164.all;

use IEEE.Numeric_Std.all;

45
entity half_adder_tb is

end;

architecture bench of half_adder_tb is

component half_adder

Port ( a : in STD_LOGIC;

b : in STD_LOGIC;

s : out STD_LOGIC;

c : out STD_LOGIC);

end component;

signal a: STD_LOGIC :='0';

signal b: STD_LOGIC :='0';

signal s: STD_LOGIC;

signal c: STD_LOGIC;

begin
uut: half_adder port map ( a => a,

b => b,

s => s,

c => c );
stimulus1: process

begin

a <= not a;

wait for 10 ns;

end process;

46
 stimulus2: process

begin

b <= not b;

wait for 20 ns;

end process;
end;

SCHEMETIC RTL SYNTHESIS:

TIME GRAPH:

47
CONCLUSION:
Hence we get the graph for half adder using VHDL.now we can connect a
hardware and burn the code to it so that it works as a half adder.

48
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 10
STUDY OF COUNTERS

Aim: - To implement MOD-8 asynchronous counter using JK Flip flop.

Apparatus: - Power Supply, Multi-meter

Components:- Wires, Breadboard, LED, resistor, Gates IC’S: - 7476 – JK flip flop.

Theory: - In digital logic and computing, a counter is a device which stores (and
sometimes displays) the number of times a particular event or process has
occurred, often in relationship to a clock signal. In electronics, counters can
be implemented quite easily using register-type circuits such as the flip-flop.
Basically there are two types of counters.
Asynchronous counter (ripple counter).
Synchronous counter.
Asynchronous counter: - In the case of an Asynchronous Counter, all the
flip-flops are not clocked simultaneously. This counter is simple in
operation & requires a min. of hardware.
But its speed is low. Each FF is triggered by a previous FF o/p. Each FF
takes its own time to give o/p (due to propagation delay). So final settling
time is high. They have the problem of glitch.
Synchronous counter: - In synchronous counters all the FFs are clocked
simultaneously. It is complex in construction, but speed is more. In this case
since each FF is clocked simultaneously thus settling time is the delay time
of single FF. No problem of glitch.

49
 Asynchronous counter IC (7490): - It is a BCD counter. It consists of four
FFs internally connected to provide a mod-2 counter and a mod-5 counter.
The mod-2 and mod-5 counters can be used independently or in
combination. FFA operates as a mod2 counter whereas the combination of
FFB, FFC and FFD form a mod-5 counter. There are two reset inputs R1 &
R2 both of which are to be connected to logic 1 level for clearing all the
FFs. The two set inputs S1 & S2 when connected to logic1 level are used
for setting the counter to 1001.

Circuit IC 7476 Pin Configuration: -

Diagram:-

MOD-8 Asynchronous Counter: -

50
Procedure: - 1. Draw circuit diagram for MOD-8 Asynchronous counter using IC7476
2. Prepare Truth table for counter.
3. Implement counter Circuit using IC7476.
4. For output indicator connect LED’s at the outputs.
5. Verify truth table for all combinations of inputs

Result: - Input Pulse Count

QL QB QA
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

Conclusion: - A MOD-8 Asynchronous Counter was implemented with its outputs

verified.

51
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 11

Aim: Design and verify the 4- Bit Synchronous/ Asynchronous Counter using JK flip flop.

Apparatus: Virtual Lab

https://de-iitr.vlabs.ac.in/exp/4bit-synchronous-asynchronous-counter/

Theory:

To verify the truth table and timing diagram of 4-bit synchronous parallel counter and 4-bit
asynchronous parallel counter by using JK flip flop ICs and analyse the circuit of 4-bit
synchronous parallel counter and 4-bit asynchronous parallel counter with the help of LEDs
display.

Introduction

A counter is a device which stores (and sometimes displays) the number of times a particular
event or process has occurred, often in relationship to a clock signal. Counters are used in
digital electronics for counting purpose, they can count specific event happening in the
circuit. For example, in UP counter a counter increases count for every rising edge of clock.

Classification of Counters

Counters are broadly divided into two categories

1. Asynchronous counter
2. Synchronous counter

1) Asynchronous Counter

In asynchronous counter we don’t use universal clock, only first flip flop is driven by main
clock and the clock input of rest of the following counters is driven by output of previous flip
flops. We can understand it by following diagram-

52
 Figure-1: Asynchronous Counter Circuit and Timing Diagram
It is evident from timing diagram that Q0 is changing as soon as the rising edge of clock
pulse is encountered, Q1 is changing when rising edge of Q0 is encountered(because Q0 is
like clock pulse for second flip flop) and so on. In this way ripples are generated through
Q0,Q1,Q2,Q3 hence it is also called RIPPLE counter.

2) Synchronous Counter

Unlike the asynchronous counter, synchronous counter has one global clock which drives
each flip flop so output changes in parallel. The one advantage of synchronous counter over
asynchronous counter is, it can operate on higher frequency than asynchronous counter as it
does not have cumulative delay because of same clock is given to each flip flop.

53
 Figure-2: Synchronous Counter Circuit and Timing Diagram

From circuit diagram we see that Q0 bit gives response to each falling edge of clock while
Q1 is dependent on Q0, Q2 is dependent on Q1 and Q0, Q3 is dependent on Q2, Q1 and Q0.

Pre-test: (Select Correct Options)

In digital logic, a counter is a device which ____________

54
 a: Counts the number of outputs
b: Stores the number of times a particular event or process has occurred
c: Stores the number of times a clock pulse rises and falls
d: Counts the number of inputs

A counter circuit is usually constructed of ____________ .

a: A number of latches connected in cascade form
b: A number of NAND gates connected in cascade form
c: A number of flip-flops connected in cascade
d: A number of NOR gates connected in cascade form

Ripple counters are also called ____________ .

a: SSI counters
b: Synchronous counters
c: VLSI counters
d: Asynchronous counters

The parallel outputs of a counter circuit represent the _____________ .

a: Parallel data word
b: Clock frequency
c: Clock count
d: Counter modulus

What is the maximum possible range of bit-count specifically in n-bit binary counter
consisting of ‘n’ number of flip-flops?
a: 0 to 2^n
b: 0 to 2^n + 1
c: 0 to 2^n – 1
d: 0 to 2^n + 1/2

Procedure:

55
Synchronous Counter

Step-1) Press Switch to supply 5V to the circuit.

The switch in ON state is and the switch in OFF state is

Step-2) Press Counter button to start the counter.
Step-3) Different combination of LEDs lit up for different combination of inputs.

The LED in OFF state is and the LED in ON state is .

The data is simultaneously added to the Truth Table.
Step-4) Repeat Steps 2 to 3 for another set of data.
Step-5) Click on "Generate Waveform" Button to generate the Timing Diagram .
Step-6) Click "Print" to get the print out of the Truth Table and the Timing Diagram.

Asynchronous Counter

Step-1) Press Switch to supply 5V to the circuit.

The switch in ON state is and the switch in OFF state is

Step-2) Press Counter button to start the counter.
Step-3) Different combination of LEDs lit up for different combination of inputs.

The LED in OFF state is and the LED in ON state is .

The data is simultaneously added to the Truth Table.

Step-4) Repeat Steps 2 to 3 for another set of data.

Step-5) Click on "Generate Waveform" Button to generate the Timing Diagram .
Step-6) Click "Print" to get the print out of the Truth Table and the Timing Diagram.

Simulation:

Instructions

4-Bit Asynchronous Parallel Counter using J-K Flip-Flop

56
Instructions

4-Bit Synchronous Parallel Counter using J-K Flip-Flop

57
Post-test

One of the major drawbacks to the use of asynchronous

counters is that ____________
a: Low-frequency applications are limited because of internal propagation delays
b: High-frequency applications are limited because of internal propagation
delays
c: Asynchronous counters do not have major drawbacks and are suitable for use
in high- and low-frequency counting applications
d: Asynchronous counters do not have major drawbacks and are suitable for use
in high- and low-frequency counting applications

A counter is implemented using three (3) flip-flops, possibly it

will have ________ maximum output status.

58
 a: 3 b: 7 c: 8 d: 15
Which sequential circuits are applicable for counting pulses?
a: Counters b: Flip Flops c: Registers d: Latches
A decimal counter has ______ states.
a: 5 b: 10 c: 15 d: 20
Counter is a ____________ .
a: Combinational circuit b: Sequential circuit c: Both d: None

References:

1. William Gothmann H, Digital Electronics: An Introduction to Theory And Practice, Prentice

Hall, 2nd ed. 1982
2. M. Morris Mano, Michael D Ciletti, "Digital Design", Pearson, 4th ed. 2008
3. Thomas L. Floyd, R. P. Jain, "Digital Fundamentals", Pearson, 11th ed. 2017
4. S Salivahanan, S Arivazhagan, "Digital Circuits and Design", Vikas Publishing House Pvt
Ltd., 3rd ed. 2009
5. Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss, "Digital Systems", Pearson, 10th ed.
2009
6. Anil K. Maini, "Digital Electronics: Principles, Devices and Applications", Wiley-Blackwell,
2007
7. Synchronous Counter: https://www.electronics-tutorials.ws/counter/count_3.html
8. Asynchronous Counters: https://www.allaboutcircuits.com/textbook/digital/chpt-
11/asynchronous-counters/

59
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 12

Aim: Design and Verify the 4-Bit Serial In - Parallel Out Shift Registers.

To analyse the circuit and truth table of 4-bit SIPO (serial input parallel output) shift register
by using IC 7474 (D flip flop).

Reference Link: Virtual Lab

https://de-iitr.vlabs.ac.in/exp/4bit-sipo-shift-register/index.html

Theory:

In Serial In Parallel Out (SIPO) shift registers, the data is stored into the register serially
while it is retrieved from it in parallel-fashion. Figure 1 shows an n-bit synchronous SIPO
shift register sensitive to positive edge of the clock pulse. Here the data word which is to be
stored (Data in) is fed serially at the input of the first flip-flop (D1 of FF1). It is also seen that
the inputs of all other flip-flops (except the first flip-flop FF1) are driven by the outputs of the
preceding ones like the input of FF2 is driven by the output of FF1. In this kind of shift
register, the data stored within the register is obtained as a parallel-output data word (Data
out) at the individual output pins of the flip-flops (Q1 to Qn).

In general, the register contents are cleared by applying high on the clear pins of all the flip-
flops at the initial stage. After this, the first bit, B1 of the input data word is fed at the D1 pin

60
of FF1.This bit (B1) will enter into FF1, get stored and thereby appears at its output Q1 on
the appearance of first leading edge of the clock. Further at the second clock pulse, the bit B1
right-shifts and gets stored into FF2 while appearing at its output pin Q2 while a new bit, B2
enters into FF1. Similarly, at each clock pulse the data within the register moves towards
right by a single bit while a new bit of the input word enters into the register. Meanwhile one
can extract the bits stored within the register in parallel-fashion at the individual flip-flop
outputs.

Analyzing on the same grounds, one can note that the n-bit input data word is obtained as an
n-bit output data word from the shift register at the rising edge of the nth clock pulse. This
working of the shift-register can be summarized as in Table I and the corresponding
waveforms are given by figure 2.

In the right-shift SIPO shift-register, data bits shift from left to right for each clock pulse.
However, if the data bits are made to shift from right to left in the same design, one gets a
left-shift SIPO shift-register as shown by figure 3. Nevertheless the basic working principle
remains the same except the fact that now Bn down to B1 is stored in Qn down to Q1 i.e. Q1

61
= B1, Q2 = B2 … Qn = Bn at the nth clock pulse.

Pretest:

A register that can be used to provide data movements ________________

a: Parallel Register b: Simple Register c: Serial Register d: Shift Register
A n-bit register has a group of _________ flip-flops and some logic gates.
a: n b: p c: 10 d: 01
Shifting a register content to left by one position is equivalent to ____________
a: division by 2 b: addition by 2 c: multiplication by 2 d: subtraction by 2
To serially shift a nibble (4 bits) of data into a shift register, there must be __________
a: 1 clock pulse b: 8 clock pulses c: 4 clock pulses d: 1 clock pulse for each
1 in the data
What is meant by parallel load of a shift register?
a: Parallel shifting of data b: Each flip-flop is loaded with data one at a time c:
All flip-flops are preset with data d: None of the above

Procedure:

Step-1) Connect the supply(+5V) to the circuit.

Step-2) Keep the Reset and Preset as active-high signals .

Step-3) Apply the data at data input .

Step-4) Press clock pulse and observe this data at LED Q3.
Step-5) Then press "ADD" button to add data in the given truth table.
Step-6) Apply the next data at data input.

62
Step-7) Press clock pulse and observe that the data at LED Q3will shift to LED Q2 and the
new data applied will appear at Q3.
Step-8) Repeat steps 3 to 5 till all the 4 bits appear at the output of shift register.
Step-9) Press the "Print" button after completing your simulation to get your results.

Simulation:

Design and verification of 4-Bit Serial In Parallel Out Shift Register

63
 Post Test

Based on how binary information is entered or shifted out, shift registers are classified
into _______ categories.
a: 2 b: 3 c: 4 d: 5
How can parallel data be taken out of a shift register simultaneously?
a: Use the Q output of the first FF b: Use the Q output of the last FF c: Tie all of
the Q outputs together d: Use the Q output of each FF
The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel
output shift register with an initial state 01110. After three clock pulses, the register
contains ________
a: 01110 b: 00001 c: 00101 d: 00101
The full form of SIPO is ___________
a: Serial-in Parallel-out b: Parallel-in Serial-out c: Serial-in Serial-out d:
Serial-In Peripheral-Out
A shift register that will accept a parallel input or a bidirectional serial load and
internal shift features is called as?
a: Tristate b: End around c: Universal d: Conversion

References:

1. William Gothmann H, Digital Electronics: An Introduction to Theory And Practice, Prentice

Hall, 2nd ed. 1982
2. M. Morris Mano, Michael D Ciletti, "Digital Design", Pearson, 4th ed. 2008
3. Thomas L. Floyd, R. P. Jain, "Digital Fundamentals", Pearson, 11th ed. 2017
4. S Salivahanan, S Arivazhagan, "Digital Circuits and Design", Vikas Publishing House Pvt
Ltd., 3rd ed. 2009
5. Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss, "Digital Systems", Pearson, 10th ed.
2009
6. Anil K. Maini, "Digital Electronics: Principles, Devices and Applications", Wiley-Blackwell,
2007
7. Shift Register (SISO & SIPO Mode) using D Flip
Flop: https://www.youtube.com/watch?v=OfoXcIymMvI
8. Shift Register: https://www.electronics-tutorials.ws/sequential/seq_5.html
9. Shift Registers: https://www.allaboutcircuits.com/textbook/digital/chpt-12/serial-in-parallel-
out-shift-register/

64
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 13

Aim: Verify the truth table of RS, JK, T and D flip-flops using NAND & NOR gates
To verify the truth table and timing diagram of RS, JK, T and D flip-flops by using NAND &
NOR gates ICs and analyse the circuit of RS, JK, T and D flip-flops with the help of LEDs
display.

Reference Link:

A flip flop is an electronic circuit with two stable states that can be used to store binary data.
The stored data can be changed by applying varying inputs. Flip-flops and latches are
fundamental building blocks of digital electronics systems used in computers,
communications, and many other types of systems.

1. R-S flip flop

2. D flip flop
3. J-K flip flop
4. T flip flop

1) RS flip flop

The basic NAND gate RS flip flop circuit is used to store the data and thus provides feedback
from both of its outputs again back to its inputs. The RS flip flop actually has three inputs,
SET, RESET and clock pulse.

Figure-1:R-S flip flop circuit diagram

65
 Figure-2:Characteristics table of R-S flip flop
2) D flip flop
A D flip flop has a single data input. This type of flip flop is obtained from the SR flip flop
by connecting the R input through an inverter, and the S input is connected directly to data
input. The modified clocked SR flip-flop is known as D-flip-flop and is shown below. From
the truth table of SR flip-flop we see that the output of the SR flip-flop is in unpredictable
state when the inputs are same and high. In many practical applications, these input
conditions are not required. These input conditions can be avoided by making them
complement of each other.

Figure-3:Circuit diagram of D flip flop

66
 Figure-4: Characteristics table of D flip flop

3) J-K flip flop

In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS flip-flop circuit
may be re-joined if both inputs are 1 than also the outputs are complement of each other as
shown in characteristics table below.

Figure-5:Circuit diagram of J-K flip flop

67
 Figure-6:Characteristics table of J-K flip flop

4) T flip flop

T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K flip-flop.
Both the JK inputs of the JK flip – flop are held at logic 1 and the clock signal continuous to
change as shown in table below.

Figure-7:Circuit diagram of T flip flop

68
 Figure-8:Characteristics table of T flip flop

Pretest:

The output of latches will remain in set/reset until ___________

a: The trigger pulse is given to change the state b: Any pulse given to go into
previous state c: They don’t get any pulse more d: The pulse is edge-triggered
What is a trigger pulse?
a: A pulse that starts a cycle of operation b: A pulse that reverses the cycle of
operation c: A pulse that prevents a cycle of operation d: A pulse that enhances a
cycle of operation
If Q = 1, the output is said to be ___________
a: Set b: Reset c: Previous state d: Current state
The sequential circuit is also called ___________
a: Flip-flop b: Latch c: Strobe d: Adder
The basic latch consists of ___________
a: Two inverters b: Two comparators c: Two amplifiers d: Two adders

Procedure:

1) SR flip flop

Step-1) Connect the supply(+5V) to the circuit.

Step-2) First press "ADD" button to add basic state of your output in the given table.
Step-3) Press the switches to select the required inputs "S" and "R" and apply the clock pulse.
Step-4) Press "ADD" button to add your inputs and outputs in the given table and their
corresponding graph.

69
Step-5) Repeat steps 3&4 for next state of inputs and their corresponding outputs.
Step-6) Press the "Print" button after completing your simulation to get your results.

2) D flip flop

Step-1) Connect the supply(+5V) to the circuit.

Step-2) First press "ADD" button to add basic state of your output in the given table.
Step-3) Press the switches to select the required inputs "D" and "Clock" .
Step-4) Press "ADD" button to add your inputs and outputs in the given table and their
corresponding graph.
Step-5) Repeat step 3 & step 4 for next state of inputs and their corresponding outputs.
Step-6) Press the "Print" button after completing your simulation to get your results.

3) J-K flip flop

Step-1) Connect the supply(+5V) to the circuit.

Step-2) First press "ADD" button to add basic state of your output in the given table.
Step-3) Press the switches to select the required inputs "J" and "K" and apply the clock pulse.
Step-4) Press "ADD" button to add your inputs and outputs in the given table and their
corresponding graph.
Step-5) Repeat step 3 & step 4 for next state of inputs and their corresponding outputs.
Step-6) Press the "Print" button after completing your simulation to get your results.

4) T flip flop

Step-1) Connect the supply(+5V) to the circuit.

Step-2) First press "ADD" button to add basic state of your output in the given table.
Step-3) Press the switches to select the required inputs "T" and apply the clock pulse.
Step-4) Press "ADD" button to add your inputs and outputs in the given table and their
corresponding graph.
Step-6) Press the "Print" button after completing your simulation to get your results.

Simulation:

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71
72
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Post Test:

Which of the following is correct for a gated D-type flip-flop?

a: The Q output is either SET or RESET as soon as the D input goes HIGH or LOW
b: The output complement follows the input when enabled c: Only one of the inputs
can be HIGH at a time d: The output toggles if one of the inputs is held HIGH
A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?

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 a: AND or OR gates b: Ex-OR or Ex-NOR gates c: NOR or NAND gates d:
AND or NOR gate
The truth table for an S-R flip-flop has how many valid entries?
a: 1 b: 2 c: 3 d: 4
The flip-flops which has not any invalid states are _____________
a: S-R, J-K, D b: S-R, J-K, T c: J-K, D, S-R d: J-K, D, T
Both the J-K & the T flip-flop are derived from the basic _____________
a: S-R flip-flop b: S-R latch c: D latch d: D flip-flop

References:
1. William Gothmann H, Digital Electronics: An Introduction To Theory And Practice ,
Prentice Hall, 2nd ed. 1982
2. M. Morris Mano, Michael D Ciletti, "Digital Design", Pearson, 4th ed. 2008
3. Thomas L. Floyd, R. P. Jain, "Digital Fundamentals", Pearson, 11th ed. 2017
4. S Salivahanan, S Arivazhagan, "Digital Circuits and Design", Vikas Publishing House Pvt
Ltd., 3rd ed. 2009
5. Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss, "Digital Systems", Pearson, 10th ed.
2009
6. Anil K. Maini, "Digital Electronics: Principles, Devices and Applications", Wiley-Blackwell,
2007
7. SR Flip-Flop with NAND Gates: https://circuitdigest.com/electronic-circuits/sr-flip-flop-
circuit-using-nand-gates
8. D latch: https://www.youtube.com/watch?v=peCh_859q7Q
9. JK Flip-Flop: https://www.youtube.com/watch?v=1mnowDsoAx0
10. D Type Flip-Flop: https://circuitdigest.com/electronic-circuits/d-flip-flops
11. T Flip-Flop: http://hyperphysics.phy-astr.gsu.edu/hbase/Electronic/Tflipflop.html
12. T Flip Flop Circuit: https://www.youtube.com/watch?v=wpoXdZmbIF0

75
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 14

Aim:

Verify the truth table of one bit and two-bit comparator using logic gates.

To analyse the truth table of 1-bit comparator by using NOT, AND and NOR logic gate ICs
and 2-bit comparator by using 1-input NOT, 3-input AND, 2-input AND, 3-input OR and 2-
input Ex-NOR logic gate ICs and to understand the working of 1-bit comparator and 2- bit
comparator with the help of LEDs display.

A magnitude digital comparator is a combinational circuit that compares two digital or binary
numbers in order to find out whether one binary number is equal, less than or greater than the
other binary number. We logically design a circuit for which we will have two inputs one for
A and other for B and have three output terminals, one for A > B condition, one for A = B
condition and one for A < B condition.

Figure-1: Block Diagram of Comparator

1) 1-Bit Magnitude Comparator:

A comparator used to compare two bits is called a single bit comparator. It consists of two
inputs each for two single bit numbers and three outputs to generate less than, equal to and
greater than between two binary numbers. The truth table for a 1-bit comparator is given
below:

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Figure-2: Truth Table of 1-Bit Comparator
From the above truth table logical expressions for each output can be expressed as follows:
A > B : AB'
A < B : A'B
A = B : A'B' + AB

By using these Boolean expressions, we can implement a logic circuit for this comparator as
given below :

Figure-3: Logic Circuit of 1-Bit Comparator

2) 2-Bit Magnitude Comparator :

A comparator used to compare two binary numbers each of two bits is called a 2-bit
magnitude comparator. It consists of four inputs and three outputs to generate less than, equal
to and greater than between two binary numbers.

The truth table for a 2-bit comparator is given below:

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Figure-4: Truth Table of 2-Bit Comparator

From the above truth table logical expressions for each output can be expressed as follows:
A > B : A1B1’ + A0B1’B0’ + A1A0B0’
A = B : A1’A0’B1’B0’ + A1’A0B1’B0 + A1A0B1B0 + A1A0’B1B0’
: A1’B1’ (A0’B0’ + A0B0) + A1B1 (A0B0 + A0’B0’)
: (A0B0 + A0’B0’) (A1B1 + A1’B1’)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A < B : A1’B1 + A0’B1B0 + A1’A0’B0

By using these Boolean expressions, we can implement a logic circuit for this comparator as
given below :

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Figure-5: Logic Circuit of 2-Bit Comparator

Applications of Comparators : 1. Comparators are used in central processing units (CPUs)

and microcontrollers (MCUs).
2. These are used in control applications in which the binary numbers representing physical
variables such as temperature, position, etc. are compared with a reference value.
3. Comparators are also used as process controllers and for Servo motor control.
4. Used in password verification and biometric applications.

Pretest:

All the comparisons made by comparator is done using _____________ .

a: 1 circuit b: 2 circuits c: 3 circuits d: 4 circuits
One that is not the outcome of magnitude comparator is ____________ .
a: a > b b: a – b c: a < b d: a = b
If two numbers are not equal then binary variable will be ____________ .
a: 0 b: 1 c: A d: B
Which one is a basic comparator?
a: AND b: Ex-OR c: NAND d: Ex-NOR
Comparators are used in ____________ .
a: Memory b: Motherboard c: CPU d: Hard drive

Procedure:

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1- Bit Comparator

Simulator 1:

Step-1) Switch ON the power supply button to supply 5V to the circuit.

Step-2) Press Switch 1 for input A and Switch 2 for input B.

The switch in ON state is and the switch in OFF state is

Step-3) i)When the input A is greater than the input B,LED 1 lits up.
ii)When the input A is lesser than the input B,LED 2 lits up.
iii)When the input A is equal to the input B,LED 3 lits up.

The LED in OFF state is and the LED in ON state is .

Step-4) Click on "Add" Button to add data to the Truth Table.
Step-5) Repeat Steps 2 to 4 for another set of data.
Step-6) Click "Print" to get the print out of the Truth Table.

Simulator 2:

Step-1) Enter the Boolean input "A" and "B".

Step-2) Enter the Boolean output for your corresponding inputs.
Step-3) Click on "Check" Button to verify your output.
Step-4) Click "Print" if you want to get print out of Truth Table.

2- Bit Comparator

Simulator 1:

Step-1) Switch ON the power supply button to supply 5V to the circuit.

Step-2) Press Switch 1 for input A1,Switch 2 for input A0,Switch 3 for input B1and Switch 4
for input B0.

The switch in ON state is and the switch in OFF state is

Step-3) i)When the input A1A0 is greater than the input B1B0,LED 1 lits up.
ii)When the input A1A0 is lesser than the input B1B0,LED 2 lits up.
iii)When the input XA1A0 is equal to the input B1B0,LED 3 lits up.

The LED in OFF state is and the LED in ON state is .

Step-4) Click on "Add" Button to add data to the Truth Table.
Step-5) Repeat Steps 2 to 4 for another set of data.
Step-6) Click "Print" to get the print out of the Truth Table.

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Simulator 2:

Step-1) Enter the two bit Boolean input "A" and "B".
Step-2) Inputs should be written such that for 'A'="A1A0" and for 'B'="B1B0"
Step-3) Enter the Boolean output for your corresponding inputs.
Step-4) Click on "Check" Button to verify your output.
Step-5) Click "Print" if you want to get print out of Truth Table.

Simulation:

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82
Post Test:

The purpose of a Digital Comparator is ____________ .

a: To convert analog input into digital b: To create different outputs c: To add a
set of different numbers d: To compare a set of variables or unknown numbers
A magnitude comparator is defined as a digital comparator which has ____________ .
a: Only one output terminal b: Two output terminals c: Three output terminals
d: No output terminal
In a comparator, if we get input as A>B then the output will be ___________ .
a: B b: 1 c: A d: 0
How many inputs are required for a digital comparator?

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 a: 1 b: 3 c: 2 d: 4
An identify comparator is defined as a digital comparator which has ____________ .
a: Only one output terminal b: Two output terminals c: Three output terminals
d: No output terminal

References:

1. William Gothmann H, Digital Electronics: An Introduction To Theory And Practice, Prentice

Hall, 2nd ed. 1982
2. M. Morris Mano, Michael D Ciletti, "Digital Design", Pearson, 4th ed. 2008
3. Thomas L. Floyd, R. P. Jain, "Digital Fundamentals", Pearson, 11th ed. 2017
4. S Salivahanan, S Arivazhagan, "Digital Circuits and Design", Vikas Publishing House Pvt
Ltd., 3rd ed. 2009
5. Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss, "Digital Systems", Pearson, 10th ed.
2009
6. Anil K. Maini, "Digital Electronics: Principles, Devices and Applications", Wiley-Blackwell,
2007
7. 1 Bit comparator: https://www.youtube.com/watch?v=UO-K0Jx2Hs0
8. Magnitude Comparator: https://www.geeksforgeeks.org/magnitude-comparator/
9. Digital Comparator and Magnitude Comparator: https://www.electronicshub.org/digital-
comparator-and-magnitude-comparator/

84
 SVKM’s NMIMS
Mukesh Patel School of Technology Management & Engineering
Department of Electronics &Telecommunication Engineering

SUB: DIGITAL DESIGN

EXPERIMENT NO. 15

Aim:

Verify Binary to Gray and Gray to Binary conversion using NAND gates only.
To analyse the truth table of binary to gray and gray to binary converter using combination of
NAND gates and to understand the working of binary to gray and gray to binary converter
with the help of LEDs display.

Reference Link: Virtual Lab

https://de-iitr.vlabs.ac.in/exp/binary-conversion/

Theory:

Binary Numbers is default way to store numbers, but in many applications binary numbers
are difficult to use and a variation of binary numbers is needed. Gray code is an ordering of
the binary numeral system such that two successive values differ in only one bit (binary
digit). Gray codes are very useful in the normal sequence of binary numbers generated by the
hardware that may cause an error or ambiguity during the transition from one number to the
next. So, the Gray code can eliminate this problem easily since only one bit changes its value
during any transition between two numbers.

Gray code has property that two successive numbers differ in only one bit because of this
property gray code does the cycling through various states with minimal effort and used in K-
maps, error correction, communication etc.

In computer science many a times we need to convert binary code to gray code and vice
versa. This conversion can be done by applying following rules:

1) Binary to Gray conversion:

1. The Most Significant Bit (MSB) of the gray code is always equal to the MSB of the given
binary code.
2. Other bits of the output gray code can be obtained by Ex-ORing binary code bit at that index
and previous index.

There are four inputs and four outputs. The input variable are defined as B3, B2, B1, B0 and
the output variables are defined as G3, G2, G1, G0. From the truth table, combinational circuit

85
is designed. The logical expressions are defined as :

B3 = G3

B2 ⊕ B3 = G2

B1 ⊕ B2 = G1

B0 ⊕ B1 = G0

Figure-1: Binary to Gray Code Converter Circuit

Figure-2: Binary to Gray Code Converter Truth Table

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2) Gray to binary conversion:

1.The Most Significant Bit (MSB) of the binary code is always equal to the MSB of the given
binary number.
2.Other bits of the output binary code can be obtained by checking gray code bit at that index.
If current gray code bit is 0, then copy previous binary code bit, else copy invert of previous
binary code bit.

There are four inputs and four outputs. The input variable are defined as G3, G2, G1, G0 and
the output variables are defined as B3, B2, B1, B0. From the truth table, combinational circuit
is designed. The logical expressions are defined as :

G0 ⊕ G1 ⊕ G2 ⊕ G3 = B0

G1 ⊕ G2 ⊕ G3 = B1

G2 ⊕ G3 = B2

G3 = B3

Figure-3: Gray to Binary Code Converter Circuit

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 Figure-4: Gray to Binary Code Converter Truth Table

Pre Test:

A code converter is a logic circuit that _____________ .

a: Inverts the given input b: Converts into decimal number c: Converts data of
one type into another type d: Converts to octal
The primary use for Gray code is ___________ .
a: Coded representation of a shaft’s mechanical position b: Turning on/off software
switches c: To represent the correct ASCII code to indicate the angular position of a shaft
on rotating machinery d: To convert the angular position of a shaft on rotating machinery
into hexadecimal code
4-bit gray code can be converted into ____________ .
a: 1-bit binary b: 2-bit binary c: 3-bit binary d: 4-bit binary
Gray to binary conversion can be implemented with _____________ .
a: AND b: Ex-OR c: NAND d: NOR
A binary code that progresses such that only one bit changes between two successive
codes is:
a: Nine's-complement code b: 8421 code c: Excess-3 code d: Gray code

Procedure:

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Gray to Binary Conversion

Step-1) Connect battery to supply 5V to the circuit.

Step-2) Press Switches for different inputs.

The switch in ON state is and the switch in OFF state is

Step-3) The corresponding combination of input and output LEDs lit up for different
combination of inputs.
The input gray code LEDs are G3,G2,G1 and G0 and the output binary code LEDs
B3,B2,B1 and B0 glow accordingly.

The input LED in OFF state is and in ON state is .

The output LED in OFF state is and in ON state is .

Step-4) Click "Add" to add the values to the Truth Table.

Step-5) Click "Print" to get the print out of the Truth Table.

Binary to Gray Code Conversion

Step-1) Connect battery to supply 5V to the circuit.

Step-2) Press Switches for different inputs.

The switch in ON state is and the switch in OFF state is

Step-3) The corresponding combination of input and output LEDs lit up for different
combination of inputs.
The input binary code LEDs are B3,B2,B1 and B0 and the output gray code LEDs
G3,G2,G1 and G0 glow accordingly.

The input LED in OFF state is and in ON state is .

The output LED in OFF state is and in ON state is .

Step-4) Click "Add" to add the values to the Truth Table.

Step-5) Click "Print" to get the print out of the Truth Table.

Simulation:

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90
Post Test:

Convert binary number into gray code: 100101

a: 101101 b: 001110 c: 110111 d: 111001
If two systems have different codes then circuit inserted between them is ___________ .
a: Combinational circuit b: Sequential circuit c: Combinational sequence circuit
d: Conversion circuit

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 Reflected binary code is also known as ___________ .
a: BCD code b: Gray Code c: ASCII code d: Binary code
Code is a symbolic representation of __________ .
a: Discrete information b: Continuous information c: Decimal information into
binary d: Binary information into decimal
Convert gray code into binary code: 0101 .
a: 1001 b: 0110 c: 1101 d: 0111

References:

1. William Gothmann H, Digital Electronics : An Introduction To Theory And Practice ,

Prentice Hall, 2nd ed. 1982
2. M. Morris Mano, Michael D Ciletti, "Digital Design", Pearson, 4th ed. 2008
3. Thomas L. Floyd, R. P. Jain, "Digital Fundamentals", Pearson, 11th ed. 2017
4. S Salivahanan, S Arivazhagan, "Digital Circuits and Design", Vikas Publishing House Pvt
Ltd., 3rd ed. 2009
5. Ronald J. Tocci, Neal S. Widmer, Gregory L. Moss, "Digital Systems", Pearson, 10th ed.
2009
6. Anil K. Maini, "Digital Electronics: Principles, Devices and Applications", Wiley-Blackwell,
2007
7. Code Converters – Binary to/from Gray Code: https://www.geeksforgeeks.org/digital-logic-
code-converters-binary-gray-code/
8. Gray Code: Binary to Gray Code Converter: https://www.electrical4u.com/binary-to-gray-
code-converter-and-grey-to-binary-code-converter/

92