8.

IMPLEMENTATION AND VERIFICATION OF FLIP-FLOPS AND

COUNTERS

8.1 Objective

To implement and verify sequential logic functions of Flip-flops and Counters using standard
ICs.

8.2 Hardware Requirement

a. Equipment - Digital IC Trainer Kit

b. Discrete Components - 74LS73 JK-Flip flop
74LS74 D-Flip flop
DM74161 Synchronous 4-Bit Counter

8.3 Introduction

Digital electronic circuits are classified into combinational logic and sequential logic.
Combinational logic output depends on the input’s levels, whereas sequential logic output depends
on stored levels and also the input levels.

Fig. 8.1 Sequential logic representation

The storage elements (Flip-flops) are devices capable of storing 1-bit binary information. The
binary information stored in the memory elements at any given time defines the state of the
sequential circuit. The input and the present state of the memory element determines the output.
Storage element’s next state is also a function of external inputs and present state.
8.3.1 Flip-Flops
Flip-flops are synchronous bistable devices. The term synchronous means the output
changes state only when the clock input is triggered. That is, changes in the output occur in
synchronization with the clock. A flip-flop circuit has two outputs, one for the normal value and
one for the complement value of the stored bit. The flip-flops are of four basic types: SR, JK, D
and T. They differ in the number of inputs and in the response invoked by different value of input
signals. The four types of flip-flops are defined in Table 8.1. The characteristic table in the third
column defines the state of each flip-flop as a function of its inputs and its previous state. Q refers
to the present state and Q(next) refers to the next state after the occurrence of the clock pulse.
Table 8.1 Flip-Flops Characteristic Table
8.3.2 Counters

Circuits for counting events are frequently used in computers and other digital systems. Since a
counter circuit must remember its past states and has memory. The number of flip flops used
and how they are connected determine the number of states and the sequence of the states that
the counter goes through in each complete cycle. Counters can be classified into two broad
categories according to the way they are clocked:

a. Asynchronous (Ripple) Counters - the first flip-flop is clocked by the external clock
pulse, and then each successive flip -flop is clocked by the Q or Q' output of the previous
flip -flop.
b. Synchronous Counters - all memory elements are simultaneously triggered by the same
clock.

8.4 Pin Diagram and Truth Table of ICs

8.4.1 IC 7474 - D Flip-flop

Fig. 8.2 IC 7474 D Flip-flop Pin Diagram and Truth Table

8.4.2 IC 7473 J-K Flip-flop

Fig. 8.3 IC 7473 J-K Flip-flop Pin Diagram and Truth Table

8.4.3 DM74161- Synchronous 4-Bit Counter

It is a synchronous 4-bit binary counter that is part of the TTL (Transistor-Transistor Logic)
family. This counter is widely used in digital electronics for applications such as counting,
frequency division, and timing.

Fig. 8.4 DM74161 Pin Diagram

Counting Example:

• Suppose the counter is at 0000, and all enable inputs are High:

o After the first clock pulse: 0001

o After the second clock pulse: 0010

o And so on, until it reaches 1111.

o On the next clock pulse after 1111, the counter rolls over to 0000 and RCO goes
High (H), indicating the counter has reached its maximum count.

Key Features

• Synchronous Operation: All four flip-flops in the counter are triggered simultaneously
by the clock input, ensuring that the outputs change in unison without propagation delays
that are common in asynchronous counters.

• Presettable: The counter can be loaded with a preset value by using the parallel data inputs
and activating the Load input. This allows the counter to start counting from any desired
value.

• Clear Function: The asynchronous Clear (CLR) input allows the counter to be reset to
zero at any time, regardless of the clock signal.

• Enable Input (ENP, ENT): These inputs control whether the counter increments with
each clock pulse. Both inputs must be high for the counter to count.

• Ripple Carry Output (RCO): This output provides a signal when the counter reaches its
maximum count (1111 in binary), allowing the counter to be cascaded with additional
counters to count beyond 4 bits.

8.4.3.1 Pin Configuration

• Inputs:

o CLR: Asynchronous Clear input. When low, it resets the counter to zero.
 o CLK: Clock input. On the rising edge of the clock, the counter increments if
enabled.

o ENP: Count Enable Parallel. Must be high to allow counting.

o ENT: Count Enable Trickle. Must be high to allow counting and to enable the
ripple carry output.

o LOAD: When low, loads the value on the parallel data inputs into the counter.

o A, B, C, D: Parallel data inputs used to preset the counter.

• Outputs:

o QA, QB, QC, QD: The 4-bit binary output of the counter.

o RCO: Ripple Carry Output, used for cascading counters.

8.4.3.2 Operation

• Counting: When both ENP and ENT are high, the counter increments its value on each
rising edge of the clock (CLK). The outputs (QA–QD) represent the current count in
binary.

• Loading: When the LOAD input is low, the counter loads the binary value present on the
parallel data inputs (A–D) into the counter on the next clock pulse, instead of counting.

• Clearing: When the CLR input is low, the counter is asynchronously reset to zero,
regardless of the clock or enabled inputs.

The DM74161 is a versatile component in digital design, offering reliable synchronous counting
with the ability to preset values and cascade with other counters for extended counting ranges.
Fig. 8.5 DM74161 Logic Diagram
 Fig. 8.6 DM74161 Timing Diagram

8.5 Lab Procedure

i.Refer datasheet for the input and output pin numbers of the IC.
ii.Connect the input pins to the logic input section using a connecting wire.
iii.Similarly connect the output pin to the logic output section of the trainer kit.
ivVerify the functionality of JK Flip flop and D Flip flop and Counters.
8.6 Result
Thus, the sequential logic functions using standard ICs such as 74LS73 JK-Flip flop, 74LS74 D-
Flip flop and DM74161 Synchronous 4-Bit Counter have been implemented and its truth table
has been verified.
 8.7 Pre-Lab Questions
1. Define flip-flop and list out some of its applications.
2. At what condition a J-K Flip-flop can be made toggle?
a) J=0, K=0 b) J=1, K=0
c) J=0, K=1 d) J=1, K=1
3. What is a synchronous counter, and how does it differ from an asynchronous counter?
4. Compare up-counters and down-counters.
5. A 4-bit binary ripple counter uses flip-flops with propagation delay time of 25ns each.
What is the maximum possible time required for change of state?

8.8 Post-Lab Questions

1. What is the difference between combinational and sequential logic circuits?

2. In a JK flip flop, we have J = Q’ and K = 1. Assume the flip flop was initially cleared and
then clocked for 6 pulses, the sequence at the Q output will be.
a. 010000 b. 011001 c. 010010 d. 010101
3. How would you cascade multiple DM74161 counters to create a larger counter?
4. How would you use DM74161 to create a Mod-10 counter?
5. What is the maximum number that can be obtained by a ripple counter by using five flip-
flops?