ECE 270: Embedded Logic Design

Dr. Sumit J Darak

Algorithms to Architectures Lab
Associate Professor, ECE, IIIT Delhi
http://faculty.iiitd.ac.in/~sumit/
ASIC vs. FPGA vs. Microcontroller*

https://www.youtube.com/watch?v=vxSvQ-IcmHM
ASIC
• ASIC: Application Specific Integration Circuits
ASIC
• ASIC: Application Specific Integration Circuits
• High non-recurring engineering cost (one-time cost to research,
design, develop and test a new product) and longest design cycle
• High cost for engineering change orders (Testing is critical! And hence,
preferred when design is finalized)
• Lowest price for high volume production
• Fastest clock performance (high performance)
• Unlimited size and Low power
• Design and test tools are expensive
• Expensive IPs
FPGA: Field Programmable Gate Array
• Array of generic logic gates
• Gates where logic function
can be programmed
• Programmable
interconnection between
gates
• Field: System can be
reprogrammed in the field
(After fabrication)
FPGA Architecture
FPGA
• Lowest cost for low to medium volume
• No NRE cost and Fastest time to market
• Field reconfigurable and partial reconfigurable
• Slower performance than ASIC (still 550 MHz)
• Limited size and steep learning curve
• Digital only*
• Industry often use FPGAs to prototype their
chips before creating them (FPGA before
ASIC).
 FPGA vs ASIC

• Demand for specialized systems and short device life -> FPGAs
Microcontrollers
• Similar to simple computer placed in a single chip with all necessary
components like memory, timers etc. embedded inside and performs
a specific task.
• Example: Arduino, Pic
• Sequential execution, easy to use, control over software
• Consumes less power than FPGAs and mostly suitable for edge
operations.
• Supports fixed as well as floating point operations
• Microprocessors: Completely different than microcontrollers.
Microprocessors
• ICs that come with a computer or CPU inside and are equipped with
processing power. Examples: Pentium 3, 4, i5 etc.
• No peripherals such as RAM, ROM on the chip.
• Microprocessors form the heart of a computing system (general
complex high-speed tasks) while microcontrollers drive embedded
systems (specific tasks).
• Bulky due to the external peripherals

• Expensive than micro-controllers

Microprocessor vs FPGA vs ASIC
Microprocessor vs FPGA vs ASIC vs GPU
SoC Zedboard
 FPGA Architecture
Lowest Power Industry’s Best Industry’s Highest All Programmable
Maximum Capability and Cost Performance SoC
Price/Performance
Summary
• FPGA/ASIC: Parallel execution, HDL (Verilog/VHDL), control over hardware
• You can make microcontroller inside FPGA/ASIC but not the other way round
• Time vs space limited
• FPGAs can perform any task while microcontrollers are limited by instruction
sets while ASICs are application specific. FPGA are filed-reconfigurable.
• Power consumption is high in FPGA
• FPGAs/ASICs can not be avoided in applications with stringent computational
and memory requirements or applications with high level of determinism
• New world SoC: ARM + FPGA + GPU
Generic FPGA Design Flow
FPGA Design Flow
• Integrated circuit technology has improved to allow more and more
components on chip
FPGA Design Flow
• All the designs start with design requirements
and design specifications
• Next step is to formulate the design
conceptually either at block diagram level or
at an algorithmic level
 FPGA Design Flow
• Design Entry:
• Olden days: Hand-drawn schematic
• Now, computer-aided design (CAD) tools: Mostly
using HDLs
FPGA Design Flow
• Behavioral simulation to ensure that the
design is functionally correct
• Can be done using: Test benches, test bench
waveforms
Functional (HDL/RTL) Simulation
HDL/RTL Simulation
• Self-checking test bench: Contains output data and self-checking
code that can be used to compare the data from later simulation
runs
• When running a simulation with this kind of test bench, simulation
outputs will be monitored. If a difference is detected between the
predicted and the actual outputs, an error is reported.
• Automate the task of verifying simulation results i.e. no need to
manually check waveform results
HDL/RTL Simulation
FPGA Design Flow
FPGA Design Flow
FPGA Design Flow
Translation
• Translate process merges all of
the input netlists and design
constraints and outputs a Xilinx
native generic database (NGD)
file
Mapping
• The Map process maps the
logic defined by an NGD file
into FPGA elements, such as
CLBs and IOBs.
• The output design is a
native circuit description
(NCD) file that physically
represents the design
mapped to the components
in the FPGA.
Post-map Static Timing
• You can generate a post-map static timing report for your design.
• It lists only the signal path delays in your design, derived from the
design logic.
• Useful in evaluating timing performance of the logic paths,
particularly if your design does not meeting timing requirements
• Route delays are not accounted (You can eliminate potential problems
before investing time in examining routing delays)
• To eliminate problems, you may choose to redesign the logic paths to
use fewer levels of logic, tag the paths for specialized routing
resources, move to a faster device, or allocate more time for the path.
Placing
• The Place and Route process takes a mapped
NCD file, places and routes the design, and
produces an NCD file that is used as input for
bitstream generation.
Routing
Routing
Post-place and Route Static Timing
• Incorporates timing delay (signal and routing delay) information to
provide a comprehensive timing summary of your design
• If you identify problems in the timing report, you can try fixing the
problems by increasing the placer effort level, using re-entrant
routing, or using multi-pass place and route.
• You can also redesign the logic paths to use fewer levels of logic,
move to a faster device, or allocate more time for the paths.
• If a placed and routed design has met all of your timing constraints,
then you can then create configuration data.
FPGA Design Flow
• FPGA programming simply involves writing a
sequence of 0 and 1 into the programmable
cells of FPGAs
• Once a design is implemented, you must
create a file that the FPGA can understand.
This file is called a bitstream: a BIT file (.bit
extension)
• The BIT file can be downloaded directly to the
FPGA or can be converted into a PROM file
which stores the programming information.
FPGA Design Process
ASIC Design Flow
• In ASIC, routed design is used to generate
photomask for producing integrated circuits
Digital Circuits Revisited!
Combinational vs Sequential Circuits
FSMs
Counter: FSMs
• For a counter with counting sequence of
{0,1,2,3,4,5,6,0,1,2,3,4,5,6,0,1,....}, how many flip-flops are needed?

• For a counter with counting sequence of {0,3,5,0,3,5,0,3,....}, how

many flip-flops are needed?
Verilog
Verilog
• One of the two major HDLs used by hardware designers in Industry
and Academia (Another is VHDL)
• C- based Syntax, easy to master and intensively used by Indian VLSI
Industry
• 1983: Introduced by Gateway Design System
• Invented as simulation language. Synthesis was an afterthought
• 1987: Verilog synthesizer by Synopsis
• 1989: Cadence acquired Gateway Design System and became the
language owner
Verilog
• Around the same time (1981-1988), the US Department of Defence
developed VHDL (VHSIC HDL). Because it was in the public domain it began
to grow in popularity.
• Afraid of losing market share, Cadence opened Verilog to the public in
1990.
• 1995: Became IEEE Standard 1364
• 2001 and 2005: New and improved version of Verilog (made life much
easier)
• Latest Verilog version is “System Verilog” .
• Ongoing efforts for automating the mapping of the code written in high
level language (C, System C, Python) to Verilog/VHDL
Few words of wisdom
• One of the common mistakes for beginners is to think of HDL as a
computer program rather than as a shorthand for describing digital
hardware.
• If you do not know approximately what hardware your HDL should
synthesize into, you probably won’t like what you get.
• You might create far more hardware than is necessary or you might write
non-synthesizable code
• THINK of your system in terms of blocks of combinational logic, registers
and FSMs. SKETCH these blocks on paper and show how they are
connected BEFORE you start writing code.
• Describing hardware with a language is similar, however, to writing a
parallel program
Verilog
• Verilog looks like C, but it describes hardware
• First understand the circuit and specifications you want then figure
out how to code it in Verilog.
• A large part of ELD (before mid-sem) is knowing how to write Verilog
that gets you the desired circuit.
• If you do one of these activities without the other, you will struggle.
• These two activities will merge at some point for you
Verilog:
• Verilog HDL is a case-sensitive language
• All keywords are in lowercase (assign, for, always, fork, if, else, input, output…)
• Statements are terminated by a semicolon (;)
• Two data types: Net (wire) and variable (Reg, Integer, real, time, realtime)
• Primitive Logic Gates and Switch-Level Gates, are built-in (Rarely used in ELD)
• Single line comments begin with the “// “and end with a carriage return.
// This is one line comment
• Multi Line comments begin with the “/*” and end with the “*/”
/* This is a multiple
lines
comments */
Verilog: Identifiers
• Identifiers are names given to an object, such as a register or a function or
a module, so that it can be referenced from other places in a description
• Identifiers must begin with an alphabetic character or the underscore
character
• Identifier cannot start with a number or dollar sign
• Identifiers may contain alphabetic characters, numeric characters,
underscore, and dollar sign
• Identifiers can be up to 1024 characters long
• Identifiers examples:
wire outAdd ; // wire is a keyword, outAdd is an identifier
reg sum ; // reg is a keyword, sum is an identifier
Verilog: Module
• Verilog describes a digital system as a set of modules
• Each module has an interface and contents description
• Modules communicate externally with input, output and bi-
directional ports (inout)
• Verilog modules consist of a list of statements declaring relationships
between a module and its environment, and between signals within a
module
Verilog: Module (Examples)
Verilog: Module (Examples)
 Verilog
module exam_1 (o1,in1,in2,in3); //module
output o1;
input in1,in2,in3;
and a1 (Q, in1, in3); //and instantiation
not n1 (P,in3); // not instantiation
and a2 (R, in2, P); // and instantiation
or o1 (o1, Q, R); // or instantiation
Endmodule
Verilog