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13 views35 pages

2c97da2clecture 15 PDF

Uploaded by

yatin singh
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ECE 270: Embedded Logic Design

RAM HDL Coding Techniques


• Data is written synchronously into the RAM for both types.
• The primary difference between distributed RAM and dedicated block
RAM lies in the way data is read from the RAM
• Single-Port block RAM
with read first mode
• Single-Port block RAM
with write first mode
• Single port block RAM
with no change mode
• Simple Dual Port Block
RAM
• Single Clock
• Two clock (HW)
True Dual Port BRAM
• Dual-Port Block RAM with
Two Write Ports in Read
First Mode
• Dual-Port RAM with
Asynchronous Read
(Distributed RAM)
ROM Modelling
ROM Modelling
Summary: Block RAM
• Dual-port 36 Kb block RAM
• Multiple configuration options: True dual port, simple dual port, single
port
• Built-in cascade logic for 64Kx1 (only for true dual port)
• Fully synchronous operation (Nothing happens without a clock)
• Two ports are symmetrical and totally independent, sharing only the
stored data
• In addition, the read port width can be different from the write port width
for each port.
• The memory content can be initialized or cleared by the configuration
bitstream.
Summary: Block RAM
• The Block Memory Generator core can generate memory structures from
1 to 4608 bits wide, and at least two locations deep.
• The maximum depth of the memory is limited only by the number of
block RAM primitives in the target device.
FIFO (First In First Out)
FIFO (First In First Out)
Flags: Empty
waddr

raddr

• The Empty flag is asserted when the last entry in the FIFO is read.
• When there are no more valid entries in the FIFO queue, the read
pointer is frozen.
• The Empty flag is deasserted after new data is written into the FIFO.
• The Empty flag is used in the read clock domain.
• The rising edge of Empty flag is inherently synchronous with RDCLK.
Flags: Almost Empty
• The Almost Empty flag is set when the FIFO contains the number of
entries specified by the ALMOST_EMPTY_OFFSET* value or fewer
entries.
• The Almost Empty flag warns you to stop reading.
• It deasserts when the number of entries in the FIFO is greater than
the ALMOST_EMPTY_OFFSET value.
• Assertion and deassertion is synchronous to RDCLK.
Flags: Read Error (Underflow)
• After the Empty flag has been asserted, any further read attempts do
not increment the read address pointer but do trigger the Read Error
flag.
• The Read Error flag is deasserted when Read Enable or Empty is
deasserted Low.
• The Read Error flag is synchronous to RDCLK.
Flags: Full and Write Error (Overflow)
• The Full flag is synchronous with WRCLK, and is asserted when there
are no more available entries in the FIFO queue.
• When the FIFO is full, the write pointer is frozen.
• The Full flag is deasserted after a subsequent read operation.
• After the Full flag is asserted, any further write attempts do not
increment the write address pointer but do trigger the Write Error
flag.
• The Write Error flag is deasserted when Write Enable or Full is
deasserted Low. This signal is synchronous to WRCLK.
Flags: Almost Full
• The Almost Full flag is set when the FIFO has the number of available
empty spaces specified by the ALMOST_FULL_OFFSET value or fewer
spaces.
• The Almost Full flag warns you to stop writing.
• It deasserts when the number of empty spaces in the FIFO is greater
than the ALMOST_FULL_OFFSET value.
• Assertion and deassertion is synchronous to WRCLK.
FIFO: Modes
• Two modes: Standard and first-word fall-through (FWFT)
• The standard mode provides the user data on the cycle after it was requested. In
standard mode, the first word written into an empty FIFO appears at DO after
you have activated RDEN. You must pull the data out of the FIFO.
• First word fall-through mode presents the first-written word on the data output
even before the first read operation. In FWFT mode, the first word written into an
empty FIFO automatically appears at DO without you activating RDEN. The next
RDEN then pulls the subsequent data word onto DO.
• After the first word has been read, there is no difference between this mode and
the standard mode.
FIFO
Flags
Flags
Flags
Flags
• In the 7 series architecture, the FIFO can be configured as a 18 Kb or 36 Kb memory.
• For the 18 Kb mode, the supported configurations are 4K x 4, 2K x 9, 1K x 18, and 512 x 36. The supported
configurations for the 36 Kb FIFO are 8K x 4, 4K x 9, 2K x 18, 1K x 36, and 512 x 72.
FIFO

• When write and read operations occur simultaneously while empty is


asserted, ??
FIFO

• When write and read operations occur simultaneously while empty is


asserted, the write operation is accepted and the read operation is
ignored. On the next clock cycle, empty is deasserted and read error is
asserted
Dual Clock FIFO
Dual Clock FIFO
• The dual-clock FIFO offers a very simple user interface.
• The design relies on free-running write and read clocks, of identical or
different frequencies up to the specified maximum frequency limit.
• The write operation is synchronous, writing the data word available at DI
into the FIFO whenever WREN is active one setup time before the rising
WRCLK edge.
• The read operation is also synchronous, presenting the next data word at
DO whenever the RDEN is active one setup time before the rising RDCLK
edge.
• You must, however, observe the FULL and EMPTY flags, and stop writing
when FULL is High, and stop reading when EMPTY is High.
FIFO
Self Study:
• Write Verilog code to design FIFO with depth=32, and data width=8.
The inputs are clock, reset, write_enable, write_data, and
read_enable. The outputs are read_Data, fifo_full, fifo_empty,
write_error and read_error flags. Verify the functionality using
testbench.
• Modify the code to work as FILO (first in last out).
A+ Projects
• Understand Vivado High Level Synthesis (HLS) Tool which converts
C/C++ code into Verilog. Create hardware IP for FFT using HLS tool.
• Understand DDS (Direct Digital Synthesizer) and FIR Filter IPs in
Vivado and their features. Design and validate various features of
these IP using suitable examples.
• Understand the difference between Verilog and SystemVerilog.
Complete Lab 1-5 and FIFO (Self study question) using SystemVerilog.
• Deliverables: Handouts and Code

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