APH001 DW1000 HW Design Guide
APH001 DW1000 HW Design Guide
APH001 DW1000 HW Design Guide
Version 1.2
Table of Contents
1 INTRODUCTION ........................................................................................................................................5
1.1 OVERVIEW ................................................................................................................................................. 5
1.2 DOCUMENT STRUCTURE................................................................................................................................ 5
2 DW1000 HARDWARE SYSTEM OVERVIEW ................................................................................................6
2.1 OVERVIEW ................................................................................................................................................. 6
2.2 SYSTEM BLOCK DIAGRAM .............................................................................................................................. 6
2.3 DW1000 APPLICATION CIRCUIT .................................................................................................................... 7
3 PCB TECHNOLOGY ....................................................................................................................................9
3.1 OVERVIEW ................................................................................................................................................. 9
3.2 NUMBER OF LAYERS ..................................................................................................................................... 9
3.3 RECOMMENDED 4-LAYER PCB STACK-UP SOLUTION ........................................................................................ 11
4 LAYOUT FLOORPLAN .............................................................................................................................. 12
4.1 OVERVIEW ............................................................................................................................................... 12
4.2 POWER ARCHITECTURE ............................................................................................................................... 12
4.3 ANTENNA CONSIDERATIONS ........................................................................................................................ 14
4.4 EXAMPLE FLOORPLAN ................................................................................................................................. 16
5 POWER MANAGEMENT .......................................................................................................................... 17
5.1 SWITCHED-MODE POWER SUPPLIES .............................................................................................................. 17
6 DW1000 TRANSCEIVER ........................................................................................................................... 18
6.1 LOCAL POWER SUPPLY ROUTING AND DECOUPLING ......................................................................................... 18
6.2 EFFECTIVE CAPACITIVE DECOUPLING.............................................................................................................. 19
6.3 DECOUPLING NOISE WITH MULTIPLE CAPACITORS............................................................................................ 19
6.3.1 VDDPA1 and VDDPA2 Routing ...................................................................................................... 19
6.4 RF LAYOUT............................................................................................................................................... 20
6.4.1 Transmission Lines ........................................................................................................................ 20
6.4.2 Placement of Sensitive RF Components ........................................................................................ 22
6.5 TCXO GUIDELINES..................................................................................................................................... 23
6.6 MICROCONTROLLER INTERFACE .................................................................................................................... 24
6.6.1 SPI Mode Selection ........................................................................................................................ 24
6.6.2 Interrupt Request Output .............................................................................................................. 24
6.6.3 Reset Pin ....................................................................................................................................... 25
7 RF CONNECTORS .................................................................................................................................... 26
7.1 SURFACE-MOUNT CONNECTORS................................................................................................................... 26
7.2 SMA CONNECTORS ................................................................................................................................... 27
7.3 SEMI-RIGID ADAPTERS................................................................................................................................ 28
8 ANTENNAS ............................................................................................................................................. 29
8.1 OVERVIEW ............................................................................................................................................... 29
8.2 ANTENNA REFERENCE DESIGNS FROM DECAWAVE ........................................................................................... 29
8.2.1 WB001 .......................................................................................................................................... 29
8.2.2 WB002 .......................................................................................................................................... 30
9 ELECTROMAGNETIC INTERFERENCE ....................................................................................................... 31
9.1 OVERVIEW ............................................................................................................................................... 31
9.2 PCB GROUND STITCHING VIAS..................................................................................................................... 31
9.3 EMI SHIELD CANS ..................................................................................................................................... 32
9.4 EMI FROM PCB INTERFACES ....................................................................................................................... 33
10 REFERENCES ....................................................................................................................................... 35
10.1 LISTING .................................................................................................................................................... 35
11 DOCUMENT HISTORY ......................................................................................................................... 35
12 MAJOR CHANGES ............................................................................................................................... 35
13 FURTHER INFORMATION .................................................................................................................... 36
14 APPENDIX A: ADVANTAGES OF USING MICROVIAS AND MORE PCB LAYERS ...................................... 37
15 APPENDIX B: EVB1000 PCB LAYOUT .DXF FILES .................................................................................. 38
15.1 INTRODUCTION ......................................................................................................................................... 38
15.2 FILES SUPPLIED.......................................................................................................................................... 38
15.2.1 DW1000 section of EVB1000 layout ............................................................................................. 38
15.2.2 Top Side Copper ............................................................................................................................ 39
15.2.3 Top Side Resist .............................................................................................................................. 40
15.2.4 Top Side Silk Screen ....................................................................................................................... 41
LIST OF FIGURES
LIST OF TABLES
1 Introduction
1.1 Overview
Guidelines for successful hardware design of systems using the DW1000 UWB transceiver IC are
presented in this application note.
The Decawave EVB1000 evaluation board serves as a layout reference design which can be copied
by customers. Included in the appendices of this application note is a section showing the layout
graphics. Layout files in .dxf format are included in the package accompanying this application note.
Section Description
1. Introduction Objective of document and structural overview.
2. DW1000 Hardware System Presents a diagram of a typical hardware system, with all major
Overview blocks, including DW1000.
Focuses on DW1000 application circuit with required external
components.
3. PCB Technology Discusses the optimum number of PCB layers.
4. Layout Floorplan Suggests the best positioning of circuit blocks, antenna, etc. on
the board.
5. Power Management General layout advice for switched-mode power supply circuits.
6. DW1000 Transceiver Guidelines for successful layout of DW1000, including power
decoupling, RF tracks, etc.
7. RF Connectors PCB design guidelines for RF connectors.
8. Antennas Overview of IR-UWB antenna specifications and Decawave
reference designs.
9. Electromagnetic Managing sources of EMI from the PCB and product assembly.
Interference
14. Advantages of Using Demonstration of how physically smaller boards can be realised
Microvias and More PCB by using more layers and microvia technology.
Layers
15. EVB1000 PCB Layout .dxf Layout graphics from Decawave EVB1000 PCB.
Files
The battery is regulated to provide a 3.3 V rail for MCU and DW1000 circuits. An additional DCDC
converter is recommended for generating the DW1000 1.8 V supply rail.
3.3 V
DCDC
1.8 V
DCDC
Antenna
SPI
38.4 MHz
• RF Front-End:
An antenna is needed for the radio air interface. An antenna with a single-ended feed is
usually used, which requires a balun (T1) to convert a single-ended transmission line to the
DW1000’s balanced RF port.
• Frequency Reference:
A 38.4 MHz crystal (X1) with two loading capacitors is connected to the DW1000.
Alternatively, a TCXO reference (X2) may be used, though this requires an additional LDO
regulator (U3) to provide a low-noise power supply.
100K
optional external pull-down if SLEEP
VDD_3V3 VCC OUT
or DEEPSLEEP modes are used
VDDDIG
U3 GND GND GND
3V LDO SPICLK
GND
SPIMISO
0.1uF
VDD_TCXO GND
VDDLDOA
VDDBAT
2200pF SPIMOSI
XTAL1
VCC OUT
0.1uF
GPIO0
X2 GND
(paddle)
38.4 MHz TCXO GPIO1
GND
48
47
46
45
44
43
42
41
40
39
38
37
49
GND
X1
38.4 MHz
VDDLDOA
VDDBAT
TESTMODE
IRQ
VDDDIG
VSSIO
VDDIO
SPICLK
SPIMISO
SPIMOSI
GPIO0
GPIO1
36 optional external
1 GPIO2 GPIO2
10pF
10pF
6 VDDIO GND
GND
VDDMS DW1000 30
0.1uF 7 GPIO6 GPIO6
GND
VDDIF 29
8 SYNC SYNC
GND CLKTUNE 28 10k
9 VDDIOA VDDIOA
VDDCLK
16k
27
10 RSTn RSTn
1p2
VDDSYN
GND
0.1uF 26
11 VDDLDOD VDDLDOD
27p
VDDVCO VDD_3V3
VDDDREG
FORCEON
25
0.1uF
WAKEUP
VDDAON
VDDLNA
12 VDDAON
SPICSn
VDDPA
VDDPA
EXTON
270R 820p
VCOTUNE
RF_N
RF_P
Don’t Do
NC
NC
0.1uF
GND U1 This!
22
23
24
GND
15
16
17
18
19
20
21
18p
13
14
0.1uF
VDDLNA
VDDPA
VDDPA
GND
SPICSn
GND
WAKEUP
T1 12p EXTON
RF Traces 100R
GND
GND
Antenna RF Traces 100R U2
RF Trace 50R
VDDDIG En Vout VDDLDOD
12p
0.1 uF 1V8
VDD_3V3 Vin VDDLDOA
GND
DC-DC Convertor
(optional)
VDD_3V3
VDDPA VDDPA VDDLNA VDDBAT VDDIOA VDDAON VDDLDOD VDDLDOA
10000 pF
330 pF
330 pF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
0.1 uF
47 uF
10 pF
10pF
GND
3 PCB Technology
3.1 Overview
Having looked at the hardware system and schematics, decisions about the PCB solution can be
considered.
• RF Track Widths:
The RF transmission line dimensions need to be accurately controlled. Differences in widths
between PCB tracks and component pads should be minimised.
Figure 3 shows 50 ohm tracks on 2-layer and 4-layer boards. Much wider tracks are needed
with 2 layers, which causes impedance discontinuities with narrow component pads,
conductors of RF connectors, etc.
0.95 mm 2.9 mm
1.6 mm
Board
Height
Impedance
Track widths discontinuities
match pad
widths
SMA
Conductor
• Decoupling Capacitors:
Decoupling capacitors must be placed close to power supply pins and the return current path
to the IC should be kept as short as possible.
In the 2-layer board in Figure 4, the power tracks block the direct path of current returning to
the DW1000 in the ground plane. This makes the capacitor is less effective at decoupling
noise.
• Noise Isolation:
Sensitive signals must be isolated from noisy signals.
In the 2-layer board in Figure 4, the power tracks are routed below the sensitive crystal and
PLL loop filter components, exposing them to noise on the power tracks.
1.8 V
3.3 V 3.3 V
PLL loop filter PLL loop filter
components components
Balanced RF Port Balanced RF Port
A board with 4 layers can satisfy all of the design guidelines above by using a continuous ground
plane on the layer below the DW1000 component layer. It is therefore recommended that at least 4
copper layers are used in the PCB.
Having six or more layers offers further advantages in terms of board space, ease of routing, etc.
More detail can be found in Appendix A.
In general, PCB layers should be flooded with ground copper, i.e. the entire area of the copper layer
not occupied with traces or components should be filled with copper connected to ground. This
reduces the impedance of the ground plane, helping to keep ground at different places on the board
at the same potential. It is also important for shielding noise from sensitive traces. Copper should not
be flooded, however, near antennas on the PCB. See section 4.3 for more information.
For the layout of RF traces, the PCB manufacturer must be consulted to ensure that trace
impedances are controlled.
Copper (1 Oz) 38 µm
Copper (1 Oz) 38 µm
4 Layout Floorplan
4.1 Overview
The floorplan concerns choosing where on the board to best place the different circuit sections. The
main considerations are minimising noise coupling through power routing and avoiding interference
with the antenna’s radiation pattern.
There are a couple of fundamental factors to consider when placing the circuit sections from the point
of view of power routing.
• Power Management:
The total power consumed by the board is supplied through the regulators and chargers in
the power management section. As high currents and switching regulators are usually
involved, this circuitry should be placed close to the battery or power source and away from
RF circuits, which are sensitive to noise.
V V
Power
Digital:
Management: RF:
Battery MCU,
LDO, DCDC DW1000
Sensors
Regulators
V V
Power
Digital:
Management: RF:
Battery MCU,
LDO, DCDC DW1000
Sensors
Regulators
V V
Power
Digital:
Management: RF:
Battery MCU,
LDO, DCDC DW1000
Sensors
Regulators
A vertically polarised monopole has nulls through its vertical axis, as illustrated in the X-Z plane
pattern in Figure 7. As the PCB ground plane lies within the antenna’s null, the radiation pattern isn’t
affected but if obstructions such as copper or metallic components enter the X-Y plane, then the gain
in this direction is reduced (Figure 8).
Having an omnidirectional antenna (i.e. one having the same gain in all directions in a certain plane)
is important because it allows the location of other DW1000 devices to be determined more
accurately.
For specific layout and placement advice for your chosen antenna, follow the guidelines given by the
antenna manufacturer.
270° 90°
UWB
Antenna 180°
X-Y Plane: 0°
270° 90°
Z
Y X
180°
270° 90°
180°
X-Y Plane: 0°
270° 90°
Z
Y X
180°
Antennas for other radio technologies shouldn’t share the UWB antenna area, but should be spatially
isolated from the UWB antenna as much as possible.
UWB
Antenna
RF/
DW1000 BLE
Antenna
Sensors
MCU/BLE TRx
Power
Management
Battery Terminals
5 Power Management
5.1 Switched-Mode Power Supplies
It’s beneficial to use switched-mode power supplies, also known as DCDC converters, as opposed to
LDOs (Low Drop-Out regulators) for power regulation as they offer increased power efficiency and
therefore longer battery life. Greater consideration must be given to the layout of DCDC converters,
however, in order to ensure they operate correctly.
A step-down, or BUCK DCDC converter IC typically requires bulk capacitors at the input and output
aswell as an output power inductor. Current loops are formed at the input and output stages and the
area of these loops must be minimised in order to limit parasitic inductance. Excessive inductance
can compromise the stability of the regulator and generate electromagnetic interference (EMI) due to
the regulator’s switching process, which can propagate to other sensitive circuits on the PCB.
Figure 10 shows a generic DCDC converter circuit. Current loop areas can be minimised by placing
components as close as possible to the regulator IC, with short, wide tracks connecting component
terminals to the IC pins.
Always follow the specific layout guidelines in the regulator vendor’s datasheet.
6 DW1000 Transceiver
6.1 Local Power Supply Routing and Decoupling
The DW1000 has eight power supply pins, each requiring decoupling capacitors which should be
placed as close as possible to the pin. A nominal 3.3 V supply level is required, though the on-chip
LDOs can be supplied with 1.8 V. An external DCDC converter can supply the 1.8 V voltage for
greater power efficiency.
In a PCB layout, the 3.3 V supply can be routed to the DW1000 using either a power plane or power
tracks, with narrower tracks used to route to decoupling caps and pins. The 47 µF bulk cap should be
placed close to the VDDPA pins, though lower-valued capacitors should be placed closest.
The 1.8 V DCDC converter can be supplied with the local 3.3 V supply for the DW1000.
External capacitors are also needed for decoupling the DW1000’s internal LDO regulator outputs.
These are shown on the right hand side of the DW1000 block in Figure 11. VDDDIG and VDDDREG
are outputs of the same internal LDO regulator and they should be connected together on the PCB in
order to minimize impedance between the decoupling capacitors and the internal circuits.
VDDPA1
VDDMS
100 nF
100 nF 330 pF 10 pF
VDDPA2
VDDIF
100 nF
47 µF
100 nF 330 pF 10 pF
VDDBATT VDDSYN
100 nF
VDDCLK
100 nF DW1000 100 nF
VDDIOA
VDDIO
100 nF
100 nF
VDDLNA
VDDIO
100 nF
1.8 V 10 nF
VDDLDOA VDDDIG
100 nF
DCDC
100 nF VDDDREG
VDDLDOD 100 nF
100 nF
Lower capacitor values should be placed closer to the VDDPA pin, so that the return path to the IC is
minimised for higher frequency noise. Since board parasitics create larger impedances at higher
frequencies, minimising the return current path limits noise propagation to other parts of the board.
VDDPA1
10 pF 330 pF 100 nF
Shortest return
current path is for
high-frequency noise
Although VDDPA1 and VDDPA2 pins are located beside each other, each pin should be decoupled
separately. Avoid joining the pads together but rather route the tracks to their decoupling capacitors
so that noise from the pins can be isolated.
6.4 RF Layout
6.4.1 Transmission Lines
The DW1000 has a balanced 100 Ω RF port, to which an external balun can be connected to
transform to a single-ended 50 Ω port for connection to an antenna or RF connector. Therefore, the
PCB layout usually requires 100 Ω differential and 50 Ω single-ended transmission lines.
• Route RF transmission lines on the same layer as the DW1000. Vias in the RF signal path
should be avoided as they create impedance discontinuity and reduce isolation.
• Ensure transmission line impedances are controlled accurately from source to load. The PCB
manufacturer can advise how to implement differential and single-ended transmission lines
for the PCB specification used.
• Ensure there is an unbroken ground path beneath transmission lines so that current paths in
the RF track and ground plane beneath it are of matching lengths. Figure 14 shows an
example of how the return current path could be lengthened by the presence of another track
in the ground layer beneath the RF track.
• Use ample vias at source and load ends of the transmission line to minimise impedance in the
return current path.
• Place vias joining ground planes on adjacent layers around the border of transmission lines to
shield the RF signal. This technique is sometimes called ‘stitching’ or ‘picket fencing’. The
distance between adjacent vias should be small relative to the wavelength (λ) of the highest
frequency signal on the RF trace. The recommended distance is λ/20.
• Remove soldermask above transmission lines. It is difficult to control the uniformity of the
soldermask thickness which can result in impedance variation. Use thin strips of soldermask
at the ends of the transmission line where they connect to component pads to prevent solder
from the pads from spreading over the tracks.
• Keep tracks short to minimise insertion loss, which is increased at UWB frequencies.
• Keep the RF track as straight as possible as bends can introduce impedance discontinuities.
If a bend must be used, make the bend radius as large as possible, as shown in Figure 15.
L2
L3
Return current Elongated return
Bottom from load current path
Reflections from
sharp track edges
The EVB1000 layout is shown in Figure 16 as an example of an optimum layout of the RF path from
DW1000 to antenna. DW1000 RF port pins connect to the DC blocking capacitors through narrow
differential traces. The differential traces between the capacitors and the balun’s balanced port are
implemented as 50 ohm single-ended traces. The trace leading from the balun’s single-ended port is
also 50 ohms. All traces are referenced to ground on the layer immediately beneath the traces.
An external 38.4MHz crystal provides the frequency reference for internal digital and RF phase-locked
loops (PLL). Both PLLs require external loop filter components. Crystal and loop filter tracks must be
isolated from noise so components should be placed close to the relevant DW1000 pins, with
continuous ground on the PCB layer beneath the components.
If placed close to the DW1000, the DCDC converter should be on the opposite side of the IC to the
crystal and PLL loop filter components to avoid switching noise coupling to the sensitive RF circuits,
as illustrated in Figure 17.
Crystal
1.8 V DCDC
Loop filter
components
Figure 18 shows how noise can be coupled to the 3.3 V rail from the PAs during frame transmission.
Due to its power supply ripple rejection capability, the LDO can filter this noise to provide a clean
voltage supply to the TCXO and VDDBATT pin.
3.3V
LDO PA Pulse
Pulse Noise Noise
Removed
DW1000
The DW1000 supports four different SPI modes for compatibility with the host microcontroller’s SPI
polarity and phase specification. GPIO5 and GPIO6, which are set as inputs during device power up,
are used to select the appropriate SPI mode. These GPIOs have internal pull-down resistors and so
the default is SPI mode 0. Pull-up resistors can be used to select SPI modes 1 – 3, as shown in
Figure 19.
10 kΩ
GPIO5
33
~55 kΩ 10 kΩ
VDDIO
31
DW1000 GPIO6
30
~55 kΩ
The interrupt request (IRQ/GPIO8) pin can be used to signal specific events to the host
microcontroller to trigger interrupts. When the DW1000 is in SLEEP or DEEPSLEEP states, the IRQ
pin will be floating. An external pull-down resistor is therefore required to ensure that spurious
interrupts aren’t signalled to the microcontroller.
More information on interrupt events and IRQ/GPIO8 pin configuration can be found in the DW1000
datasheet [1] and DW1000 user manual [2].
100 kΩ
45
GPIO8
IRQ /
(GPIO)
DW1000 MCU
The active-low, DW1000 reset (RSTn) pin is held low internally during power-up but can also be used
to reset the DW1000 by pulling the pin low. The pin must not be driven high externally. Figure 21
shows a suitable solution where the microcontroller’s GPIO pin is configured as open-drain, so that
RSTn can be pulled low but not driven high.
DW1000 MCU
(GPIO)
RSTn 27
Open-Drain
configuration
7 RF Connectors
7.1 Surface-Mount Connectors
An RF connector of some kind may be needed in the RF path in order to connect the device to test
equipment for production testing.
Surface-mount connectors with the ability to switch the RF signal path from the antenna trace to the
plug adapter are recommended as it is important that the stub formed from the antenna and feed
trace are removed from the measurement. To ensure an accurate impedance match between the
board and the adapter, there must be a low-impedance path between the board’s ground plane and
the adapter cable’s ground shield. Place many vias in, or as close as possible to, the connector
ground pads, as shown in Figure 22.
Antenna
SMT
connector
Some suggested coaxial switch connectors are listed in the following table.
Many vias should be used within or close to the SMA connector ground pads. Since an edge-mounted
SMA connector attaches to top and bottom PCB layers, through-hole vias should be used to reduce
the impedance to current flowing from the connector’s ground connection on the bottom layer.
Match track and connector pad widths in order to avoid impedance discontinuity, as discussed in
section 3.2.
RF Signal Path
Connector
makes stub
RF Signal Path
The RF track may need to be cut in order to attach the inner conductor of the adapter. The length of
exposed inner conductor should be minimised. Soldermask on the top layer of the PCB should be
removed so that the copper shield of the adapter can be soldered to the board. The shield of the
adapter should be soldered to the board as close as possible to the point where the inner conductor
of the adapter is soldered to the RF track. Connections should be made to ground on either side of
the RF track. By following these guidelines, the transmission line impedance from PCB to adapter can
be kept as consistent as possible.
Ground soldered
close to inner
conductor
connection
Exposed inner
conductor kept
short
8 Antennas
8.1 Overview
In contrast with narrowband radio systems, antennas for UWB RTLS applications need to meet
additional performance specifications, such as fidelity factor and group delay.
Close proximity to objects with low RF-transparency can degrade antenna performance, reducing
efficiency and altering radiation patterns. WB001 is designed for use in products such as body-worn
tags. It is a linearly-polarised monopole antenna with a ground shorting via feature designed to have
good gain across UWB channels in the 3.5 to 7 GHz frequency range. It is a planar antenna which
can be implemented in copper as part of the PCB layout.
A design document, including gerber files, can be found in the downloadable WB001 package at
www.decawave.com.
8.2.2 WB002
WB002 is the antenna provided in Decawave EVK1000 and TREK1000 development kits and is a
good antenna for use in free-space scenarios. It is a linearly-polarised monopole antenna designed to
have good gain across UWB channels in the 3 to 8 GHz frequency range. It is a planar antenna which
can be implemented in copper as part of the PCB layout.
A design document, including gerber files, can be found in the downloadable WB002 package at
www.decawave.com.
9 Electromagnetic Interference
9.1 Overview
It is intended that any electromagnetic radiation from a product with a radio should be from the
product’s antenna. In reality, however, it is found that unintentional radiation commonly occurs from
structures within the product other than the radio system’s antenna. Electromagnetic interference
(EMI) is the name given to this kind of unintentional radiation as it can interfere with the radio signal
transmitted from the antenna.
There are techniques which can be used to limit EMI originating from both the PCB and the other
structures within an assembled product.
An illustration of the positioning of ground stitching vias on a PCB is shown in Figure 27. The distance
between adjacent vias should be small relative to the wavelength (λ) of the highest frequency signal
on the PCB. The recommended distance is λ/20 or less.
Ground stitching
vias around
perimeter of PCB
There are, however, some circumstances in which placing a shield can over the DW1000 circuit block
may be necessary. Here are some examples.
• If the product uses another radio technology (e.g. BLE, WiFi, cellular, etc.) which can transmit
when the UWB receiver is active, then UWB desensitisation due to blocking may occur.
• If noisy power supplies and digital signals are placed near the DW1000’s sensitive RF
circuits.
• If there are other sensitive circuit blocks on the PCB that could suffer from noise generated in
the DW1000’s digital circuits.
The fence of the shield can should have a section removed to form a “mousehole” where the RF track
emerges, so that the impedance of the RF track isn’t altered by the close proximity of the grounded
shield can fence. Guideline dimensions of the mousehole would be a width equal to three times the
RF track width and height equal to four times the substrate height between the track and its reference
ground layer in the PCB.
Through-hole vias should be used to stitch ground copper in the layers of the PCB around the
perimeter of the shield can. This improves shielding of noise which could propagate through the PCB.
It also minimises impedance between shield can and ground plane, preventing shield can itself from
radiating noise.
Bottom
Layer
50 Ω trace leading
to UWB antenna
Ground stitching
vias around border
of shield can
RF currents on signals and ground planes in the PCB can couple to signals routed on wires and
battery leads. These conductors are often unshielded and so they can act as antennas, radiating EMI
unintentionally from the product, as illustrated in Figure 29.
UWB
antenna Top
Co
ver
Cover
Bottom
Wires can
act as
antennas
EMI can combine constructively or destructively with the energy transmitted from the UWB antenna to
create a distorted UWB transmit spectrum. Figure 30 illustrates a scenario where the transmit
spectrum of a UWB product is being measured. With the EMI source facing the measuring antenna,
the spectrum is distorted, with a peak in power where the EMI constructively interferes with the signal
from the product’s antenna. When the product is in a position where the EMI source is facing away
from the measuring antenna, the EMI is much weaker and the measured power is well below the
regulatory limit. The product’s power must be set lower to allow for the peak seen due to the EMI
source. This demonstrates how EMI can lead to reduced communication range aswell as ranging
inaccuracies associated with varying power being transmitted in a 360° plane around the product.
Measuring Power
antenna
-41.3
dBm/MHz
Frequency
Unintentional radiation can
distort measured UWB spectrum
Measuring Power
antenna
-41.3
dBm/MHz
Frequency
Lower power measured with
weak unintentional radiation
Follow these guidelines for limiting EMI from wire and battery PCB interfaces.
• Keep wires as short as possible. This will limit their ability to radiate EMI.
• Try to position wires so that they run close to the surface of the PCB ground plane. EMI
radiating from the wires can be reduced through coupling to the ground plane.
• Try placing ferrites or decoupling capacitors to decouple noise on the PCB at the wire
interface connection. This will filter noise before reaching the wires.
• Electromagnetic absorber sheet material or EMI cloth can be positioned on wires so that
noise can be absorbed rather than radiated.
10 References
10.1 Listing
Reference is made to the following documents in the course of this Application Note: -
11 Document History
Table 4. Document History
12 Major Changes
Revision 1.0
Revision 1.1
Revision 1.2
13 FURTHER INFORMATION
Decawave develops semiconductors solutions, software, modules, reference designs - that enable
real-time, ultra-accurate, ultra-reliable local area micro-location services. Decawave’s technology
enables an entirely new class of easy to implement, highly secure, intelligent location functionality and
services for IoT and smart consumer products and applications.
For further information on this or any other Decawave product, please refer to our website
www.decawave.com.
Figure 31 illustrates an example 6-layer PCB stack-up where a high component density is possible for
several reasons.
• With 6 layers in the stack-up, there is enough routing space for ICs to be placed opposite
each other on top and bottom sides of the PCB.
• In addition to plated through-hole vias which are drilled through all 6 layers, the use of blind
microvias between the top and bottom two layers greatly eases escape routing.
• Using via-in-pad technology, where the via can be placed within component pads as opposed
to adjacent to the pad, offers board space savings. As no soldermask is applied over
component pads, vias need to be filled with epoxy or copper to avoid air entrapment and
outgassing during assembly, adding additional cost.
DW1000
Layer 3 (Signal)
Layer 4 (Power)
Layer 5 (Ground)
Bottom Layer (Signal)
IC
Figure 31. High Component Density with 6 PCB Layers and Microvias
Note: In order to maintain the correct impedances of the RF tracks, the PCB stack up shown in
section 3.3 should be used. However, customers should consult their PCB manufacturer to fine tune
impedances. During PCB manufacture, impedance control techniques should be employed to ensure
that the RF tracks have the correct impedance. This is required because of the variability of laminate
parameters with standard FR4 material.
Description: This file is an image of the DW1000 section of Decawave’s EVB1000 board for
reference.
Filename: DW1000_IC_PCB_TopCopperOnly.dxf
Description: This file shows how the topside tracks and ground plane are constructed on the
DW1000 section of the EVB1000 PCB. This is the main file of interest.
Filename: DW1000_IC_PCB_TopResistOnly.dxf
Description: This file shows how the top side solder resist (mask) is applied to the DW1000 section
of the EVB1000 PCB. Note: We do not recommend applying solder resist on the RF traces. This
helps ensure that the correct RF impedance is maintained. In order to stop solder flowing onto these
tracks during the solder reflow process, slivers of resist as shown are used.
Filename: DW1000_IC_PCB_TopSilkscreenOnly.dxf
Description: This file shows the top side silk screen of the DW1000 section of EVB1000 for
reference.