EE3302 - DLC 2 Marks With Answers
EE3302 - DLC 2 Marks With Answers
7) Reduce A (A + B)
A (A + B) = AA + AB= A (1 + B) [1 + B = 1]= A.
15) Find the complement of the functions F1 = x'yz' + x'y'z and F2 = x (y'z' + yz).
By applying De-Morgan's theorem.
F1' = (x'yz' + x'y'z)' = (x'yz')'(x'y'z)' = (x + y' + z)(x + y +z')
F2' = [x (y'z' + yz)]' = x' + (y'z' + yz)'
= x' + (y'z')'(yz)'
7) Define Decoder.
A decoder is a multiple - input multiple output logic circuit that converts coded inputs into
coded outputs where the input and output codes are different.
9) Define Encoder.
An encoder has 2n input lines and n output lines. In encoder the output lines generate the
binary code corresponding to the input value.
14) Write down the steps in implementing a Boolean function with levels of NAND Gates.
Simplify the function and express it in sum of products.
Draw a NAND gate for each product term of the expression that has at least two
Literals.
The inputs to each NAND gate are the literals of the term.
This constitutes a group of first level gates.
Draw a single gate using the AND-invert or the invert- OR graphic symbol in the
second level, with inputs coming from outputs of first level gates.
A term with a single literal requires an inverter in the first level. How ever if the
single literal is complemented, it can be connected directly to an input of the
second level NAND gate.
15) Give the general procedure for converting a Boolean expression in to multilevel NAND
diagram?
Draw the AND-OR diagram of the Boolean expression.
Convert all AND gates to NAND gates with AND-invert graphic symbols.
Convert all OR gates to NAND gates with invert-OR graphic symbols.
Check all the bubbles in the same diagram. For every bubble that is not compensated by
another circle along the same line, insert an inverter or complement the input literal.
UNIT-III
SYNCHRONOUS SEQUENTIAL CIRCUITS
In sequential circuits the output variables dependent not only on the present input
variables but they also depend up on the past history of these input variables.
17. Give the comparison between combinational circuits and sequential circuits.
Combinational circuits Sequential circuits Memory unit is not required Memory unity is
Required Parallel adder is a combinational circuit Serial adder is a sequential circuit.
23. Give the comparison between synchronous & Asynchronous sequential circuits?
Synchronous sequential circuits Asynchronous sequential circuits. Memory elements are
locked flip-flops Memory elements are either unlocked flip - flops or time delay elements.
UNIT-IV
ASYNCHRONOUS SEQUENTIAL CIRCUITS AND PROGRAMMABLE LOGIC
DEVICES
1. Explain ROM.
A read only memory (ROM) is a device that includes both the decoder and the OR gates
within a single IC package. It consists of n input lines and m output lines. Each bit Combination
of the input variables is called an address. Each bit combination that comes out of the output lines
is called a word. The number of distinct addresses possible with n input variables is 2n.
3. Explain PROM.
PROM (Programmable Read Only Memory) it allows user to store data or program.
PROMs use the fuses with materiallike nichrome and polycrystalline. The user can blow these
fuses by passing around 20 to 50 mA of current for the period 5 to 20μs.The blowing of fuses is
called programming of ROM. The PROMs are one time programmable. Once programmed, the
information is stored permanent.
4. Explain EPROM.
EPROM (Erasable Programmable Read Only Memory) EPROM use MOS circuitry. They
store 1’s and 0’s as a packet of charge in a buried layer of the IC chip. We can erase the stored
data in the EPROMs by exposing the chip to ultraviolet light via its quartz window for 15 to 20
minutes. It is not possible to erase selective information. The chip can be reprogrammed.
5. Explain EEPROM.
EEPROM (Electrically Erasable Programmable Read Only Memory). EEPROM also use
MOS circuitry. Data is stored as charge or no charge on an insulated layer or an insulated floating
gate in the device. EEPROM allows selective erasing at the register level rather than erasing all
the information since the information can be changed by using electrical signals.
GAL is Generic Array Logic. GAL consists of a programmable AND array and a fixed
OR array with output logic.
19. Why the input variables to a PAL are buffered
The input variables to a PAL are buffered to prevent loading by the large number of AND
gate inputs to which available or its complement can be connected.
UNIT-V
VHDL
1. What is Verilog?
Verilog is a general purpose hardware descriptor language. It is similar in syntax to the C
programming language. It can be used to model a digital system at many levels of abstraction
anging from the algorithmic level to the switch level.