Hindawi

VLSI Design
Volume 2018, Article ID 4804729, 8 pages
https://doi.org/10.1155/2018/4804729

Research Article
Crypto-Stego-Real-Time (CSRT) System for
Secure Reversible Data Hiding

Latika Desai and Suresh Mali

Dr. D. Y. Patil Institute of Technology, Savitribai Phule Pune University, Pune, India

Correspondence should be addressed to Latika Desai; [email protected]

Received 17 May 2018; Revised 16 August 2018; Accepted 1 September 2018; Published 27 September 2018

Academic Editor: Maurizio Martina

Copyright © 2018 Latika Desai and Suresh Mali. This is an open access article distributed under the Creative Commons Attribution
License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Due to demand of information transfer through higher speed wireless communication network, it is time to think about security
of important information to be transferred. Further, as these communication networks are part of open channel, to preserve
the security of any Critical Information (CI) is really a challenging task in any real-time application. Data hiding techniques
give more security and robustness of important CI against encryption or cryptographic software solutions. However, hardwired
approach exhibits better solution not only in terms of reduction of complexity but also in terms of adaptive real-time output. This
paper demonstrates frequency, Discrete Cosine Transform (DCT) domain Steganographic data hiding hardware solution for secret
communication called Crypto-Stego-Real-Time (CSRT) System. The challenge is to design a secure algorithm keeping reliability of
minimum distortion of original cover signal while embedding considerable amount of CI. Field Programmable Gate Array (FPGA)
implementation shown in this paper is more secure, robust, and fast. Pipelining process while embedding enhances the speed of
embedding, optimizes the memory utilization, and gives better Peak Signal to Noise Ratio (PSNR) and high robustness. Practically
implemented hardware Steganographic solutions shown in this paper also give better performance than that of the current state-
of-the-art hardware implementations.

1. Introduction Therefore these techniques are not suitable for real-time

applications such as ATM where uploading authentication cre-
In the today’s Internet era, there is a need of protection of dentials (as CI) through Internet is always essential. Authen-
Critical Information (CI) like Personal Identification Num- ticating mobile wallets, online Stock trading, and many more
ber (PIN) of Automated Teller Machine (ATM) card, One real-time e-transactions applications are to be supported by
Time Password (OTP), bank transactions, etc. while com- cryptographic and steganographic security systems.
municating CI in open channel system (internet). To avoid Researchers are constantly trying to improve the capa-
unauthorized access, one can encrypt CI itself before it actu- bilities of reversible Steganographic data hiding methodolo-
ally gets transferred from one location to another. However,
gies in terms of parameters such as embedding capacity,
such encrypted CI is still specifically available to any hacker
and will be in a position to extract CI. Therefore, to make imperceptibility, security, time complexity, and robustness.
highest security of CI, Steganographic data hiding techniques Implementation of embedding function (fEm ) and extraction
are used to keep the communication of CI itself hidden from function (fEx ) may be in either software or hardware platform.
the hacker. Many such techniques have been proposed earlier, Hardware implementation has always offered advantages
which comes under two categories, namely, spatial domain over software realization [1] in terms of low execution
and frequency domain. Most of the researchers are focused time, low power consumption, high reliability, and real-
on the software-data hiding through different approaches time performance. Implemented hardware can also be made
like Least Significant Bit (LSB), 2/3 LSB, n-bit LSB, DCT, compatible with existing consumer electronics communicat-
and Discrete Wavelet Transform (DWT). Unfortunately, soft- ing devices. Table 1 also narrates many more advantages of
ware-data hiding techniques are generic, complex, and slow. hardware approaches by [1–3].
 3979, 2018, 1, Downloaded from https://onlinelibrary.wiley.com/doi/10.1155/2018/4804729, Wiley Online Library on [20/10/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
2 VLSI Design

Table 1: Hardware versus software based implementation of data security.

Software Implementation Hardware Implementation

Generalized design under PC environment Customized designed using FPGAs (ES)
Complex Algorithms can be possible Simplified Algorithms with hardware
Not a Real time solution Real time solution with hardware
More power requires for PC Less power required for embedded system
Easy to modify the design Difficult to modify the design
More area & cannot execute without PC. Less area & can execute without PC.
Not Portable Portable
The Cost of PC, OS and language support Low-cost due to specific hardware involved
Less secured More secured
Easy to copy the implemented code. Difficult to copy the implemented hardware.
All operations are sequential Parallel operations are possible

2. Overview of Reversible Data of the algorithm implemented in an FPGA-based hardware by

Hiding Techniques Mohd et al. [10] has been examined with respect to resource
utilization, timing, and energy. Because of higher complex
Reconfigurable hardware architecture supports algorithm computation, the implementation has a higher cost and slow-
change and multiple keys, as well as different CI size. It speeds er speed.
up the process of embedding due to availability of cache The spatial domain hardware approach has also been
memory. Multiprocessor System on Chip (MPSoC) architec- introduced by Mahmoudpour and Mirzakuchaki et al. [11]
tures demonstrated by Maity et al. [4] exhibits high intrusion through randomizations using Linear Feedback Shift Register
protection. It gives real-time transmission using channel (LFSR) for getting better security against attack. However, the
coding and biphase modulation. However, the computation maximum value of PSNR in this approach is 51.217. Hard-
requirement for embedding is quite high. The Adaptive Ran- ware platform has also been used by Rajagopala et al. [12].
dom Inverted Key (ARIK) LSB substitution method proposed However, being a spatial domain embedding approach, it
by Balakrishnan et al. [5] using cyclone II FPGA board has is less secure and non robust even if PSNR is up to 60.98.
improved performance with respect to imperceptibility of Reversible Steganography spatial domain implemented using
Stego. However, the designed architecture was operated at LFSR has been demonstrated by Mahmood et al. [13]. The
a frequency of 50 MHz, occupies 10513 logic elements, and different LFSR and seeds are preferred for better security.
consumes 92 mw of power at the embedding stage. Effective However, complex logic consumes more hardware and the
integration of conventional cryptography, encryption, and Ste- maximum value of PSNR is 51.21 for even 10% of the pay load
ganography has been presented by Mali et al. [6] using Adap- of embedding.
tive Energy Thresholding (AET) technique. The approach The reversible data hiding implementation proposed by
enhances the parameters security, robustness, and payload Sundararaman et al. [14] is the spatial domain approach with
against different attacks. Being implemented in software, LFSR. Five different polynomials are used for five different
the approach cannot be applied in real-time environment. covers with different sizes. Because of the limited use of
Gomez-Hernandez et al. [7] worked on context techniques bitwise Steganographic operation, this hardware approach
used for embedding, where the loss of information during is less secure. The demonstrated approach has maximum
recovery process has been avoided using simple and repetitive PSNR 51.27. Also, Synthesis report states that for 64 x 64 size
operations with context technique. However, the perfor- cover LEs used are 11493. Intermediate Significant Bit (ISB)
mance would have been better with parallelism in terms of replacement technique demonstrated by Shabir et al. [15]
area and time. suggests a fix location for embedding. Although it provides
Mohd et al. [8] demonstrate the FPGA hardware imple- capacity up to 25%, the maximum PSNR achieved due to ISB
mentation in spatial domain Steganography. Simulation, syn- process is 37.97. The transform domain DCT based approach
thesis, and analysis show that random embedding increases for data hiding implemented in MATLAB by Rahman et al.
utilization of LEs. However, spatial domain techniques are [16] uses sequential embedding of secret bits in the LSBs of
always more vulnerable than that of frequency domain tech- DCT coefficients. The experimental results show that the use
niques. Adaptive randomization in reconfigurable hardware of middle frequency DCT coefficients has given better results
architecture using Integer Wavelet Transform (IWT) has of PSNR as compared to low frequency DCT coefficients.
been proposed by Ramalingam et al. [9]. Although it gives However, being a software implementation, it is not suitable
PSNR up to 60, the design consumed 34% of the LEs, 22% for real-time applications.
of the dedicated logic register, and 2% of the embedded Anderson and Petitcolas [17] show that considerations of
multiplier on FPGA. The main drawback of the IWT based entropy give us better results as it gives us some quantitative
data hiding is the computational overhead. The performance leverage. The embedding of information is in parity checks
 3979, 2018, 1, Downloaded from https://onlinelibrary.wiley.com/doi/10.1155/2018/4804729, Wiley Online Library on [20/10/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
VLSI Design 3

Table 2: Analysis of various data hiding techniques.

Approach Imperceptibility Capacity Robustness Time Complexity

Spatial Domain[31] Medium High Low Low
Frequency Domain[] High Low High Low
Spread Spectrum [33] High High Medium High
Matrix Embedding [34] High High Low Medium
Difference Expansion[35] High High Low Low
Optimization Technique [36] High Medium High High
Histogram Modification [37] High Medium Low Low

rather than in the data directly. This approach gives improved Analysis of the state-of-the-art techniques leads to some
efficiency and also allows us to do public key Steganography. interesting findings: frequency domain gives high robustness
The Steganography approach introduced by Odeh et al. [18] and high imperceptibility. However, these techniques are very
is a real-time hardware engine, where text is embedded. By complex and time consuming while being implemented in
taking care of a real-time application proposed work is hardware. Further, data hiding Capacity, Security, and Ro-
faster to maintain security in communication over Internet. bustness parameters are mutually exclusive to each other and
However, because of lack of parallel processing, the speed of therefore optimizing them in real-time hardware environ-
embedding is low. If we consider different applications like ment is really a tough task. The support of parallel processing
covert communication, fingerprinting, and copyright protec- helps in compensating for the time needed for such complex
tion as well as many more, the most important parameters computations.
observed are the security, robustness, invisibility, time com-
plexity, and area and power dissipation. Among all these 3. Proposed Methodology
parameters security is the major aspect and is commonly used
in all these different applications announced by Fedrich [19]. Any non-Critical Information called cover data (C) acts as a
The FPGA-based microarchitecture defined by Farouk et carrier of Critical Information (CI). A Secrete Key (K) is used
al. [20] with the secret key feature is suitable for real-time by the Steganographic embedding function (fEm ) to hide CI
application. Selecting the hiding bits in a pseudorandom and gives Stego data (S) as an output (device at Transmitting
manner as a function of a secret key has been used to increase end DT ) as shown in
obscurity. The receiver needs only the modulated cover and
the secret key to recover the message, i.e., no original cover is 𝐷𝑇
𝑆 󳨀󳨀→ 𝑓𝐸𝑚 (𝐶, 𝐶𝐼, 𝐾) (1)
required.
The importance of DCT in terms of scalability and mini- where S is Stego data, C is cover data, CI is Critical Informa-
mal distortion demonstrated by Cariccia et al. [21] as well as tion, and K is Secrete Key.
Renda et al. [22] is quite noticeable. Because of the ability The same Secrete Key (K) is used by the Steganographic
of DCT algorithms to produce high throughput, low power extraction function (fEx ) to extract CI󸀠 (as a device at
dissipation, and reduced chip area with primary objective of receiving end DR ) as shown in
security, they are more popular amongst the researchers.
𝐷𝑅
Cryptographic different approaches are demonstrated 𝐶𝐼󸀠 󳨀󳨀→ 𝑓𝐸𝑥 (𝑆, 𝐾) (2)
through [23–29] using Virtex 5 FPGA platform. While secur-
ing the data, with AES (Advanced Encryption Standard) as where S is Stego data, CI󸀠 is Extracted Critical Information,
well as Data Decryption Systems Standard (DES) and Triple and K is Secrete Key.
DES (TDES) using FPGA, different approaches are imple- Typical generalized hardware Steganographic data hiding
mented to enhance the performance for secure communica- mechanism is as shown in Figure 1.
tion. However, the area utilization is varying from 260 LEs Proposed hardware based reversible data hiding system to
to 9276 LEs. Watermarking method using DWT [30] with implement data hiding system consists of both cryptographic
344.329 MHz frequency has also shown considerably less and Steganographic approach and therefore is called Crypto-
area utilized with more delays in the process of embedding. Stego-Real-Time (CSRT) System. Figure 2 outlines the pro-
Comparison of software and hardware implementation of posed methodology.
such systems is given in Table 1. This table shows that the As a part of cryptography, the encryption process is
hardware deployment gives more speed, the secrecy, and converting CI from plain text into unintelligible ciphertext.
the robustness with minimum cost as compared to software On the receiving side of the process, decryption is used to
counterpart. Brief analysis of various techniques [31–37] to convert this unintelligible ciphertext back into plaintext CI󸀠
develop such systems is given in Table 2. The frequency as an extracted CI. If CI consists of M “Characters” in CI,
domain techniques demonstrated in [32–37] as well as [21, stored in the Message Cache, it can be represented as
22] show better performance in terms of imperceptibility,
capacity, robustness, and process. 𝐶𝐼 = [𝑋0 , 𝑋1 , 𝑋2 , . . . , 𝑋𝑀−1 , ] (3)
 3979, 2018, 1, Downloaded from https://onlinelibrary.wiley.com/doi/10.1155/2018/4804729, Wiley Online Library on [20/10/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
4 VLSI Design

Secret Key (K) Secret Key (K)

Stego Data
(S)
Cover Data (C) Extracted
fEm
E fE
Ex Critical
Critical
Information (CI’)
Information (CI)

Unintentional
Attacks(A) or
Intentional
Device at Trapping Device at
Transmitting end (DT ) By Hacker (H) Receiving end (DR )

Figure 1: Steganographic data hiding mechanism.

Sharing of Common Key (K)

Embedding Extraction
Steganography

Steganography
(f Em) (f Ex)
C

S
CI Encryption Decryption CI’

Non-Suspicious Reducing the

Hacker Chance of Suspect

Figure 2: Proposed Crypto-Stego-Real-Time (CSRT) System.

where M is number of characters in CI stored in “Message The format of content of Li while selecting the character
Cache” at ‘A0 to AM−1 address locations in a sequence. and specific bit of the character is as shown in Figure 3. As
The process of encryption typically carried out using there are 8 bits in each character, the randomization is also
“Randomly Selected Set of Addresses” stored in a “LOOK- applicable to these bits.
UP Table” is randomly selecting any address location (Am ) The proposed algorithm works on 8 bytes of cover at a
of Message Cache and hence, at any given time, one of the time as follows:
characters stored in Message Cache get selected as “Ym ”
and can be written as follows: there is a “LOOK-UP Table” 𝐶 = [𝐵7 , 𝐵6 , 𝐵5 , . . . , 𝐵0 ] (6)
consisting of random numbers which eventually act as an
addresses to locate any random character at “Message Cache”. where B7 to B0 = 8 bytes of the cover given to CSRT at any
Obviously, the number of locations in “LOOK-UP Table” is 8 given time whose DCT can be written as
times more than that of the number of locations in “Message
Cache”, i.e., 8∗M. At any given time, one of the characters 𝐷 = 𝐷𝐶𝑇 (𝐶) (7)
stored in “Message Cache” gets selected as “Randomly Selected
where D is A set of 8 DCT coefficients of 8 respective bytes of
Character” given by
the cover given in (6) which can also be written as
𝑌𝑚 = [𝐴 𝑚 ] = [[𝐿 𝑖 ]] = [[𝐶𝑛𝑡]] (4)
𝐷 = 𝐶7 , 𝐶6 , 𝐶5 , . . . , 𝐶0 (8)
where Ym is Randomly Selected Character and Am is Ran-
domly Selected Address for “Message Cache” and eventually where every DCT coefficient (C) consists of signed binary
content of sequential location of “LOOK-UP Table” 0 to M-1 representation. The bit selected (shown in Figure 3) is embed-
excluding three “Least Significant Bits” of content of Li . ded in C3 . Embedding of the bit in C3 is nothing but making
The “Clock Generator” of CSRT selects sequential loca- LSB of C3 as that of bit to be embedded as
tions of “LOOK-UP Table” and is given as
𝐿 𝑖 = 𝐶𝑛𝑡 (5) LSB of 𝐶3 = Selected Bit of 𝑌𝑚
(9)
where Cnt is output of the COUNTER. = Selected Bit of [[𝐿 𝑖 ]]
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VLSI Design 5

Selected BIT
Random ‘BIT’Selection’ for Embedding

CLOCK MUX
LOOK-UP
Table Message
‘8 M’ Cache
COUNTER
Locations ‘M’
Ym
Bytes
Address
For
LOOK-UP

Random ‘Character Selection’

Figure 3: Randomization of characters and bits of “Message Cache”.

After modifying the LSB of C3 inverse DCT (IDCT) of D is (CI󸀠 ) the Stego data (S) sent from the PC to FPGA board on
taken to get Stego as follows: byte by byte basis and the extracted CI’ stored in FPGA RAM
at Message Cache is validated by receiving it on PC.
𝑆 = 𝐼𝐷𝐶𝑇 (𝐷) (10)

where is S is the Stego block of data consisting of 8 bytes 6. Result and Discussion
having an embedded bit of information in LSB of C3 .
This section declares the analysis of different parameters like
PSNR, area, and the time. The different methodologies are
4. Embedding Algorithm explained in the literature such as LSB, MSB, DWT, IWT,
and proposed approach [CSRT]. The PSNR values are shown
(1) Accept CI into Message Cache
through Figure 5. The proposed hardware approach gives
(2) Accept LOOK-UP Table as an Embedding Key (K) 73.77 dB PSNR value which is approximately 10% more than
(3) Accept 8-byte cover data (C) mentioned approaches.
The analysis of the proposed hardware approach for
(4) Compute DCT of 8 bytes of cover data
the area in terms of Slice Registers, Slice Look-Up-Tables
(5) Randomly select byte (Ym ) from Message Cache (LUTs), and slice LUT-FF pair used in various approaches is
(6) Select a bit using 3 LSBs of contents of selected byte demonstrated through Figures 6, 7, and 8 respectively. The
LOOK-UP Table proposed CSRT method uses only 241 Slice Registers and 1202
LUTs.
(7) Embed the selected bit at DCT coefficient C3
To understand the performance, speed of execution of
(8) Compute IDCT of 8 bytes of cover data to get Stego algorithm of embedding of CI has been considered. This time
data varies from 84.48 𝜇s to 1351.68 𝜇s while embedding of CI
(9) Repeat Step-3 to Step-8 for all the bits of all the from 128 bytes to 2 K bytes in 1K bytes to 16 K bytes of cover
characters Message Cache data; Figure 9 gives an idea of reduction of processing speed
of the proposed CSRT method.
(10) Stop.
Security of the system is very high as the cryptographic
Although there are multiple steps in the proposed algorithm, Encryption and Steganographic data hiding processes has
it is possible to have parallel processing of Step-(3) to Step-8. been developed in FPGA hardware. Although hidden data
If we take Pre Em = Step-(3) and Step-(4), Emd = Step-(5) and are reversible and can be recovered by the intended user, it
Step-(6) and Post-Em = Step-(7) and Step-(8), it is possible to should not be detectable by any hacker (most of the hackers
reduce the total time required for embedding all the bits of are nonsuspicious) as shown in Figure 2. The sharing of a
Message Cache as shown in Figure 4. common key is important for the intended extractor. This
key may be predecided from look up table which eventually
5. Experimental Set Up randomly select the bits of the characters from message cache
for embedding. A person who knows the algorithm and look-
The logic necessary to implement the algorithm is down- up table must be the person who will be able to extract the
loaded from the PC to Configurable FPGA board using Critical Information (CI). For example, for 128 bytes of CI,
Virtex-5, XC5VLX50T, FFG1136C Board. Critical Informa- there will be 1 K bytes of look-up table and the attacker has to
tion (CI) and Embedding Key (K) are transferred to the FPGA try 21024 and check permutations and combinations of look-
RAM at Message Cache and LOOK-UP Table, respectively. The up table provided that the embedder knows the algorithm. As
cover data (C) is then transferred on byte by byte basis. After CI increases, the size of the look-up table also increases, and
the embedding process, it gets validated by transferring Stego hence the permutations and combinations of look-up table.
data (S) back to PC. While extracting the Critical Information Although this dependability is the drawback of the system,
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6 VLSI Design

T
Pre_Em Emd Post_Em
Pre_Em Emd Post_Em
Pre_Em Emd Post_Em
Pre_Em Emd Post_Em

Figure 4: Parallel processing of steps of CSRT algorithm.

PSNR
80 73.77
70 63.18
60.9
60
51.2
50 43.6
PSNR

40
30
20
10
0
1 [10] LSB[8]
DWT 2 3
MSB[12] 4
IWT[9] 5
DCT[CSRT]

Figure 5: PSNR with different hardware approaches.

Slice Register Used

2500
2056
Slice Register Used

2000
1500
1206 1105
1000 808
500 399
255 241
0
1
[23] 2
[24] 3
[25] 4
[26] 5
[28] 6 [CSRT]
[29] 7

Figure 6: Slice registers used with different approaches.

Number of Slice LUTs Used

10000 9276
Number of Slice LUTs used

9000
8000
7000
6000
5000 4721
4000 3788 3557
3000
2000 1338 1692
1202
1000
0
1
[23] 2
[24] 3
[25] 4
[26] 5
[28] 6 [CSRT]
[29] 7

Figure 7: Number of slice LUTs used with different approaches.

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VLSI Design 7

Number of Fully used LUT-FF Pairs

2000
1792
1800

Fully used LUT-FF Pairs

1600
1400
1200
1000
800 748
632 660
600
400 260 236
200 161
0
1
[23] 2
[24] 3
[25] 4
[26] 5
[28] 6 [CSRT]
[29] 7

Figure 8: Fully used slice LUT-FF pairs with different approaches.

1600
1400
Processing Time (s)

1351.68
1200
1000
800
675.84
600
400 337.92
200 168.96
84.48
0
1
128 2
256 3
512 4
1024 5
2048
Critical Information (Message Bits)

Figure 9: Critical Information (CI) processing time.

the system is reconfigurable and, therefore, one can design Conflicts of Interest
the look-up table of any size based on size of the CI.
The authors declare that they have no conflicts of interest.

7. Conclusion
Acknowledgments
The Crypto-Stego-Real-Time (CSRT) System presented in
We are thankful to Dr. D. Y. Patil Institute of Technology,
this paper is highly secured due to its implementation in
Pimpri, Pune, for encouragement and support.
hardware. As the encryption of CI has been done in the hard-
ware using cache memory, the random addresses of cache
memory are used for scribbling CI to be embedded in the References
cover bit by bit fashion. One cannot extract CI unless he/she
knows the algorithm and look-up table as a key of embedding. [1] S. Debnath, M. Kalita, and S. Majumder, “A Review on Hard-
ware Implementation of Steganography,” in Proceedings of the
Pipelining process while embedding enhances the speed
Devices for Integrated Circuit, pp. 149–152, Kalyani, India, March
of embedding and optimizes the memory utilization. The 2017.
system PSNR (73.77), Number of Slice LUTs used (1202), [2] M. Faheem, S. Jamel, A. Hassan, Z. A., N. Shafinaz, and M. Mat,
and execution time (1351.68 𝜇S for 2 K bits of CI) show an “A Survey on the cryptographic encryption algorithms,” Inter-
evidence of better performance in terms of throughput of national Journal of Advanced Computer Science and Applica-
the system. The drawback of the system is its Embedding tions, vol. 8, no. 11, pp. 333–344, 2017.
Key which varies with CI. As CI increases, the size of the [3] https://www.infosecurity-magazine.com/magazine-features/
key also increases. However, the system is reconfigurable tales-crypt-hardware-software/.
and, therefore, one can design the look-up table of any size [4] S. P. Maity and M. K. Kundu, “Distortion free image-in-image
based on the size of the CI. The overall performance of the communication with implementation in FPGA,” Elsevier Inter-
presented CSRT system is better than current state-of-the-art national Journal of Electronics and Communications, vol. 67, pp.
methods and, therefore, it is most suitable for any real-time 438–447, 2012.
applications. [5] R. Balakrishnan, A. Rengarajan, and J. B. B. Rayappan, “Multi-
plexed stego path on reconfigurable hardware: a novel random
approach,” Elsevier Computers and Electrical Engineering, vol.
Data Availability 55, pp. 153–163, 2016.
[6] S. N. Mali, P. M. Patil, and R. M. Jalnekar, “Robust and secured
The data used to support the findings of this study are avail- image-adaptive data hiding,” Digital Signal Processing, vol. 22,
able from the corresponding author upon request. no. 2, pp. 314–323, 2012.
 3979, 2018, 1, Downloaded from https://onlinelibrary.wiley.com/doi/10.1155/2018/4804729, Wiley Online Library on [20/10/2024]. See the Terms and Conditions (https://onlinelibrary.wiley.com/terms-and-conditions) on Wiley Online Library for rules of use; OA articles are governed by the applicable Creative Commons License
8 VLSI Design

[7] E. Gómez-Hernández, C. Feregrino-Uribe, and R. Cumplido, [23] M. H. Rais and S. M. Qasim, “Virtex-5 Fpga implementation of
“FPGA hardware architecture of the steganographic context advanced encryptionstandard algorithm,” in Proceedings of the
technique,” in Proceedings of the IEEE Computer Society Inter- 3rd Global Conference on Power Control and Optimization, pp.
national Conference on Electronics, Communications and Com- 201–206, May 2010.
puters, pp. 123–128, Mexico, March 2008. [24] P. Ghosal, M. Biswas, and M. Biswas, “Hardware Implementa-
[8] B. J. Mohd, T. Hayajneh, S. Abed, and A. Itradat, “Analysis and tion of TDES CryptoSystem with on chip verification in FPGA,”
modeling of FPGA implementations of spatial steganography Journal of Telecommunications, vol. 1, no. 1, pp. 113–117, 2010.
methods,” Journal of Circuits, Systems and Computers, vol. 23, [25] K. Rahimunnisa, P. Karthigaikumar, S. Rasheed, J. Jayakumar,
no. 2, pp. 1–25, 2014. and S. Sureshkumar, “FPGA implementation of AES algorithm
[9] B. Ramalingam, R. Amirtharajan, and J. B. B. Rayappan, “Stego for high throughput using folded parallel architecture,” Security
on FPGA: An IWT Approach,” Hindawi Publishing Corporation and Communication Networks, vol. 7, no. 11, pp. 2225–2236,
Scientific World Journal, pp. 1–9, 2014. 2014.
[10] B. J. Mohd, T. Hayajneh, and A. N. Quttoum, “Wavelet-trans- [26] U. Farooq and M. F. Aslam, “Comparative analysis of different
form steganography: Algorithm and hardware implementa- AES implementation techniques for efficient resource usage and
tion,” International Journal of Electronic Security and Digital better performance of an FPGA,” Journal of King Saud Uni-
Forensics, vol. 5, no. 3-4, pp. 241–256, 2013. versity - Computer and Information Sciences, vol. 29, no. 3, pp.
[11] S. Mahmoudpour and S. Mirzakuchaki, “Hardware Architec- 295–302, 2017.
ture for a Message Hiding Algorithm with Novel Randomizers,” [27] A. Gielata, P. Russek, and K. Wiatr, “AES Hardware Implemen-
International Journal of Computer Applications, vol. 37, no. 7, pp. tation in FPGA for Algorithm Acceleration Purpose,” in Pro-
46–53, 2012. ceedings of the ICSES 2008 International Conference on Signals
[12] S. Rajagopala, P. J. Prabhakar, M. S. Kumar et al., “MSB Based and Electronic Systems, ICSES’08, pp. 137–140, Poland, Septem-
Embedding with Integrity: An Adaptive RGB Stego on FPGA ber 2008.
Platform,” Information Technology Journal, vol. 13, no. 12, pp. [28] S. Sadoudi, C. Tanougast, M. S. Azzaz, and A. Dandache,
1945–1952, 2014. “Design and FPGA Implementation of a wireless hyperchaotic
[13] A. Mahmood, N. Kanai, and S. Mohmmad, “An FPGA imple- communication system for secure real-time image transmis-
mentation of secured steganography communication system,” sion,” Journal on Image and Video Processing Springer, pp. 1–18,
Tikrit Journal of Engineering Sciences, vol. 19, no. 4, pp. 14–23, 2013.
2012. [29] R. R. Farashahi, B. Rashidi, and S. M. Sayedi, “FPGA based fast
[14] R. Sundararaman and H. Narayan Upadhyay, “Stego system on and high-throughput 2-slow retiming 128-bit AES encryption
chip with lfsr based information hiding approach,” International algorithm,” Microelectronics Journal, vol. 45, pp. 1014–1025, 2014.
Journal of Computer Applications, vol. 18, no. 2, pp. 24–31, 2011. [30] P. P. Karthigai and A. K. Baskaran, “FPGA implementation of
[15] A. Shabir, A. Parah Javaid, and G. M. Bhat, “Data hiding in high speed low area DWT based invisible image watermarking
intermediate significant bit planes, a high capacity blind ste- algorithm,” in Proceedings of the International Conference on
ganographic technique,” in Proceedings of the IEEE International Communication Technology and System Design Elsevier, vol. 30,
Conference on Emerging Trends in Science, Engineering and pp. 266–273, October 2012.
Technology, pp. 192–197, 2012. [31] T.-T. Quach, “Optimal cover estimation methods and stegano-
[16] S. A. El Rahman, “A comparative analysis of image steganog- graphic payload location,” IEEE Transactions on Information
raphy based on DCT algorithm and steganography tool to hide Forensics and Security, vol. 6, no. 4, pp. 1214–1222, 2011.
nuclear reactors confidential information,” Computers and Elec- [32] H.-L. Yeh, S.-T. Gue, P. Tsai, and W.-K. Shih, “Wavelet bit-plane
trical Engineering, pp. 1–20, 2016. based data hiding for compressed images,” AEÜ - International
[17] R. J. Anderson and F. A. P. Petitcolas, “On the limits of steganog- Journal of Electronics and Communications, vol. 67, no. 9, pp.
raphy,” IEEE Journal on Selected Areas in Communications, vol. 808–815, 2013.
16, no. 4, pp. 474–481, 1998. [33] A. Valizadeh and Z. J. Wang, “Correlation-and-bit-aware spread
[18] A. Odeh, K. Elleithy, and M. Faezipour, “Fast real-time hard- spectrum embedding for data hiding,” IEEE Transactions on
ware engine for multipoint text steganography,” in Proceedings Information Forensics and Security, vol. 6, no. 2, pp. 267–282,
of the 2014 IEEE Long Island Systems, Applications and Technol- 2011.
ogy Conference, LISAT 2014, pp. 1–5, May 2014. [34] Q. Mao, “A fast algorithm for matrix embedding steganography,”
[19] J. Fridrich, Steganography in Digital Media: Principles, Algo- Digital Signal Processing, vol. 25, no. 1, pp. 248–254, 2014.
rithms, and Applications, Cambridge University Press, New [35] O. M. Al-Qershi and B. E. Khoo, “High capacity data hiding
York, NY, USA, 2009. schemes for medical images based on difference expansion,” The
[20] H. A. Farouk and M. Saeb, “Design and implementation of a sec- Journal of Systems and Software, vol. 84, no. 1, pp. 105–112, 2011.
ret key steganographic micro-architecture employing FPGA,” in [36] A. Khamrui and J. K. Mandal, “A Genetic Algorithm-Based
Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Steganography using Discrete Cosine Transformation (GAS-
Automation Conference - 2004, pp. 577-578, Japan, January DCT),” in Proceedings of the International Conference on Com-
2004. putational Intelligence: Modeling Techniques and Applications,
[21] F. Cariccia, P. Cariccia, M. Martina, A. Molino, and F. Vacca, vol. 10, pp. 105–111, 2013.
“Multimedia SoC: A systolic core for embedded DCT evalu- [37] N. A. Saleh, H. N. Boghdady, S. I. Shaheen, and A. M. Darwish,
ation,” in Proceedings of the IEEE Conference Paper, pp. 1749– “High capacity lossless data embedding technique for palette
1753, USA, November 2002. images based on histogram analysis,” Digital Signal Processing,
[22] G. Renda, M. Masera, M. Martina, and G. Masera, “Approxi- vol. 20, no. 6, pp. 1629–1636, 2010.
mate Arai DCT architecture for HEVC,” in Proceedings of the
1st New Generation of CAS, NGCAS 2017, pp. 133–136, Italy,
September 2017.