SOI FinFET compact model for RF circuits simulation

J. Alvarado1, J.C. Tinoco2, S. Salas3, A.G. Martinez-Lopez3, B.S. Soto-Cruz1, A. Cerdeira4 and
J.-P. Raskin5
1
Centro de Investigación en Dispositivos Semiconductores, BUAP, Puebla, México
2
Depto. de Ing. en Telecomunicaciones, Facultad de Ingeniería UNAM, México D.F.
3
Centro de Investigación en Micro y Nanotecnología, Universidad Veracruzana, Veracruz, México
4
Sección de Electrónica del Estado Sólido, CINVESTAV, México D.F.
5
Institute ICTEAM, Université catholique de Louvain, Louvain-la-Neuve, Belgium

Abstract — A methodology to properly establish an Comparisons with experimental data of stand-alone

accurate SOI FinFET compact model through SPICE transistors are done to check the validity of the compact RF
simulator is presented. This compact model is implemented modeling. SOI FinFETs with 250 and 500 nm of channel
in Verilog-A to simulate the performance of RF circuits based
length (L) composed of 50 gate fingers (Nfinger) controlling 9
on SOI FinFET technology. It predicts well static behavior of
the transistor and circuit, as well as their small-signal RF fins (Nfin) each were built at IMEC, Leuven, Belgium. The
behavior by modeling the intrinsic capacitances and also the transistors with fin height (Hfin) and fin width (Wfin) of 60
effects of the gate resistance and the extrinsic gate and 32 nm, respectively, were measured. Also, the
capacitances. Finally, the comparison between the simulated transistors are characterized by a fin spacing (Sfin) of 328 nm
and measured performance of a Low Noise Amplifier and a extension length to the source and drain contact (Lext)
demonstrates the validity and the capabilities of this compact
of 145 nm. The gate stack is formed by 2 nm equivalent
model to simulate the dc and RF behavior of RF circuits.
oxide thickness (EOT), 5 nm of TiN metal and 100 nm-
thick polysilicon (Tpoly). Extraction of the small-signal
Index Terms — RF circuits, LNA, FinFETs, Compact
model, Verilog-A. parameters are performed according to [3].
After validation of the SOI FinFET compact model, the
I. INTRODUCTION static and RF performance of a Low Noise Amplifier
Thanks to the better electrostatic control of the channel (LNA) is simulated in SPICE. The important impact of the
with its three-gate architecture, which reduces the Short 3D extrinsic capacitances and gate resistance on LNA RF
Channel Effects (SCE), SOI FinFETs became attractive for performance is clearly demonstrated.
very high frequency applications. In this context, accurate
RF modeling is of first importance, which can be made II. SMALL-SIGNAL EQUIVALENT CIRCUIT
based on the definition of the small-signal lumped Fig. 1 shows the FinFET equivalent-circuit, where the
equivalent circuit [1]. Hence a compact model that intrinsic elements Cgsi, Cgdi, Cdsi, gdi and gmi are bias
considers internal capacitances as well as external parasitic dependent, whereas extrinsic capacitances Cgse, Cgde and Cdse
elements, such as three-dimensional (3D) capacitances, gate originate from the overlap between the source and drain
resistance and source/drain resistances, becomes crucial for regions and the thin gate oxide, and the fringing electric
this purpose. Recently, an analytical compact model for SOI field between contacts. Also, the bias independent extrinsic
Symmetric Doped Double Gate MOSFETs (SDDGM) was series resistances Rge, Rse and Rde are included.
implemented in Verilog-A, where its applicability for SOI According to [1], the impedance matrix is given by
FinFETs was demonstrated in [2] as well as its capability to Z¦ = Ze+YS-1, where the admittance matrix (YS) is:
reproduce the small-signal parameters from dc
characteristics [1]. The SDDGM compact model considers ª jZ Cgs  Cgd  jZCgd º (1)
the doping concentration of the silicon layer from lowly to YS « g  jZC g di  jZ Cds  Cgd »¼
¬ mi gd
highly doped, which provides good agreement with
numerical calculation of the potentials. Field dependent
where Cgs, Cgd and Cds are the sum of the extrinsic and
mobility as well as SCE, such as DIBL, channel length intrinsic capacitances as: Cgs = Cgsi + Cgse, Cgd = Cgdi +
modulation and velocity saturation, are included. Cgde and Cds = Csdi + Cdse and Ze is the extrinsic resistances
In this context, an extension of the Verilog-A matrix. Changes in technological parameters (e.g. oxide
implementation is proposed with the aim of correctly thickness) or bias conditions impose the need to execute
determining the behavior of the SOI FinFETs in high the whole extraction of the small-signal equivalent circuit,
frequency domain through SPICE simulations.

978-1-4673-1553-1/13/$31.00 © 2013 IEEE 87 SiRF 2013

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therefore a compact model becomes crucial to determine Sfin, Wfin, L, Tpoly and Hfin). The internal fringing capacitances
these parameters for any variation. Cfint are taken into account as in [1].
III. SMALL-SIGNAL MODEL C. Intrinsic Capacitances (Cggi)
The proposed methodology to correctly model the Considering the normalized charges qnd and qns calculated
small-signal parameter of a SOI FinFET considers the by the drain current model, analytical expressions for the
three following steps: (A) matching between experimental intrinsic capacitances are obtained according to [1]. Hence,
I-V curves and the modeled drain current, here normalized Cgsi, Cgdi and Csdi are calculated and the total gate to gate
charges at drain and source are determined, qnd and qns capacitance is given by Cgg = Cgs + Cgd, where:
respectively; (B) calculation of the 3D extrinsic
capacitances including external fringing field effects as C gs C gsi  C f int ˜ ^1  tanh >20 VG  Vt @` C fext (3)
presented in [4]; (C) determination of the intrinsic C gse
capacitances using the normalized charges qnd and qns
which can be calculated and fitted with measured values C gd C gdi  2C f int  C fext (4)
after removing the calculated extrinsic capacitances. The C gde
complete small-signal compact model has been validated where Vt the threshold voltage. Fig. 3 shows the comparison
with available experimental data and also finite-element between simulated and modeled capacitances at different
numerical simulations to cover a wide range of bias bias conditions and a fair agreement is observed.
conditions and FinFET geometries. The mobility degradation, series resistances and
A. Drain current model recombination models were modulated to get a good
Considering the first step, the drain current model has to matching between the measured I-V curves and the
match with experimental I-V curves and its expression is: simulations. Also, modeled capacitances and measured ones
are compared, and in order to extract the intrinsic
ª q 2  qnd
2
§ q  qb · º (2) parameters from the measured devices, it is necessary to
I DS I 0 « ns  2 qns  qnd  qb ln¨¨ ns ¸¸» remove RSD and Cgge (= Cgse + Cgde) as described in [1].
¬ 2 © qnd  qb ¹¼
Table I summarizes the obtained results.
where I0 = 2µeffIt2W/L Cox , , q is the normalized depleted
b IV. LOW NOISE AMPLIFIER
charge, It is the thermal voltage, Cox , is the oxide
capacitance per unit area and µeff is the effective mobility, In order to validate the small-signal model, a LNA is
which considers the effects of the lateral and transversal implemented in SPICE simulator. In Fig. 4 (left) the
electric fields according to [1]. Fig. 2 (top) shows the schematic view of the LNA and its measurement setup [5]
comparison between the experimental and modeled transfer are presented. Since a trans-impedance topology was
and output characteristics, whereas Fig. 2 (bottom) shows chosen, high power consumption but wide band can be
the comparison for the transconductance and conductance. achieved, as well as no coils and no couplings are
Fair agreement is demonstrated in each case, where the total necessary, which allows focusing on the FinFET device
source-drain extrinsic resistance (RSD) is included. behavior. VDD is set to 1.2 V and the current consumption of
the LNA is fixed close to 25 mA for both gate lengths. To
B. Extrinsic Capacitances (Cgge) fulfill the current consumption specification the total gate
Overlap and fringing field effects between the gate width of the transistors composing the LNA are WM1 =
electrode and the silicon film are modeled by Cgse and Cgde. 2,325 Pm and WM2 = 273 Pm for the 500 nm-gate length
Those fringing capacitances include internal (Cfint) and FinFETs, whereas they are WM1 = 5,014 Pm and WM2 =
external (Cfext) coupling fields. The external fringing 3,326 Pm for the 250 nm-long FinFETs.
capacitance is constant and originates from the 3D FinFET Fig. 4 (right) shows the simulated associated power gain
structure, whereas the internal fringing capacitance is bias for the two channel lengths, where a comparable
dependent due to the charge variation in the channel close to maximum gain is obtained in both cases. The gate
the source or drain regions. A new semi-analytical model resistance Rge is taken into account in these simulations
for the external capacitances has been developed [4] and is through the Wu’s model [6]. It is worth to point out that
now implemented in SDDGM compact model. The external the cut-off frequency of the simulated LNA circuit (fC_LNA)
capacitance compact model takes into account the is slightly higher for the LNA with shorter gate length
source/drain electrodes and has 5 components that describe FinFET (250 nm). Additionally, Fig. 4 (right) shows the
the different electrical couplings in the structure by power gain of experimental SOI 75 nm-long FinFET LNA
Cfext=Nfin(C1+C2+C3+C4+C5), where C1 to C5 are described circuit reported by Knoblinger [5]. The fC_LNA of their
in [4] and have dependence with FinFET geometry (Lext, LNA is only slightly higher than our simulated values for

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much longer FinFET channel length. This observed Table I. Comparison of the small-signal parameters predicted by the
saturation of the LNA cut-off frequency is related to the model and extracted from wideband S-parameters measurements [1].
excess of parasitic capacitances which are relatively more Model Measurements
important for shorter devices as was demonstrated in [3]. Gate length 500 nm 250 nm 500 nm 250 nm
In order to evaluate the degradation coming from the gmi / gdi (mS) 23/0.72 40/1.1 24.7/0.81 34.3/2.8
Cgsi / Cgdi (fF) 353/17.1 160/12 360.1/17.3 152.6/8
external capacitances on the LNA behavior, 250 nm- fT (GHz) 9.88 37 10.4 34
FinFET LNA is simulated in neglecting Cfext. Fig. 4 (right)
depicts the result of this simulation, where higher fC_LNA as
well as power gain are obtained. Additionally, considering
the other parasitic extrinsic effects that degrade the RF
performance, simulations with Rge reduced by a factor 2 and
5 are made. This artificial reduction of the parasitic
elements allows us to simulate the intrinsic performance of
the LNA. As a consequence, the minimization of Cfext and
Rge becomes mandatory in order to achieve higher fC_LNA and
gain.
V. CONCLUSIONS
An extended Verilog-A implementation of the SDDGM
compact model for SOI FinFETs in a SPICE simulator is
presented. Fair agreement with dc characteristics as well as
with extracted small-signal intrinsic parameters of modeled
and measured RF SOI FinFETs is demonstrated. Simulated
RF performance of LNA based on a FinFET technology
show good agreement with measured data presented in the
literature. This methodology provides an efficient way to
determine the analog and RF performance of SOI FinFET
RF circuits. Fig. 2. I-V characteristics (top) as well as transconductance and
conductance (bottom).
ACKNOWLEDGEMENT
This work was partially supported by PROMEP project
PROMEP/103-5/11/5481 and by UNAM-DGAPA-PAPIIT
IA101612. J. Alvarado thanks to CONACyT for its support
by “Programa de Apoyo Complementario para la
Consolidación Institucional Repatriación y Retención”.
REFERENCES
[1] J. Alvarado et al., in Proc. 2012 8th ICCDCS.
[2] J. Alvarado et al., in Proc. MIXDES’09, 2009.
[3] J.C. Tinoco et al., in Proc. SiRF’12, 2012. Fig. 3. Simulated and modeled capacitances.
[4] S. Salas et al., accepted to SiRF’13, 2013.
[5] G. Knoblinger et al., in Proc. 2007 IEEE Inter. SOI Conf.
[6] W. Wu and M. Chan, IEEE TED, vol. 54, April 2007.

Fig. 4. Schematic of the LNA and its measurements setup (left).

Fig. 1. Small-signal equivalent circuit model of SOI FinFET. Simulated power gain of LNA (right).

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