0% found this document useful (0 votes)
8 views2 pages

MP ct1

Uploaded by

nithya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
8 views2 pages

MP ct1

Uploaded by

nithya
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
You are on page 1/ 2

SRM INSTITUTE OF SCIENCE & TECHNOLOGY 8.

Port C of 8255 can function independently as


RAMAPURAM CAMPUS
DEPARTMENT OF ELECTRICAL AND ELECTRONICS a) input port b) output port
ENGINEERING c) either input or output ports d) both input and output ports
CYCLE TEST -I Date : 21.02.18
Sub. Code :15EE305J Max. Marks : 75 9. In 8257 (DMA), each of the four channels has
Sub. Name : Duration : 130 MIN a) a pair of two 8-bit registers b) a pair of two 16-bit registers
MICROCONTROLLERS c) one 16-bit register d) one 8-bit register
Year / SEM : III/ VI
ANSWER ALL THE QUESTIONS 10. The pin that disables all the DMA channels by clearing the mode
PART A (15 x 1 = 15 Marks) registers is
1. To address a memory location out of N memory locations, the a) MARK b) CLEAR c) RESET d) READY
number of address lines required is 11. Which is not the control bus signal:
a) READ b) WRITE c) RESET d) ALE
a) log N (to the base 2) b) log N (to the base 10)
12. In the following interrupts which is the non-vectored interrupt
c) log N (to the base e) d) log (2N) (to the base e) a)TRAP b)INTR c)RST 7.5 d)RST 6.5
2. The advantage of dynamic RAM is 13. The registers that holds the address of the word currently being
a) high packing density b) low cost written by the CPU from the display RAM are
c) less power consumption d) all of the mentioned a) control and timing register
3. The process of refreshing the data in the RAM to reduce the b) control and timing register and timing control
c) display RAM d) display address registers
possibility of data loss is known as
14. The bus is available when the DMA controller receives the signal
a) data cycle b) regain cycle a) HRQ b) HLDA c) DACK d) INTA
c) retain cycle d) refresh cycle 15. The operation that can be performed on the status register is
4. A mask programmed ROM is a) write operation b) read operation
a)programmed at the time of fabrication c) read and write operations d) Interrupt operation
b) programmed by the user
c) erasable and programmable PART B
d) erasable electrically (ANSWER ANY 6) (6*4=24)
5․ Which one of the following circuits transmits two messages 16. Differentiate Microprocessor & Microcontroller
simultaneously in one direction
17. Explain the flag register of 8085
a)Duplex b)Diplex c)Simplex d)Quadruplex
6. Name the address pair which store the address of memory 18. Draw and explain the Tristate logic of microprocessor.
location 19. Write the control word of 8255
a) BC b)HL c) DE d)AB 20. Explain DMA data transfer and the related signals.
7. Programmable peripheral input-output port is other name for 21. Define Interrupts and the related signal used in 8085
a) serial input-output port b) parallel input-output port 22. What are the features of DMA controller?
23. What are the two modes of operation of keys in keyboard
c) serial input port d) parallel output port
PART C
Answer All the Questions (2*12= 24 marks)

24. Draw and Explain the architecture of 8085


(OR)
25. Explain the classification of memory in detail

26. With a neat diagram explain in detail about programmable


Peripheral I/O ports of 8255.
OR
27. Explain the 8257 DMA controller with a neat block diagram
28. With a neat diagram explain the operation of 8279 keyboard /
Display controller
OR
29. Explain the various steps involved in microprocessor based system
design

You might also like