0% found this document useful (0 votes)
35 views3 pages

Saket 2

Uploaded by

Sagnik Barik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
35 views3 pages

Saket 2

Uploaded by

Sagnik Barik
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 3

SAKET SHOBHELAL Email: gajbhiyesaket@gmail.

com
GAJBHIYE Linkedin: linkedin.com/in/saket-gajbhiye-0285a6189
( MTech - VLSI Design, VNIT Nagpur ) Contact: +91 8149784616

AREAS OF INTEREST
Digital Circuit Design, RTL Design, Logic Synthesis, Physical Design, STA, ASIC Design, Analog
Design

SUMMARY
❏ M.Tech in VLSI Design from NIT Nagpur in July 2020.
❏ Worked on ASIC Design flow from RTL to GDSII.
❏ Hands-on experience with synthesis and analysis of RTL designs using Design Compiler.
❏ Experience in Static Timing Analysis of synthesized design using Synopsys Primetime
❏ Hands-on experience in Placement and Routing flow using Cadence Innovus (Floor planning, Power
planning , Standard Cells Placements, Global and Nano Route, CTS , Setup and Hold Analysis, Filler Cell
Placement)
❏ Good understanding of Verilog HDL and C programming.
❏ Good understanding of Digital VLSI Design, VLSI system Design concept, low power design concept through various
courses works in MTech.
❏ Hands on experience in device testing and characterization using probe station and Keithley.

ACADEMIC QUALIFICATION ..
QUALIFICATION SPECIALIZATION INSTITUTE YEAR CGPA

M.Tech VLSI Design NIT Nagpur 2020 6.6

B.E Electronics Mumbai 2014 61


University
XII (HSC) STATE Board ( PCM ) Nagpur 2010 80
University
X (SSC) STATE Board Nagpur 2008 86
University

TECHNOLOGY
PUBLICATIONS SPECIFIC APPLICATIONS/TOOLS
( IEEE INDICON 2019 ) …………………………………………………

❏ RTL Design : Vivado (Xilinx), ISE (Xilinx), VCS(Synopsys)


❏ Synthesis Tool : Design Compiler (Synopsys), Genus (Cadence),Primetime(STA)
❏ LEC Tool : Conformal LEC (Cadence), Formality(Synopsys)
❏ PNR Tool : Innovus (Cadence)
❏ SPICE Tool : ngspice (Opensource)
❏ Device modelling : Proteus, COMSOL Multiphysics
❏ Hardware Description and Programing Language : Verilog, C Programming
.
Courses:
• Hardware Modeling Using Verilog by IIT Kharagpur NPTEL.
• CMOS Digital VLSI Design by IIT Roorkee NPTEL.
• VSD – Static Timing Analysis by Kunal Ghosh from Udemy.
• VSD- Physical Design Flow by Kunal Ghosh from Udemy.

PROJECTS

Handheld device to measure Particulate Matter (PM2.5 and PM10) 2019-2020


❏ Hardware used : Laser, photodiode
❏ Description : In this work I am trying to measure mass concentration and no. of particle
of dust using optical scattering principal

Implementation of complete RTL to GDSII Flow for 4-bit adder 2019


❏ Software used : Vivado (Xilinx), Design Compiler (Synopsys), Conformal LEC (Cadence),
Innovus(Cadence)
❏ Description : Designed 4-bit adder using Verilog HDL and performed all the steps in
RTL to GDS2 flow which includes simulation, synthesis, LEC, PNR and physical
verification using SCL 180nm.

Huffman Coding on FPGA 2018


❏ Software used : ISE Xilinx
❏ Description : Huffman Coding for Data Compression technique using Verilog and
implemented on FPGA.

Design of multifunctional calculator and implementation on Basys3 board. 2018


Software used : Vivado Xilinx
❏ Description : Multifunctional calculator Programed using verilog and implemented on the
7-segment display on Basys3 board for showing result and used slide switches to give inputs.

DTMF Based Load Control 2013-14


Description: This project is used to control any electrical device/appliance remotely around the
globe. It makes use of Dual Tone Multiple Frequency (DTMF) controller to accomplish the same
with the help of microcontrollers and relays depending on the outputs controller.
EXTRA - CURRICULAR ACTIVITIES

❏ Teaching Assistant For B.Tech Student (For Device Modeling LAB in VNIT)2020 (6 month)
❏ Delivered a lecture on the Design Compiler (Synopsys) in the SMDP workshop
conducted by VNIT.
❏ Participated in the 5th International Symposium on Semiconductors Materials and Devices (ISSMD)
❏ Attended workshop on “RTL to GDSII Flow & Test and Technology Technical
Council India”.

POSITIONS and RESPONSIBILITY

❏ Vice-Captain for club named Furious Falcon sports fest named VIHANG
2020(Only sports fest organized for Post Graduates) in NIT Nagpur.
❏ Captain for Basketball team in various events.
❏ Headed a District level troop of Scout and Guide summit held in Nashik(2008).
❏ Organized Football, Basketball and Futsal major fests of college named “HORIZON”
❏ Worked as publicity co-ordinator during College Fest.

DECLARATION

I, hereby confirm that the information given above is true to the best of my knowledge.

SAKET SHOBHELAL GAJBHIYE

You might also like