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Module 4 - Cache Memory Problems

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24 views

Module 4 - Cache Memory Problems

Uploaded by

somesh.tg2023
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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1. A two-way set associative cache memory uses blocks of four words.

The
cache can accommodate a total of 2048 words from main memory. The main
memory size is 128K x 32.
a. How many bits are there in the tag, block and word fields of the address
format?
b. What is the size of the cache memory?

Solution-

128 K = 217; For a set size of 2, the index: address has 10 bits to accommodate
2048/2 = 1024 words of cache.
(a)

7 bits 10 bits

TAG INDEX

← Block → Words ←
8 bits 2 bits
b)
Tag 1 Data 1 Tag 2 Data 2 0

1024
← 7 → ← 32 bits → ← 7 → ← 32 bits →
Size of cache memory is 1024 x 2 (7 + 32)
= 1024 × 78

2. A digital computer has a memory unit of 64K x 16 and a cache memory of


1K words. The cache uses direct mapping with a block size of four words.
a. How many bits are there in the tag, block and word fields of the address
format?
b. How many bits are there in the each word of cache, and how are they
divided into functions? Include a valid bit.
c. How many blocks can the cache accommodate?
Solution-

64 K × 16: 16 bit address; 16-bit data.


(a) 6 8 2 = 16 bits address
TAG BLOCK WRD

INDEX = 10 bit cache address.


b)1 6 16 = 23 bits in each word of cache
V TAG DATA

(b) 28 = 256 blocks of 4 words each

3. Consider a 64KB direct-mapped cache with a line length of 32 bytes.

a. Determine the number of bits in the address that refer to the byte within a cache
line.

b. Determine the number of bits in the address required to select the cache line.

Solution-

a. For the given cache, the number of bits in the address to determine the byte
within the line=

n = 2 5 = 5 bits

b. There are 64K/32= 2048 lines in the given cache. The number of bits required to
select the required line 2 11 = 11 bits

4. Consider a direct mapped cache with 8 cache blocks (0-7). If the memory block
requests are in the order-
3, 5, 2, 8, 0, 6, 3, 9, 16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82, 17, 24
Which of the following memory blocks will be in the cache at the end of the
sequence?

Also, calculate the hit ratio and miss ratio.


We have,
 There are 8 blocks in cache memory numbered from 0 to 7.
 In direct mapping, a particular block of main memory is mapped to a particular
line of cache memory.
 The line number is given by-
Cache line number = Block address modulo Number of lines in cache
Solution-

For the given sequence-


 Requests for memory blocks are generated one by one.
 The line number of the block is calculated using the above relation.
 Then, the block is placed in that particular line.
 If already there exists another block in that line, then it is replaced.
 Hit ratio = 3 / 20
 Miss ratio = 17 / 20
5. Consider a fully associative cache with 8 cache blocks (0-7). The memory block
requests are in the order-
4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, 8, 3, 16, 25, 7
If LRU replacement policy is used, which cache block will have memory block 7?
Also, calculate the hit ratio and miss ratio.

Solution-

We have,
 There are 8 blocks in cache memory numbered from 0 to 7.
 In fully associative mapping, any block of main memory can be mapped to any
line of the cache that is freely available.
 If all the cache lines are already occupied, then a block is replaced in accordance
with the replacement policy.

Thus,
 Line-5 contains the block-7.
 Hit ratio = 5 / 17
 Miss ratio = 12 / 17

6.

A cache is having 60% hit ratio for read operation. Cache access time is 30 ns and
main memory access time is 100 ns, 50% operations are read operation.
What will be the average access time for read operation?

Avg access time (for read operation) = Hit ratio * cache access time + miss ratio *
( Cache access time + MM access time )
Given, Cache access time is 30 ns and main memory access time is 100 ns.
Hit ratio = 60% so Miss ratio = 40%
so Avg access time = (0.6 * 30 ) + 0.4 * ( 30 + 100 )
= 18 + 52
= 70
so average access time for read operation is 70 ns.

7. In a two-level cache system, the access times of L 1 and L2 1 and 8 clock cycles,
respectively. The miss penalty from the L 2 cache to main memory is 18 clock
cycles. The miss rate of L1 cache is twice that of L2. The average memory access
time(AMAT) of this cache system is 2 cycles. Find the miss rates of L 1 and L2 .
miss rates of L1 0.111 and L2 is 0.056

Average Memory Access time = Hit time + Miss Rate x Miss penalty

Consider a system with 2 level caches. Access times of Level 1 cache, Level 2
cache and main memory are 1 ns, 10ns, and 500 ns, respectively. The hit rates
of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the
average access time of the system ignoring the search time within the cache?

Ave rage access t ime = [H 1 *T 1 ]+ [ ( 1 -H 1 ) * H2 *T 2 ]+ [ ( 1 -H 1 ) ( 1 -H 2 ) *Hm *Tm ]


where,
H1 = Hit rate of level 1 cache = 0.8
T1 = Access time for level 1 cache = 1 ns
H2 = Hit rate of level 2 cache = 0.9
T2 = Access time for level 2 cache = 10 ns
Hm = Hit rate of Main Memory = 1
Tm = Access time for Main Memory = 500 ns

So, Average Access Time = ( 0.8 * 1 ) + ( 0.2 * 0.9 * 10 ) + ( 0.2 * 0.1 * 1 *


500)
= 0.8 + 1.8 + 10
= 12.6 ns

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