Chapter-1 Combinational logic circuits

Combinational circuit is a circuit in which we combine the different gates in the circuit, for example
encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational
circuits are following −

 The output of combinational circuit at any instant of time, depends only on the levels present
at input terminals.
 The combinational circuit do not use any memory. The previous state of input does not have
any effect on the present state of the circuit.
 A combinational circuit can have an n number of inputs and m number of outputs.

Block diagram

1. Half Adder

The Half-Adder is a basic building block of adding two numbers as two inputs and produce out two
outputs. The adder is used to perform OR operation of two single bit binary numbers.
The augent and addent bits are two input states, and 'carry' and 'sum 'are two output states of the
half adder.

Block diagram Truth Table

In the above table,

1. 'A' and' B' are the input states, and 'sum' and 'carry' are the output states.
2. The carry output is 0 in case where both the inputs are not 1.
3. The least significant bit of the sum is defined by the 'sum' bit.

The SOP form of the sum and carry are as follows:

Sum = x'y+xy'
Carry = xy
Construction of Half Adder Circuit:

In the block diagram, we have seen that it contains two inputs and two outputs.
The augent and addent bits are the input states, and carry and sum are the output states of the half
adder. The half adder is designed with the help of the following two logic gates:

 2-input AND Gate.

 2-input Exclusive-OR Gate or Ex-OR Gate

1) 2-input Exclusive-OR Gate or Ex-OR Gate

The Sum bit is generated with the help of the Exclusive-OR or Ex-OR Gate.

Block diagram Truth Table

The above is the symbol of the EX-OR gate. In the above diagram, 'A' and 'B' are the inputs,
and the 'SUMOUT' is the final outcome after performing the XOR operation of both numbers.

From the above table, it is clear that the XOR gate gives the result 1 when both of the inputs
are different. When both of the inputs are the same, the XOR gives the result 0.

2) 2-input AND Gate:

The XOR gate is unable to generate the carry bit. For this purpose, we use another gate
called AND Gate

The AND gate gives the correct result of the carry.

Block diagram Truth Table

The above is the symbol of the AND gate. In the above diagram, 'A' and 'B' are the inputs, and
'OUT' is the final outcome after performing AND operation of both numbers.
 From the above table, it is clear that the AND gate gives the result 1 when both of the inputs
are 1. When both of the inputs are different and 0, the AND gates gives the result 0.

Half-Adder logical circuit:

So, the Half Adder is designed by combining the 'XOR' and 'AND' gates and provide the sum
and carry.

2. Half Subtractor

The half subtractor is also a building block for subtracting two binary numbers. It has two inputs and
two outputs. This circuit is used to subtract two single bit binary numbers A and B. The 'diff'
and 'borrow' are two output states of the half subtractor.

Block diagram Truth Table

The SOP form of the Diff and Borrow is as follows:

Diff= A'B+AB'
Borrow = A'B

In the above table,

o 'A' and 'B' are the input variables whose values are going to be subtracted.
o The 'Diff' and 'Borrow' are the variables whose values define the subtraction result, i.e.,
difference and borrow.
o The first two rows and the last row, the difference is 1, but the 'Borrow' variable is 0.
o The third row is different from the remaining one. When we subtract the bit 1 from the bit 0,
the borrow bit is produced.
Construction of Half Subtractor Circuit:

In the block diagram, we have seen that it contains two inputs and two outputs.
The carry and sum are the output states of the half subtractor. The half subtractor is designed with
the help of the following logic gates:

 2-input AND gate.

 2-input Exclusive-OR Gate or Ex-OR Gate
 NOT or inverter Gate

1) 2-input Exclusive-OR Gate or Ex-OR Gate

The Diff bit is generated with the help of the Exclusive-OR or Ex-OR gate.

Block diagram Truth Table

The above is the symbol of the EX-OR gate. In the above diagram, 'A' and 'B' are the inputs,
and 'Diff' is the final outcome after performing the XOR operation of both numbers.

From the above table, it is clear that the XOR gate gives the result 1 when both of the inputs
are different. When both of the inputs are the same, the XOR gives the result 0.

2) 2-input AND gate:

The XOR gate is unable to generate the carry bit. For this purpose, we use another gate
called AND gate. The AND gate is not enough to give the correct result of 'Borrow'. We
will use the NOT gate with the 'AND' gate to get the correct result.

Block diagram Truth Table

The above is the symbol of the AND gate. In the above diagram, 'A' and 'B' are the inputs,
and 'OUT' is the final outcome after performing AND operation of both numbers.

From the above table, it is clear that the AND gate gives the result 1 when both of the inputs
are 1. When both of the inputs are different and 0, the AND gates gives the result 0.
 3) NOT or Inverter Gate:

The NOT gate is used to get the inverse output. We can combine the 'AND' and 'NOT' gates
in order to get the combinational gate 'NAND'. By inverting the input 'A' using 'NOT' gate
and then use the output of the 'NOT' gate as the input of the 'AND' gate, we can get the
'Borrow' bit.

Block diagram Truth Table

Half-Subtractor logical circuit:

So, the Half Subtractor is designed by combining the 'XOR', 'AND', and 'NOT' gates and provide the
Diff and Borrow.

3. Full Adder

The half adder is used to add only two numbers. To overcome this problem, the full adder was
developed. The full adder is used to add three 1-bit binary numbers A, B, and carry C. The full adder
has three input states and two output states i.e., sum and carry.

Block diagram Truth Table

In the above table,

1. 'A' and' B' are the input variables. These variables represent the two significant bits which are
going to be added
2. 'Cin' is the third input which represents the carry. From the previous lower significant position,
the carry bit is fetched.
3. The 'Sum' and 'Carry' are the output variables that define the output values.
4. The eight rows under the input variable designate all possible combinations of 0 and 1 that
can occur in these variables.

Construction of Half Adder Circuit:

In the above circuit, there are two half adder circuits that are combined using the OR gate. The first
half adder has two single-bit binary inputs A and B. As we know that, the half adder produces two
outputs, i.e., Sum and Carry. The 'Sum' output of the first adder will be the first input of the second
half adder, and the 'Carry' output of the first adder will be the second input of the second half adder.
The second half adder will again provide 'Sum' and 'Carry'. The final outcome of the Full adder
circuit is the 'Sum' bit. In order to find the final output of the 'Carry', we provide the 'Carry' output of
the first and the second adder into the OR gate. The outcome of the OR gate will be the final carry
out of the full adder circuit.

The MSB is represented by the final 'Carry' bit.

The full adder logic circuit can be constructed using the 'AND' and the 'XOR' gate with an OR
gate.

The actual logic circuit of the full adder is shown in the above diagram. The full adder circuit
construction can also be represented in a Boolean expression.

 Sum:
 Perform the XOR operation of input A and B.
  Perform the XOR operation of the outcome with carry. So, the sum is (A XOR B) XOR

(A ⊕ B) ⊕ Cin
Cin which is also represented as:

 Carry:
 Perform the 'AND' operation of input A and B.
 Perform the 'XOR' operation of input A and B.
 Perform the 'OR' operations of both the outputs that come from the previous two steps. So

A.B + (A ⊕ B)
the 'Carry' can be represented as:

4. Full Subtractors

The Half Subtractor is used to subtract only two numbers. To overcome this problem, a full
subtractor was designed. The full subtractor is used to subtract three 1-bit numbers A, B, and C,
which are minuend, subtrahend, and borrow, respectively. The full subtractor has three input states
and two output states i.e., diff and borrow.

Block diagram Truth Table

In the above table,

o 'A' and' B' are the input variables. These variables represent the two significant bits that are
going to be subtracted.
o 'Borrowin' is the third input which represents borrow.
o The 'Diff' and 'Borrow' are the output variables that define the output values.
o The eight rows under the input variable designate all possible combinations of 0 and 1 that
can occur in these variables.

Construction of Full Subtractor Circuit:

 In the above circuit, there are two half adder circuits that are combined using the OR gate. The first
half subtractor has two single-bit binary inputs A and B. As we know that, the half subtractor
produces two outputs, i.e., 'Diff' and 'Borrow'. The 'Diff' output of the first subtractor will be the first
input of the second half subtractor, and the 'Borrow' output of the first subtractor will be the second
input of the second half subtractor. The second half subtractor will again provide 'Diff' and 'Borrow'.
The final outcome of the Full subtractor circuit is the 'Diff' bit. In order to find the final output of the
'Borrow', we provide the 'Borrow' of the first and the second subtractor into the OR gate. The
outcome of the OR gate will be the final carry 'Borrow' of full subtractor circuit.

The MSB is represented by the final 'Borrow' bit.

The full subtractor logic circuit can be constructed using the 'AND', 'XOR', and NOT gate with
an OR gate.

The actual logic circuit of the full subtractor is shown in the above diagram. The full subtractor
circuit construction can also be represented in a Boolean expression.

 Diff:
 Perform the XOR operation of input A and B.
 Perform the XOR operation of the outcome with 'Borrow'. So, the difference is (A XOR B)

(A ⊕ B) ⊕ 'Borrowin'
XOR 'Borrowin' which is also represented as:

 Borrow:
 Perform the 'AND' operation of the inverted input A and B.
 Perform the 'XOR' operation of input A and B.
 Perform the 'OR' operations of both the outputs that come from the previous two steps. So

A'.B + (A ⊕ B)'
the 'Borrow' can be represented as:

5. Binary Adder

The registers play an important role in performing the micro-operations. The registers hold the digital
component and the data which performs the arithmetic operation. The Binary Adder is a logical
circuit which is used to perform the addition operation of two binary number of any length.

The Binary Adder is formed with the help of the Full-Adder circuit. The Full-Adders are connected
in series, and the output carry of the first Adder will be treated as the input carry of the next Full-
Adder.
 N-Bit Parallel Adder

The Full Adder is used to sum two single-bit binary numbers with carry input. In digital calculation,
we need to add two n-bit binary numbers rather than only single-bit binary numbers. For this
purpose, we need to use n-bit parallel Adder. In order to get N-bit parallel adder, we cascade the n
number of Full Adders. The carry output of the first Adder is treated as the carry input of the second
Adder.

4-bit Binary Adder

o The 'A' and 'B' are the augend, and addend bits are defined by the subscript numbers. The
subscripts start from right to left, and the lower-order bit is defined by subscript '0'.
o The C0, C1, C2, and C3 are the carry inputs which are connected together as a chain using
Full Adder. The C4 is the carry output produced by the last Full-Adder.
o The Cout of the first Adder is connected as the Cin of the next Full-Adder.
o The S0, S1, S2, and S3 are the sum outputs that produce the sum of augend and addend bits.
o The inputs for the input variable 'A' and 'B' are fetched from different source registers. For
example, the bit for the input variable 'A' comes from register 'R1', and a bit for the input
variable 'B' comes from register 'R2'.
o The outcome produced by adding both input variables is stored into either third register or to
one of the source registers.

6. Binary Adder-Subtractor
A Binary Adder-Subtractor is a special type of circuit that is used to perform both operations, i.e.,
Addition and Subtraction. The operation which is going to be used depends on the values contained
by the control signal. In Arithmetic Logical Unit, it is one of the most important components.

To work with Binary Adder-Subtractor, it is required that we have knowledge of the XOR gate, Full-
Adder, Binary Addition, and subtraction.

For example, we will take two 4-bit binary numbers 'X' and 'Y' for the operation with digits.
X0 X1 X2 X3 for X
Y0 Y1 Y2 Y3 for Y

The Binary Adder-Subtractor is a combination of 4 Full-Adder, which is able to perform the addition
and subtraction of 4-bit binary numbers. The control line determines whether the operation being
performed is either subtraction or addition. This determination is done by the binary values 0 and 1,
which is hold by K.

In the above diagram, the control lines of the first Full-Adder is directly coming as its input(input
carry C0). The X0 is the least significant bit of A, which is directly inputted in the Full-Adder. The
result produced by performing the XOR operation of Y 0 and K is the third input of the Binary Adder-
Subtractor. The sum/difference(S0) and carry(C0) are the two outputs produced from the First Full-
adder.

When the value of K is set to true or 1, the Y 0⨁K produce the complement of Y0 as the output. So
the operation would be X+Y0', which is the 2's complement subtraction of X and Y. It means when
the value of K is 1; the subtraction operation is performed by the binary Adder-Subtractor.

In the same way, when the value of K is set to 0, the Y 0⨁K produce Y0 as the output. So the
operation would be X+Y0, which is the binary addition of X and Y. It means when the value of K is
0; the addition operation is performed by the binary Adder-Subtractor.

The carry/borrow C0 is treated as the carry/borrow input for the second Full-Adder. The
sum/difference S0 defines the least significant bit of the sum/difference of numbers X and Y. Just like
X0, the X1, X2, and X3 are faded directly to the 2nd, 3rd, and 4th Full-Adder as an input. The outputs
after performing the XOR operation of Y1, Y2, and Y3 inputs with K are the third inputs for 2 nd, 3rd,
and 4th Full-Adder. The carry C1, C2 are passed as the input to the Full-Adder. Cout is the output carry
of the sum/difference. To form the final result, the S 1, S2, S3 are recorded with s0. We will use n
number of Full-Adder to design the n-bit binary Adder-Subtractor.

Example:

We assume that we have two 3 bit numbers, i.e., X=100 and Y=011, and feed them in Full-Adder as
an input.
 X0 = 0 X1 = 0 X2 = 1
Y0 = 1 Y1 = 1 & Y2 = 0

Y0⨁K=Y0 and Cin=K=0

For K=0:

So, from first Full-Adder

S0 = X0+Y0+Cin
S0= 0 + 1 + 0

7. Multiplexer

A multiplexer is a combinational circuit that has 2 n input lines and a single output line. Simply, the
multiplexer is a multi-input and single-output combinational circuit. The binary information is
received from the input lines and directed to the output line. On the basis of the values of the
selection lines, one of these data inputs will be connected to the output.

Unlike encoder and decoder, there are n selection lines and 2 n input lines. So, there is a total of
2N possible combinations of inputs. A multiplexer is also treated as Mux.

There are various types of the multiplexer which are as follows:

 2×1 Multiplexer:

In 2×1 multiplexer, there are only two inputs, i.e., A 0 and A1, 1 selection line, i.e., S0 and
single outputs, i.e., Y. On the basis of the combination of inputs which are present at the
selection line S0, one of these 2 inputs will be connected to the output. The block diagram and
the truth table of the 2×1 multiplexer are given below.

Block diagram Truth Table

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1

Logical circuit of the above expression is given below:

 4×1 Multiplexer:

In the 4×1 multiplexer, there is a total of four inputs, i.e., A 0, A1, A2, and A3, 2 selection lines,
i.e., S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs that are
present at the selection lines S0 and S1, one of these 4 inputs are connected to the output. The
block diagram and the truth table of the 4×1 multiplexer are given below.

Block diagram Truth Table

The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Logical circuit of the above expression is given below:

 8 to 1 Multiplexer

In the 8 to 1 multiplexer, there are total eight inputs, i.e., A 0, A1, A2, A3, A4, A5, A6, and A7, 3
selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination of
inputs that are present at the selection lines S0, S1, and S2, one of these 8 inputs are connected
to the output. The block diagram and the truth table of the 8×1 multiplexer are given below.

Block diagram Truth Table

The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A6
+S0.S1.S3.A7

Logical circuit of the above expression is given below:

 8 ×1 multiplexer using 4×1 and 2×1 multiplexer

We can implement the 8×1 multiplexer using a lower order multiplexer. To implement the
8×1 multiplexer, we need two 4×1 multiplexers and one 2×1 multiplexer. The 4×1
multiplexer has 2 selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only 1
selection line.

For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1 multiplexer produces one
output. So, in order to get the final output, we need a 2×1 multiplexer. The block diagram of
8×1 multiplexer using 4×1 and 2×1 multiplexer is given below.

8. Demultiplexer

A De-multiplexer is a combinational circuit that has only 1 input line and 2 N output lines. Simply, the
multiplexer is a single-input and multi-output combinational circuit. The information is received from
the single input lines and directed to the output line. On the basis of the values of the selection lines,
the input will be connected to one of these outputs. De-multiplexer is opposite to the multiplexer.

Unlike encoder and decoder, there are n selection lines and 2 n outputs. So, there is a total of
2n possible combinations of inputs. De-multiplexer is also treated as De-mux.

There are various types of De-multiplexer which are as follows:

 1×2 De-multiplexer:
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y 0, and Y1, 1 selection lines, i.e.,
S0, and single input, i.e., A. On the basis of the selection value, the input will be connected to
one of the outputs. The block diagram and the truth table of the 1×2 multiplexer are given
below.
 Block diagram Truth Table

The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A

Logical circuit of the above expressions is given below:

 1×4 De-multiplexer:

In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and Y3, 2 selection
lines, i.e., S0 and S1 and single input, i.e., A. On the basis of the combination of inputs which
are present at the selection lines S 0 and S1, the input be connected to one of the outputs. The
block diagram and the truth table of the 1×4 multiplexer are given below.

Block diagram Truth Table

 The logical expression of the term Y is as follows:

Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A

Logical circuit of the above expressions is given below:

 1×8 De-multiplexer:

In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and
Y7, 3 selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of the combination
of inputs which are present at the selection lines S 0, S1 and S2, the input will be connected to
one of these outputs. The block diagram and the truth table of the 1×8 de-multiplexer are
given below.

Block diagram Truth Table

The logical expression of the term Y is as follows:

Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2 A
Y5=S0.S1'.S2 A
Y6=S0'.S1.S2 A
Y7=S0.S1.S3.A

Logical circuit of the above expressions is given below:

1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer

We can implement the 1×8 de-multiplexer using a lower order de-multiplexer. To implement
the 1×8 de-multiplexer, we need two 1×4 de-multiplexer and one 1×2 de-multiplexer. The
1×4 multiplexer has 2 selection lines, 4 outputs, and 1 input. The 1×2 de-multiplexer has only
1 selection line.

For getting 8 data outputs, we need two 1×4 de-multiplexer. The 1×2 de-multiplexer produces
two outputs. So, in order to get the final output, we have to pass the outputs of 1×2 de-
multiplexer as an input of both the 1×4 de-multiplexer. The block diagram of 1×8 de-
multiplexer using 1×4 and 1×2 de-multiplexer is given below.
9. Implementation of Boolean equations using Multiplexer & demultiplexer

 Type #1

Let us solve some problems on implementing the boolean expressions using a multiplexer. In this
method, 3 variables are given(say P, Q, R), which are the selection inputs for the mux. For three
selection inputs, the mux to be built was 2n = 23 = 8 : 1. So, in this method, the type of mux can
be decided by the given number of variables.
How to solve?
i. The first step is to select the multiplexer. If the given expression has n variables, then
determine the multiplexer using the formula 2n : 1.
ii. Connect the inputs, that correspond to the given minterms to logic 1.
iii. Connect all the other inputs to the ground(logic 0).
iv. Connect the input variables(P, Q, R) as the selection lines.

Solved problem #1
Implement the boolean expression F(A, B, C) = ∑ m(2, 3, 6, 7) using a multiplexer.

Solution:

There are 3 variables in the given expression, hence 2n = 23 = 8 : 1 multiplexer. So, the mux has 8
input lines, 3 selection lines, and one output.

The inputs, corresponding to the minterms (2, 3, 6, 7) are connected to logic 1 and the remaining
terms to logic 0(grounded). The given input variables are connected as three selection lines.
 Solved problem #2

Implement the boolean expression F(A, B, C) = ∑ m(0, 1, 3, 5, 7) using a multiplexer.

Solution:

Similar to the above problem, there are 3 variables and hence 8 : 1 multiplier is used to solve the
expression. The three input variables(A, B, C) are connected as three selection lines.

The inputs, corresponding to the minterms (0, 1, 3, 5, 7) are connected to logic 1 and the
remaining terms to the logic 0(grounded).

 Type #2

If the boolean expression has n+1 variables, we take only n variables as the selection line of the
multiplexer. The remaining single variable is used as the inputs of the mux. In this way, any
boolean expression having n variables can be implemented with 2n-1 to 1 multiplexer.

How to solve this method?

i. From the given set of n+1 input variables, the n least significant variables are used as
selection line inputs.
ii. The 2n inputs for 2n : 1 multiplexer are derived by using an implementation table.
iii. The implementation table has all the inputs(D0, D1, D2, D3,…) for the multiplexer, under
which, all the minterms are listed in two rows.
iv. The first row consists of all minters where A is complemented and the second row has the
remaining minterms where A is in uncomplemented form.
v. The minterms in the given boolean expression alone are circled.

Look at the example of implementation table here,

Each column is analyzed separately as follows:

 If both the minterms in the two rows are circled, 1 is applied to the corresponding multiplexer
input.(check 4th column in the above table)
 If both the minterms in the two rows are not circled, 0 is applied to the corresponding
multiplexer input.(check 3rd column in the above table)
 If the minterm in the first row alone is circled, is applied to the corresponding multiplexer
input.(check 2nd column in the above table)
 If the minterm in the second row alone is circled, is applied to the corresponding multiplexer
input.(check 1st column in the above table)

Solved problem #3
Implement the boolean expression F(A, B, C) = ∑ m(0, 2, 5, 6) using 4 : 1 multiplexer.

Solution:

In the given boolean expression, there are 3 variables. We should use 2 3 : 1 = 8 : 1 multiplexer.
But as per the question, it is to be implemented with 4 : 1 mux.

For 4 : 1 multiplexer, there should be 2 selection lines. So from the given 3 variables, the 2 least
significant variables(B, C) are used as selection line inputs.

Let us derive the four inputs of 4 : 1 multiplexer using the implementation table. The four inputs
are listed in column-wise and all the minterms are written under the four inputs in 2 rows as
shown below.

The minterms given in the boolean expression is circled and analyzed. After analyzing, the input
values of 4 : 1 mux is obtained as , A, 1, 0.

Thus the circuit can be drawn as below.

Solved problem #4

Implement F(A, B, C, D) = ∑ m(0, 1, 5, 6, 8, 10, 12, 15) using 8 : 1 multiplexer.

Solution:

In the given boolean expression, there are 4 variables. We should use 2 4 : 1 = 16 : 1 multiplexer.
But as per the question, it is to be implemented with 8 : 1 mux.

For 8 : 1 multiplexer, there should be 3 selection lines. So from the given 4 variables, the 3 least
significant variables(B, C, D) are used as selection line inputs.

The 8 inputs are derived using the implementation table shown below

From the derived input, 8 : 1 multiplexer can be drawn as below

 Type #3
In the above two types, a multiplexer circuit is derived from the given boolean expression. In type
#3, a logic function is derived from the given multiplexer circuit. Based on the given circuit, form
the truth table, from which the logical expression can be derived.

Solved problem #5
For the given multiplexer circuit, determine the logic function.

Solution:

In the given multiplexer circuit, B and C are the selection inputs. Hence the possible input
combinations are 00, 01, 10 and 11.

For these input combinations, the mux selects a particular input and gives it to the output.

That is, if BC input is 00, D0 is selected as the output. Similarly if BC = 01, D1 is selected as the
output. When the input BC = 10, D2 is selected as the output. If BC = 11, D3 is selected as the
output.

The truth table is given below.

From the truth table, the output expression can be written as,
 Its corresponding minterm expression can be written as, F = Σ m(4, 5, 3)

The obtained expression can be still minimized as below,

10. Encoder

The combinational circuits that change the binary information into N output lines are known
as Encoders. The binary information is passed in the form of 2 N input lines. The output lines define
the N-bit code for the binary information. In simple words, the Encoder performs the reverse
operation of the Decoder. At a time, only one input line is activated for simplicity. The produced N-
bit output code is equivalent to the binary information.

There are various types of encoders which are as follows:

 4 to 2 line Encoder:

In 4 to 2 line encoder, there are total of four inputs, i.e., Y 0, Y1, Y2, and Y3, and two outputs, i.e.,
A0 and A1. In 4-input lines, one input-line is set to true at a time to get the respective binary code
in the output side. Below are the block diagram and the truth table of the 4 to 2 line encoder.

Block diagram Truth Table

The logical expression of the term A0 and A1 is as follows:

A1=Y3+Y2
A0=Y3+Y1
 Logical circuit of the above expressions is given below:

 8 to 3 line Encoder:

The 8 to 3 line Encoder is also known as Octal to Binary Encoder. In 8 to 3 line encoder, there
is a total of eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and
A2. In 8-input lines, one input-line is set to true at a time to get the respective binary code in the
output side. Below are the block diagram and the truth table of the 8 to 3 line encoder.

Block diagram Truth Table

The logical expression of the term A0, A1, and A2 are as follows:

A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1

Logical circuit of the above expressions is given below:

 Decimal to BCD Encoder

The Octal to Binary Encoder is also known as 10 to 4 line Encoder. In 10 to 4 line encoder,
there are total of ten inputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, and Y9 and four outputs, i.e.,
A0, A1, A2, and A3. In 10-input lines, one input-line is set to true at a time to get the
respective BCD code in the output side. The block diagram and the truth table of the decimal to
BCD encoder are given below.

Block diagram Truth Table

The logical expression of the term A0, A1, A2, and A3 is as follows:

A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1

Logical circuit of the above expressions is given below:

 Priority Encoder:

4 to 2 line Priority Encoder:

In this priority encoder, there are total of 4 inputs, i.e., Y 0, Y1, Y2, and Y3, and two outputs, i.e.,
A0 and A1. The Y3 has high and Y0 has low priority inputs. When more than one input is '1' at the
same time, the output will be the (binary) code corresponding to the higher priority input. Below
is the truth table of the 4 to 2 line priority encoder.

Truth Table

The logical expression of the term A0 and A1 can be found using K-map as:

A1=Y3+Y2
A0=Y3+Y2'.Y1

Logical circuit of the above expressions is given below:

Uses of Encoders:

1. These systems are very easy to use in all digital systems.

2. Encoders are used to convert a decimal number into the binary number. The objective is to
perform a binary operation such as addition, subtraction, multiplication, etc.
11. Decoder

The combinational circuit that change the binary information into 2 N output lines is known
as Decoders. The binary information is passed in the form of N input lines. The output lines define
the 2N-bit code for the binary information. In simple words, the Decoder performs the reverse
operation of the Encoder. At a time, only one input line is activated for simplicity. The produced 2 N-
bit output code is equivalent to the binary information.

There are various types of decoders which are as follows:

 2 to 4 line decoder:

In the 2 to 4 line decoder, there is a total of three inputs, i.e., A 0, and A1 and E and four outputs,
i.e., Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set to 1, one of
these four outputs will be 1. The block diagram and the truth table of the 2 to 4 line decoder are
given below.

Block diagram Truth Table

The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:

Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Logical circuit of the above expressions is given below:

 3 to 8 line decoder:

The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder, there
is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and
A2. This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one
of these four outputs will be 1. The block diagram and the truth table of the 3 to 8 line encoder are
given below.

Block diagram Truth Table

The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:

Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Logical circuit of the above expressions is given below: